//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 cores b register ////
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//// 8051 cores b register ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// b register for 8051 core ////
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//// b register for 8051 core ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit, wr_addr, rd_addr, data_out);
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module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit, wr_addr, rd_addr, data_out);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
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// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
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// data_in (in) data input - used to write to b register [oc8051_alu.des1]
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// data_in (in) data input - used to write to b register [oc8051_alu.des1]
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// wr (in) write - actine high [oc8051_decoder.wr -r]
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// wr (in) write - actine high [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wr_addr (in) write address [oc8051_ram_wr_sel.out]
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// wr_addr (in) write address [oc8051_ram_wr_sel.out]
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// data_out (out) data output [oc8051_ram_sel.b_reg]
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// data_out (out) data output [oc8051_ram_sel.b_reg]
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//
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//
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input clk, rst, wr, wr_bit, bit_in;
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input clk, rst, wr, wr_bit, bit_in;
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input [2:0] rd_addr;
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input [2:0] rd_addr;
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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output bit_out;
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output bit_out;
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output [7:0] data_out;
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output [7:0] data_out;
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reg bit_out;
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reg bit_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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//
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//
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//writing to b
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//writing to b
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//must check if write high and correct address
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//must check if write high and correct address
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data_out <= #1 `OC8051_RST_B;
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data_out <= #1 `OC8051_RST_B;
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else
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else
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case ({wr, wr_bit})
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case ({wr, wr_bit})
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2'b10: begin
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2'b10: begin
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if (wr_addr==`OC8051_SFR_B)
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if (wr_addr==`OC8051_SFR_B)
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data_out <= #1 data_in;
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data_out <= #1 data_in;
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end
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end
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2'b11: begin
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2'b11: begin
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if (wr_addr[7:3]==`OC8051_SFR_B_B)
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if (wr_addr[7:3]==`OC8051_SFR_B_B)
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data_out[wr_addr[2:0]] <= #1 bit_in;
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data_out[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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endcase
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endcase
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end
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end
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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begin
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begin
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bit_out <= #1 data_out[rd_addr];
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if (rst) bit_out <= #1 1'b0;
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else bit_out <= #1 data_out[rd_addr];
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end
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end
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endmodule
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endmodule
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