//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 instruction cache ////
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//// 8051 instruction cache ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 8051 instruction cache ////
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//// 8051 instruction cache ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/04/02 11:22:15 simont
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// fix bug.
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//
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// Revision 1.4 2003/01/21 14:08:18 simont
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// Revision 1.4 2003/01/21 14:08:18 simont
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// fix bugs
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// fix bugs
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//
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//
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// Revision 1.3 2003/01/13 14:14:41 simont
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// Revision 1.3 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.2 2002/10/24 13:34:02 simont
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// Revision 1.2 2002/10/24 13:34:02 simont
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// add parameters for instruction cache
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// add parameters for instruction cache
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//
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//
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// Revision 1.1 2002/10/23 16:55:36 simont
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// Revision 1.1 2002/10/23 16:55:36 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
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module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
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dat_i, cyc_o, adr_o, ack_i, stb_o);
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dat_i, cyc_o, adr_o, ack_i, stb_o);
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//
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//
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// rst (in) reset - pin
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// rst (in) reset - pin
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// clk (in) clock - pini
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// clk (in) clock - pini
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input rst, clk;
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input rst, clk;
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//
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//
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// interface to oc8051 cpu
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// interface to oc8051 cpu
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//
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//
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// adr_i (in) address
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// adr_i (in) address
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// dat_o (out) data output
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// dat_o (out) data output
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// stb_i (in) strobe
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// stb_i (in) strobe
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// ack_o (out) acknowledge
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// ack_o (out) acknowledge
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// cyc_i (in) cycle
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// cyc_i (in) cycle
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input stb_i, cyc_i;
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input stb_i, cyc_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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output ack_o;
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output ack_o;
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output [31:0] dat_o;
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output [31:0] dat_o;
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reg [31:0] dat_o;
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reg [31:0] dat_o;
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//
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//
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// interface to instruction rom
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// interface to instruction rom
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//
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//
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// adr_o (out) address
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// adr_o (out) address
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// dat_i (in) data input
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// dat_i (in) data input
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// stb_o (out) strobe
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// stb_o (out) strobe
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// ack_i (in) acknowledge
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// ack_i (in) acknowledge
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// cyc_o (out) cycle
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// cyc_o (out) cycle
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input ack_i;
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input ack_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output stb_o, cyc_o;
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output stb_o, cyc_o;
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output [15:0] adr_o;
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output [15:0] adr_o;
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//reg [15:0] adr_o;
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//reg [15:0] adr_o;
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reg stb_o, cyc_o;
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reg stb_o, cyc_o;
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parameter ADR_WIDTH = 6; // cache address wihth
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parameter ADR_WIDTH = 6; // cache address wihth
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parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
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parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
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parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
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parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
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parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
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parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
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parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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//
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//
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// internal buffers adn wires
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// internal buffers adn wires
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//
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//
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// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
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// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
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reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
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reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
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// valid[x]=1 if block x is valid;
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// valid[x]=1 if block x is valid;
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reg [BL_NUM:0] valid;
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reg [BL_NUM:0] valid;
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// con0, con2 contain temporal control information of current address and corrent address+2
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// con0, con2 contain temporal control information of current address and corrent address+2
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// part of con_buf memory
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// part of con_buf memory
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reg [14-ADR_WIDTH:0] con0, con2;
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reg [13-ADR_WIDTH:0] con0, con2;
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//current upper address,
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//current upper address,
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reg [13-ADR_WIDTH:0] cadr0, cadr2;
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reg [13-ADR_WIDTH:0] cadr0, cadr2;
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reg stb_b;
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reg stb_b;
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// byte_select in 32 bit line (adr_i[1:0])
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// byte_select in 32 bit line (adr_i[1:0])
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reg [1:0] byte_sel;
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reg [1:0] byte_sel;
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// read cycle
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// read cycle
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reg [LINE_WIDTH-1:0] cyc;
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reg [LINE_WIDTH-1:0] cyc;
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// data input from cache ram
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// data input from cache ram
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reg [31:0] data1_i;
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reg [31:0] data1_i;
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// temporaly data from ram
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// temporaly data from ram
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reg [15:0] tmp_data1;
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reg [15:0] tmp_data1;
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reg wr1, wr1_t, stb_it;
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reg wr1, wr1_t, stb_it;
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////////////////
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reg vaild_h, vaild_l;
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wire [31:0] data0, data1_o;
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wire [31:0] data0, data1_o;
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wire cy, cy1;
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wire cy, cy1;
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wire [BL_WIDTH-1:0] adr_i2;
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wire [BL_WIDTH-1:0] adr_i2;
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wire hit, hit_l, hit_h;
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wire hit, hit_l, hit_h;
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wire [ADR_WIDTH-1:0] adr_r, addr1;
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wire [ADR_WIDTH-1:0] adr_r, addr1;
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reg [ADR_WIDTH-1:0] adr_w;
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reg [ADR_WIDTH-1:0] adr_w;
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reg [15:0] mis_adr;
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reg [15:0] mis_adr;
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wire [15:0] data1;
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wire [15:0] data1;
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wire [LINE_WIDTH-1:0] adr_r1;
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wire [LINE_WIDTH-1:0] adr_r1;
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assign cy = &adr_i[LINE_WIDTH+1:1];
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assign cy = &adr_i[LINE_WIDTH+1:1];
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assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
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assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
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assign hit_l =(con0=={cadr0,1'b1});
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assign hit_l = (con0==cadr0) & vaild_l;
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assign hit_h =(con2=={cadr2,1'b1});
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assign hit_h = (con2==cadr2) & vaild_h;
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assign hit = hit_l && hit_h;
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assign hit = hit_l && hit_h;
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assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
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assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
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assign addr1 = wr1 ? adr_w : adr_r;
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assign addr1 = wr1 ? adr_w : adr_r;
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assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
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assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
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//assign ack_o = hit;
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assign ack_o = hit && stb_it;
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assign ack_o = hit && stb_it;
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
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assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
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assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
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oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
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.wr1(wr1));
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.wr1(wr1));
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defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
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defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
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defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
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defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
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/*
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generic_dpram #(ADR_WIDTH, 32) oc8051_cache_ram1(
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.rclk ( clk ),
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( adr_i[ADR_WIDTH+1:2] ),
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.do ( data0 ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr1 ),
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.waddr ( addr1 ),
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.di ( data1_i )
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);
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*/
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always @(stb_b or data0 or data1 or byte_sel)
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always @(stb_b or data0 or data1 or byte_sel)
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begin
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begin
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if (stb_b) begin
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if (stb_b) begin
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case (byte_sel)
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case (byte_sel)
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2'b00 : dat_o = data0;
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2'b00 : dat_o = data0;
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2'b01 : dat_o = {data0[23:0], data1[15:8]};
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2'b01 : dat_o = {data0[23:0], data1[15:8]};
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2'b10 : dat_o = {data0[15:0], data1};
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2'b10 : dat_o = {data0[15:0], data1};
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default: dat_o = {data0[ 7:0], data1, 8'h00};
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default: dat_o = {data0[ 7:0], data1, 8'h00};
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endcase
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endcase
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end else begin
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end else begin
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dat_o = 32'h0;
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dat_o = 32'h0;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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con0 <= #1 9'h0;
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con0 <= #1 9'h0;
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con2 <= #1 9'h0;
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con2 <= #1 9'h0;
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vaild_h <= #1 1'b0;
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vaild_l <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
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con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
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con2 <= #1 {con_buf[adr_i2], valid[adr_i2]};
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con2 <= #1 {con_buf[adr_i2]};
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vaild_l <= #1 valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]];
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vaild_h <= #1 valid[adr_i2];
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cadr0 <= #1 8'h00;
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cadr0 <= #1 8'h00;
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cadr2 <= #1 8'h00;
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cadr2 <= #1 8'h00;
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end else begin
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end else begin
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cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
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cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
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cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
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cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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stb_b <= #1 1'b0;
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stb_b <= #1 1'b0;
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byte_sel <= #1 2'b00;
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byte_sel <= #1 2'b00;
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end else begin
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end else begin
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stb_b <= #1 stb_i;
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stb_b <= #1 stb_i;
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byte_sel <= #1 adr_i[1:0];
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byte_sel <= #1 adr_i[1:0];
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
|
begin
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if (rst)
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if (rst)
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begin
|
begin
|
cyc <= #1 2'b00;
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cyc <= #1 2'b00;
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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data1_i<= #1 32'h0;
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data1_i<= #1 32'h0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
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adr_w <= #1 6'h0;
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adr_w <= #1 6'h0;
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valid <= #1 16'h0;
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valid <= #1 16'h0;
|
end
|
end
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else if (stb_b && !hit && !stb_o && !wr1)
|
else if (stb_b && !hit && !stb_o && !wr1)
|
begin
|
begin
|
cyc <= #1 2'b00;
|
cyc <= #1 2'b00;
|
cyc_o <= #1 1'b1;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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data1_i <= #1 32'h0;
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data1_i <= #1 32'h0;
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wr1 <= #1 1'b0;
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wr1 <= #1 1'b0;
|
end
|
end
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else if (stb_o && ack_i)
|
else if (stb_o && ack_i)
|
begin
|
begin
|
data1_i<= #1 dat_i;
|
data1_i<= #1 dat_i;
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wr1 <= #1 1'b1;
|
wr1 <= #1 1'b1;
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adr_w <= #1 adr_o[ADR_WIDTH+1:2];
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adr_w <= #1 adr_o[ADR_WIDTH+1:2];
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|
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if (&cyc)
|
if (&cyc)
|
begin
|
begin
|
cyc <= #1 2'b00;
|
cyc <= #1 2'b00;
|
cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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// con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cyc <= #1 cyc + 1'b1;
|
cyc <= #1 cyc + 1'b1;
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b0;
|
end
|
end
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|
|
/* case (cyc)
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|
2'b00: begin
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cyc <= #1 2'b01;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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end
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|
2'b01: begin
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cyc <= #1 2'b10;
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cyc_o <= #1 1'b1;
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stb_o <= #1 1'b1;
|
|
end
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|
2'b10: begin
|
|
cyc <= #1 2'b11;
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|
cyc_o <= #1 1'b1;
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|
stb_o <= #1 1'b1;
|
|
end
|
|
default: begin
|
|
cyc <= #1 2'b00;
|
|
cyc_o <= #1 1'b0;
|
|
stb_o <= #1 1'b0;
|
|
con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
|
|
valid[mis_adr[7:4]] <= #1 1'b1;
|
|
end
|
|
endcase*/
|
|
end
|
end
|
else
|
else
|
wr1 <= #1 1'b0;
|
wr1 <= #1 1'b0;
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end
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end
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|
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//rih
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//rih
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always @(posedge clk)
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always @(posedge clk)
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if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )
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if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )
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con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
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con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
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|
|
|
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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mis_adr <= #1 1'b0;
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mis_adr <= #1 1'b0;
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else if (!hit_l)
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else if (!hit_l)
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mis_adr <= #1 adr_i;
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mis_adr <= #1 adr_i;
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else if (!hit_h)
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else if (!hit_h)
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mis_adr <= #1 adr_i+'d2;
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mis_adr <= #1 adr_i+'d2;
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end
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end
|
|
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always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
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begin
|
begin
|
if (rst)
|
if (rst)
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tmp_data1 <= #1 1'b0;
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tmp_data1 <= #1 1'b0;
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else if (!hit_h && wr1 && (cyc==adr_r1))
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else if (!hit_h && wr1 && (cyc==adr_r1))
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tmp_data1 <= #1 dat_i[31:16];
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tmp_data1 <= #1 dat_i[31:16];
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else if (!hit_l && hit_h && wr1)
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else if (!hit_l && hit_h && wr1)
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tmp_data1 <= #1 data1_o[31:16];
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tmp_data1 <= #1 data1_o[31:16];
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end
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end
|
|
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always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
wr1_t <= #1 1'b0;
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wr1_t <= #1 1'b0;
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stb_it <= #1 1'b0;
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stb_it <= #1 1'b0;
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end else begin
|
end else begin
|
wr1_t <= #1 wr1;
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wr1_t <= #1 wr1;
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stb_it <= #1 stb_i;
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stb_it <= #1 stb_i;
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end
|
end
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end
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end
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|
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endmodule
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endmodule
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