//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// 8051 indirect address ////
|
//// 8051 indirect address ////
|
//// ////
|
//// ////
|
//// This file is part of the 8051 cores project ////
|
//// This file is part of the 8051 cores project ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Contains ragister 0 and register 1. used for indirrect ////
|
//// Contains ragister 0 and register 1. used for indirrect ////
|
//// addressing. ////
|
//// addressing. ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.6 2003/05/05 15:46:37 simont
|
// Revision 1.6 2003/05/05 15:46:37 simont
|
// add aditional alu destination to solve critical path.
|
// add aditional alu destination to solve critical path.
|
//
|
//
|
// Revision 1.5 2003/01/13 14:14:41 simont
|
// Revision 1.5 2003/01/13 14:14:41 simont
|
// replace some modules
|
// replace some modules
|
//
|
//
|
// Revision 1.4 2002/09/30 17:33:59 simont
|
// Revision 1.4 2002/09/30 17:33:59 simont
|
// prepared header
|
// prepared header
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "oc8051_timescale.v"
|
`include "oc8051_timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
|
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
|
//
|
//
|
|
|
|
|
input clk, // clock
|
input clk, // clock
|
rst, // reset
|
rst, // reset
|
wr, // write
|
wr, // write
|
sel, // select register
|
sel, // select register
|
wr_bit; // write bit addressable
|
wr_bit; // write bit addressable
|
input [1:0] bank; // select register bank
|
input [1:0] bank; // select register bank
|
input [7:0] data_in; // data input
|
input [7:0] data_in; // data input
|
input [7:0] wr_addr; // write address
|
input [7:0] wr_addr; // write address
|
|
|
output [7:0] ri_out;
|
output [7:0] ri_out;
|
|
|
//reg [7:0] buff [31:0];
|
//reg [7:0] buff [31:0];
|
reg wr_bit_r;
|
reg wr_bit_r;
|
|
|
|
|
reg [7:0] buff [0:7];
|
reg [7:0] buff [0:7];
|
|
|
//
|
//
|
//write to buffer
|
//write to buffer
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
buff[3'b000] <= #1 8'h00;
|
buff[3'b000] <= #1 8'h00;
|
buff[3'b001] <= #1 8'h00;
|
buff[3'b001] <= #1 8'h00;
|
buff[3'b010] <= #1 8'h00;
|
buff[3'b010] <= #1 8'h00;
|
buff[3'b011] <= #1 8'h00;
|
buff[3'b011] <= #1 8'h00;
|
buff[3'b100] <= #1 8'h00;
|
buff[3'b100] <= #1 8'h00;
|
buff[3'b101] <= #1 8'h00;
|
buff[3'b101] <= #1 8'h00;
|
buff[3'b110] <= #1 8'h00;
|
buff[3'b110] <= #1 8'h00;
|
buff[3'b111] <= #1 8'h00;
|
buff[3'b111] <= #1 8'h00;
|
end else begin
|
end else begin
|
if ((wr) & !(wr_bit_r)) begin
|
if ((wr) & !(wr_bit_r)) begin
|
case (wr_addr) /* synopsys full_case parallel_case */
|
case (wr_addr) /* synopsys full_case parallel_case */
|
8'h00: buff[3'b000] <= #1 data_in;
|
8'h00: buff[3'b000] <= #1 data_in;
|
8'h01: buff[3'b001] <= #1 data_in;
|
8'h01: buff[3'b001] <= #1 data_in;
|
8'h08: buff[3'b010] <= #1 data_in;
|
8'h08: buff[3'b010] <= #1 data_in;
|
8'h09: buff[3'b011] <= #1 data_in;
|
8'h09: buff[3'b011] <= #1 data_in;
|
8'h10: buff[3'b100] <= #1 data_in;
|
8'h10: buff[3'b100] <= #1 data_in;
|
8'h11: buff[3'b101] <= #1 data_in;
|
8'h11: buff[3'b101] <= #1 data_in;
|
8'h18: buff[3'b110] <= #1 data_in;
|
8'h18: buff[3'b110] <= #1 data_in;
|
8'h19: buff[3'b111] <= #1 data_in;
|
8'h19: buff[3'b111] <= #1 data_in;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
//read from buffer
|
//read from buffer
|
|
|
assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
|
assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
|
data_in : buff[{bank, sel}];
|
data_in : buff[{bank, sel}];
|
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
wr_bit_r <= #1 1'b0;
|
wr_bit_r <= #1 1'b0;
|
end else begin
|
end else begin
|
wr_bit_r <= #1 wr_bit;
|
wr_bit_r <= #1 wr_bit;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|