//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// 8051 cores interrupt control module ////
|
//// 8051 cores interrupt control module ////
|
//// ////
|
//// ////
|
//// This file is part of the 8051 cores project ////
|
//// This file is part of the 8051 cores project ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// contains sfr's: tcon, ip, ie; ////
|
//// contains sfr's: tcon, ip, ie; ////
|
//// interrupt handling ////
|
//// interrupt handling ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// Nothing ////
|
//// Nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Jaka Simsic, jakas@opencores.org ////
|
//// - Jaka Simsic, jakas@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2003/01/13 14:14:41 simont
|
|
// replace some modules
|
|
//
|
// Revision 1.5 2002/09/30 17:33:59 simont
|
// Revision 1.5 2002/09/30 17:33:59 simont
|
// prepared header
|
// prepared header
|
//
|
//
|
//
|
//
|
|
|
|
|
`include "oc8051_defines.v"
|
`include "oc8051_defines.v"
|
|
|
//synopsys translate_off
|
//synopsys translate_off
|
`include "oc8051_timescale.v"
|
`include "oc8051_timescale.v"
|
//synopsys translate_on
|
//synopsys translate_on
|
|
|
|
|
|
|
module oc0851_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
|
module oc8051_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
|
//timer interrupts
|
//timer interrupts
|
tf0, tf1, t2_int,
|
tf0, tf1, t2_int,
|
tr0, tr1,
|
tr0, tr1,
|
//external interrupts
|
//external interrupts
|
ie0, ie1,
|
ie0, ie1,
|
//uart interrupts
|
//uart interrupts
|
uart_int,
|
uart_int,
|
//to cpu
|
//to cpu
|
intr, reti, int_vec, ack);
|
intr, reti, int_vec, ack);
|
|
|
input [7:0] wr_addr, data_in, rd_addr;
|
input [7:0] wr_addr, data_in, rd_addr;
|
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
|
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
|
|
|
output tr0, tr1, intr, bit_out;
|
output tr0, tr1, intr, bit_out;
|
output [7:0] int_vec, data_out;
|
output [7:0] int_vec, data_out;
|
|
|
reg [7:0] ip, ie, int_vec, data_out;
|
reg [7:0] ip, ie, int_vec, data_out;
|
|
|
reg [3:0] tcon_s;
|
reg [3:0] tcon_s;
|
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
|
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
|
wire [7:0] tcon;
|
wire [7:0] tcon;
|
|
|
//
|
//
|
// isrc processing interrupt sources
|
// isrc processing interrupt sources
|
// int_dept
|
// int_dept
|
wire [2:0] isrc_cur;
|
wire [2:0] isrc_cur;
|
reg [2:0] isrc [1:0];
|
reg [2:0] isrc [1:0];
|
reg int_dept;
|
reg int_dept;
|
wire int_dept_1;
|
wire int_dept_1;
|
reg int_proc;
|
reg int_proc;
|
reg [1:0] int_lev [1:0];
|
reg [1:0] int_lev [1:0];
|
wire cur_lev;
|
wire cur_lev;
|
|
|
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
|
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
|
assign int_dept_1 = int_dept - 1'b1;
|
assign int_dept_1 = int_dept - 1'b1;
|
assign cur_lev = int_lev[int_dept_1];
|
assign cur_lev = int_lev[int_dept_1];
|
|
|
//
|
//
|
// contains witch level of interrupts is running
|
// contains witch level of interrupts is running
|
//reg [1:0] int_levl, int_levl_w;
|
//reg [1:0] int_levl, int_levl_w;
|
|
|
//
|
//
|
// int_ln waiting interrupts on level n
|
// int_ln waiting interrupts on level n
|
// ip_ln interrupts on level n
|
// ip_ln interrupts on level n
|
// int_src interrupt sources
|
// int_src interrupt sources
|
wire [5:0] int_l0, int_l1;
|
wire [5:0] int_l0, int_l1;
|
wire [5:0] ip_l0, ip_l1;
|
wire [5:0] ip_l0, ip_l1;
|
wire [5:0] int_src;
|
wire [5:0] int_src;
|
wire il0, il1;
|
wire il0, il1;
|
|
|
|
|
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
|
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
|
|
|
//
|
//
|
//interrupt priority
|
//interrupt priority
|
assign ip_l0 = ~ip[5:0];
|
assign ip_l0 = ~ip[5:0];
|
assign ip_l1 = ip[5:0];
|
assign ip_l1 = ip[5:0];
|
|
|
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
|
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
|
|
|
//
|
//
|
// waiting interrupts
|
// waiting interrupts
|
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
|
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
|
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
|
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
|
assign il0 = |int_l0;
|
assign il0 = |int_l0;
|
assign il1 = |int_l1;
|
assign il1 = |int_l1;
|
|
|
//
|
//
|
// TCON
|
// TCON
|
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
|
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
|
assign tr0 = tcon_s[2];
|
assign tr0 = tcon_s[2];
|
assign tr1 = tcon_s[3];
|
assign tr1 = tcon_s[3];
|
assign intr = |int_vec;
|
assign intr = |int_vec;
|
|
|
|
|
//
|
//
|
// IP
|
// IP
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
ip <=#1 `OC8051_RST_IP;
|
ip <=#1 `OC8051_RST_IP;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
|
ip <= #1 data_in;
|
ip <= #1 data_in;
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
|
ip[wr_addr[2:0]] <= #1 bit_in;
|
ip[wr_addr[2:0]] <= #1 bit_in;
|
end
|
end
|
|
|
//
|
//
|
// IE
|
// IE
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
ie <=#1 `OC8051_RST_IE;
|
ie <=#1 `OC8051_RST_IE;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
|
ie <= #1 data_in;
|
ie <= #1 data_in;
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
|
ie[wr_addr[2:0]] <= #1 bit_in;
|
ie[wr_addr[2:0]] <= #1 bit_in;
|
end
|
end
|
|
|
//
|
//
|
// tcon_s
|
// tcon_s
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
tcon_s <=#1 4'b0000;
|
tcon_s <=#1 4'b0000;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
|
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
|
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
|
case (wr_addr[2:0])
|
case (wr_addr[2:0])
|
3'b000: tcon_s[0] <= #1 bit_in;
|
3'b000: tcon_s[0] <= #1 bit_in;
|
3'b010: tcon_s[1] <= #1 bit_in;
|
3'b010: tcon_s[1] <= #1 bit_in;
|
3'b100: tcon_s[2] <= #1 bit_in;
|
3'b100: tcon_s[2] <= #1 bit_in;
|
3'b110: tcon_s[3] <= #1 bit_in;
|
3'b110: tcon_s[3] <= #1 bit_in;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// tf1 (tmod.7)
|
// tf1 (tmod.7)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
tcon_tf1 <=#1 1'b0;
|
tcon_tf1 <=#1 1'b0;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
tcon_tf1 <= #1 data_in[7];
|
tcon_tf1 <= #1 data_in[7];
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
|
tcon_tf1 <= #1 bit_in;
|
tcon_tf1 <= #1 bit_in;
|
end else if (!(tf1_buff) & (tf1)) begin
|
end else if (!(tf1_buff) & (tf1)) begin
|
tcon_tf1 <= #1 1'b1;
|
tcon_tf1 <= #1 1'b1;
|
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
|
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
|
tcon_tf1 <= #1 1'b0;
|
tcon_tf1 <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// tf0 (tmod.5)
|
// tf0 (tmod.5)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
tcon_tf0 <=#1 1'b0;
|
tcon_tf0 <=#1 1'b0;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
tcon_tf0 <= #1 data_in[5];
|
tcon_tf0 <= #1 data_in[5];
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
|
tcon_tf0 <= #1 bit_in;
|
tcon_tf0 <= #1 bit_in;
|
end else if (!(tf0_buff) & (tf0)) begin
|
end else if (!(tf0_buff) & (tf0)) begin
|
tcon_tf0 <= #1 1'b1;
|
tcon_tf0 <= #1 1'b1;
|
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
|
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
|
tcon_tf0 <= #1 1'b0;
|
tcon_tf0 <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
// ie0 (tmod.1)
|
// ie0 (tmod.1)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
tcon_ie0 <=#1 1'b0;
|
tcon_ie0 <=#1 1'b0;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
tcon_ie0 <= #1 data_in[1];
|
tcon_ie0 <= #1 data_in[1];
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
|
tcon_ie0 <= #1 bit_in;
|
tcon_ie0 <= #1 bit_in;
|
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
|
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
|
tcon_ie0 <= #1 1'b1;
|
tcon_ie0 <= #1 1'b1;
|
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
|
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
|
tcon_ie0 <= #1 1'b0;
|
tcon_ie0 <= #1 1'b0;
|
end else if (!(tcon_s[0]) & (ie0)) begin
|
end else if (!(tcon_s[0]) & (ie0)) begin
|
tcon_ie0 <= #1 1'b0;
|
tcon_ie0 <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
// ie1 (tmod.3)
|
// ie1 (tmod.3)
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
|
// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
|
tcon_ie1 <=#1 1'b0;
|
tcon_ie1 <=#1 1'b0;
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
|
tcon_ie1 <= #1 data_in[3];
|
tcon_ie1 <= #1 data_in[3];
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
|
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
|
tcon_ie1 <= #1 bit_in;
|
tcon_ie1 <= #1 bit_in;
|
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
|
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
|
tcon_ie1 <= #1 1'b1;
|
tcon_ie1 <= #1 1'b1;
|
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
|
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
|
tcon_ie1 <= #1 1'b0;
|
tcon_ie1 <= #1 1'b0;
|
end else if (!(tcon_s[1]) & (ie1)) begin
|
end else if (!(tcon_s[1]) & (ie1)) begin
|
tcon_ie1 <= #1 1'b0;
|
tcon_ie1 <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// interrupt processing
|
// interrupt processing
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
int_vec <= #1 8'h00;
|
int_vec <= #1 8'h00;
|
int_dept <= #1 1'b0;
|
int_dept <= #1 1'b0;
|
isrc[0] <= #1 3'h0;
|
isrc[0] <= #1 3'h0;
|
isrc[1] <= #1 3'h0;
|
isrc[1] <= #1 3'h0;
|
int_proc <= #1 1'b0;
|
int_proc <= #1 1'b0;
|
int_lev[0] <= #1 1'b0;
|
int_lev[0] <= #1 1'b0;
|
int_lev[1] <= #1 1'b0;
|
int_lev[1] <= #1 1'b0;
|
end else if (reti) begin // return from interrupt
|
end else if (reti) begin // return from interrupt
|
if (int_dept==2'b01)
|
if (int_dept==2'b01)
|
int_proc <= #1 1'b0;
|
int_proc <= #1 1'b0;
|
int_dept <= #1 int_dept - 2'b01;
|
int_dept <= #1 int_dept - 2'b01;
|
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
|
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
|
int_proc <= #1 1'b1;
|
int_proc <= #1 1'b1;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
|
int_dept <= #1 int_dept + 2'b01;
|
int_dept <= #1 int_dept + 2'b01;
|
if (int_l1[0]) begin
|
if (int_l1[0]) begin
|
int_vec <= #1 `OC8051_INT_X0;
|
int_vec <= #1 `OC8051_INT_X0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
end else if (int_l1[1]) begin
|
end else if (int_l1[1]) begin
|
int_vec <= #1 `OC8051_INT_T0;
|
int_vec <= #1 `OC8051_INT_T0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
end else if (int_l1[2]) begin
|
end else if (int_l1[2]) begin
|
int_vec <= #1 `OC8051_INT_X1;
|
int_vec <= #1 `OC8051_INT_X1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
end else if (int_l1[3]) begin
|
end else if (int_l1[3]) begin
|
int_vec <= #1 `OC8051_INT_T1;
|
int_vec <= #1 `OC8051_INT_T1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
end else if (int_l1[4]) begin
|
end else if (int_l1[4]) begin
|
int_vec <= #1 `OC8051_INT_UART;
|
int_vec <= #1 `OC8051_INT_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
end else if (int_l1[5]) begin
|
end else if (int_l1[5]) begin
|
int_vec <= #1 `OC8051_INT_T2;
|
int_vec <= #1 `OC8051_INT_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
end
|
end
|
|
|
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
|
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
|
int_proc <= #1 1'b1;
|
int_proc <= #1 1'b1;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
|
int_dept <= #1 int_dept + 2'b01;
|
int_dept <= #1 int_dept + 2'b01;
|
if (int_l0[0]) begin
|
if (int_l0[0]) begin
|
int_vec <= #1 `OC8051_INT_X0;
|
int_vec <= #1 `OC8051_INT_X0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
end else if (int_l0[1]) begin
|
end else if (int_l0[1]) begin
|
int_vec <= #1 `OC8051_INT_T0;
|
int_vec <= #1 `OC8051_INT_T0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
end else if (int_l0[2]) begin
|
end else if (int_l0[2]) begin
|
int_vec <= #1 `OC8051_INT_X1;
|
int_vec <= #1 `OC8051_INT_X1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
end else if (int_l0[3]) begin
|
end else if (int_l0[3]) begin
|
int_vec <= #1 `OC8051_INT_T1;
|
int_vec <= #1 `OC8051_INT_T1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
end else if (int_l0[4]) begin
|
end else if (int_l0[4]) begin
|
int_vec <= #1 `OC8051_INT_UART;
|
int_vec <= #1 `OC8051_INT_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
end else if (int_l0[5]) begin
|
end else if (int_l0[5]) begin
|
int_vec <= #1 `OC8051_INT_T2;
|
int_vec <= #1 `OC8051_INT_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
end
|
end
|
end else begin
|
end else begin
|
int_vec <= #1 8'h00;
|
int_vec <= #1 8'h00;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) data_out <= #1 8'h0;
|
if (rst) data_out <= #1 8'h0;
|
else if (wr & !wr_bit & (wr_addr==rd_addr) & (
|
else if (wr & !wr_bit & (wr_addr==rd_addr) & (
|
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
|
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
|
data_out <= #1 data_in;
|
data_out <= #1 data_in;
|
end else begin
|
end else begin
|
case (rd_addr)
|
case (rd_addr)
|
`OC8051_SFR_IP: data_out <= #1 ip;
|
`OC8051_SFR_IP: data_out <= #1 ip;
|
`OC8051_SFR_IE: data_out <= #1 ie0;
|
`OC8051_SFR_IE: data_out <= #1 ie0;
|
default: data_out <= #1 tcon;
|
default: data_out <= #1 tcon;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
tf0_buff <= #1 1'b0;
|
tf0_buff <= #1 1'b0;
|
tf1_buff <= #1 1'b0;
|
tf1_buff <= #1 1'b0;
|
ie0_buff <= #1 1'b0;
|
ie0_buff <= #1 1'b0;
|
ie1_buff <= #1 1'b0;
|
ie1_buff <= #1 1'b0;
|
end else begin
|
end else begin
|
tf0_buff <= #1 tf0;
|
tf0_buff <= #1 tf0;
|
tf1_buff <= #1 tf1;
|
tf1_buff <= #1 tf1;
|
ie0_buff <= #1 ie0;
|
ie0_buff <= #1 ie0;
|
ie1_buff <= #1 ie1;
|
ie1_buff <= #1 ie1;
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) bit_out <= #1 1'b0;
|
if (rst) bit_out <= #1 1'b0;
|
else if (wr & wr_bit & (wr_addr==rd_addr)) begin
|
else if (wr & wr_bit & (wr_addr==rd_addr)) begin
|
bit_out <= #1 bit_in;
|
bit_out <= #1 bit_in;
|
end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
|
end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
|
bit_out <= #1 data_in[rd_addr[2:0]];
|
bit_out <= #1 data_in[rd_addr[2:0]];
|
end else begin
|
end else begin
|
case (rd_addr[7:3])
|
case (rd_addr[7:3])
|
`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
|
`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
|
`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
|
`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
|
default: bit_out <= #1 tcon[rd_addr[2:0]];
|
default: bit_out <= #1 tcon[rd_addr[2:0]];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|