//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 cache ram ////
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//// 8051 cache ram ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 64x31 dual port ram ////
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//// 64x31 dual port ram ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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//
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//
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// duble port ram
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// duble port ram
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//
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//
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module oc8051_ram_64x32_dual_bist (
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module oc8051_ram_64x32_dual_bist (
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clk,
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clk,
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rst,
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rst,
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adr0,
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adr0,
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dat0_o,
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dat0_o,
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en0,
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en0,
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adr1,
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adr1,
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dat1_i,
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dat1_i,
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dat1_o,
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dat1_o,
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en1,
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en1,
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wr1
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wr1
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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,
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,
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scanb_rst,
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scanb_rst,
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scanb_clk,
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scanb_clk,
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scanb_si,
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scanb_si,
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scanb_so,
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scanb_so,
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scanb_en
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scanb_en
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`endif
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`endif
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);
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);
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parameter ADR_WIDTH = 6;
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parameter ADR_WIDTH = 6;
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input clk,
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input clk,
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wr1,
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wr1,
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rst,
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rst,
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en0,
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en0,
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en1;
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en1;
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input [7:0] dat1_i;
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input [7:0] dat1_i;
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input [ADR_WIDTH-1:0] adr0,
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input [ADR_WIDTH-1:0] adr0,
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adr1;
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adr1;
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output [7:0] dat0_o,
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output [7:0] dat0_o,
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dat1_o;
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dat1_o;
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reg [7:0] rd_data;
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reg [7:0] rd_data;
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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input scanb_rst;
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input scanb_rst;
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input scanb_clk;
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input scanb_clk;
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input scanb_si;
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input scanb_si;
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output scanb_so;
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output scanb_so;
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input scanb_en;
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input scanb_en;
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`endif
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`endif
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`ifdef OC8051_RAM_XILINX
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`ifdef OC8051_RAM_XILINX
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xilinx_ram_dp xilinx_ram(
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xilinx_ram_dp xilinx_ram(
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// read port
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// read port
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.CLKA(clk),
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.CLKA(clk),
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.RSTA(rst),
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.RSTA(rst),
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.ENA(en0),
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.ENA(en0),
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.ADDRA(adr0),
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.ADDRA(adr0),
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.DIA(32'h00),
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.DIA(32'h00),
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.WEA(1'b0),
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.WEA(1'b0),
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.DOA(dat0_o),
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.DOA(dat0_o),
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// write port
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// write port
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.CLKB(clk),
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.CLKB(clk),
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.RSTB(rst),
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.RSTB(rst),
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.ENB(en1),
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.ENB(en1),
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.ADDRB(adr1),
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.ADDRB(adr1),
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.DIB(dat1_i),
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.DIB(dat1_i),
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.WEB(wr1),
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.WEB(wr1),
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.DOB(dat1_o)
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.DOB(dat1_o)
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);
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);
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defparam
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defparam
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xilinx_ram.dwidth = 32,
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xilinx_ram.dwidth = 32,
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xilinx_ram.awidth = ADR_WIDTH;
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xilinx_ram.awidth = ADR_WIDTH;
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`else
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`else
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`ifdef OC8051_RAM_VIRTUALSILICON
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`ifdef OC8051_RAM_VIRTUALSILICON
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`else
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`else
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`ifdef OC8051_RAM_GENERIC
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`ifdef OC8051_RAM_GENERIC
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generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(
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generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(
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.rclk ( clk ),
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.rclk ( clk ),
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.rrst ( rst ),
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.rrst ( rst ),
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.rce ( en0 ),
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.rce ( en0 ),
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.oe ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( adr0 ),
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.raddr ( adr0 ),
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.do ( dat0_o ),
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.do ( dat0_o ),
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.wclk ( clk ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wrst ( rst ),
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.wce ( en1 ),
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.wce ( en1 ),
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.we ( wr1 ),
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.we ( wr1 ),
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.waddr ( adr1 ),
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.waddr ( adr1 ),
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.di ( dat1_i )
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.di ( dat1_i )
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);
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);
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`else
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`else
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reg [31:0] dat1_o,
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reg [31:0] dat1_o,
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dat0_o;
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dat0_o;
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//
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//
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// buffer
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// buffer
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reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
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reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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dat1_o <= #1 32'h0;
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dat1_o <= #1 32'h0;
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else if (wr1) begin
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else if (wr1) begin
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buff[adr1] <= #1 dat1_i;
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buff[adr1] <= #1 dat1_i;
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dat1_o <= #1 dat1_i;
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dat1_o <= #1 dat1_i;
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end else
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end else
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dat1_o <= #1 buff[adr1];
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dat1_o <= #1 buff[adr1];
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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dat0_o <= #1 32'h0;
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dat0_o <= #1 32'h0;
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else if ((adr0==adr1) & wr1)
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else if ((adr0==adr1) & wr1)
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dat0_o <= #1 dat1_i;
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dat0_o <= #1 dat1_i;
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else
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else
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dat0_o <= #1 buff[adr0];
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dat0_o <= #1 buff[adr0];
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end
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end
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`endif //OC8051_RAM_GENERIC
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`endif //OC8051_RAM_GENERIC
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`endif //OC8051_RAM_VIRTUALSILICON
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`endif //OC8051_RAM_VIRTUALSILICON
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`endif //OC8051_RAM_XILINX
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`endif //OC8051_RAM_XILINX
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endmodule
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endmodule
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