//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 cores top level module ////
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//// 8051 cores top level module ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 8051 definitions. ////
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//// 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.32 2003/06/20 13:36:37 simont
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// ram modules added.
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//
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// Revision 1.31 2003/06/17 14:17:22 simont
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// Revision 1.31 2003/06/17 14:17:22 simont
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// BIST signals added.
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// BIST signals added.
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//
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//
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// Revision 1.30 2003/06/03 16:51:24 simont
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// Revision 1.30 2003/06/03 16:51:24 simont
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// include "8051_defines" added.
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// include "8051_defines" added.
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//
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//
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// Revision 1.29 2003/05/07 12:36:03 simont
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// Revision 1.29 2003/05/07 12:36:03 simont
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// chsnge comp.des to des1
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// chsnge comp.des to des1
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//
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//
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// Revision 1.28 2003/05/06 09:41:35 simont
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// Revision 1.28 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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//
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//
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// Revision 1.27 2003/05/05 15:46:37 simont
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// Revision 1.27 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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//
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//
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// Revision 1.26 2003/04/29 11:24:31 simont
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// Revision 1.26 2003/04/29 11:24:31 simont
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// fix bug in case execution of two data dependent instructions.
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// fix bug in case execution of two data dependent instructions.
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//
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//
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// Revision 1.25 2003/04/25 17:15:51 simont
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// Revision 1.25 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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//
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//
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// Revision 1.24 2003/04/11 10:05:59 simont
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// Revision 1.24 2003/04/11 10:05:59 simont
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// deifne OC8051_ROM added
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// deifne OC8051_ROM added
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//
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//
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// Revision 1.23 2003/04/10 12:43:19 simont
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// Revision 1.23 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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// defines for pherypherals added
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//
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//
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// Revision 1.22 2003/04/09 16:24:04 simont
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// Revision 1.22 2003/04/09 16:24:04 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.21 2003/04/09 15:49:42 simont
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// Revision 1.21 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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//
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Include instruction cache.
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// Include instruction cache.
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//
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//
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// Revision 1.19 2003/04/02 15:08:30 simont
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// Revision 1.19 2003/04/02 15:08:30 simont
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// raname signals.
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// raname signals.
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//
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//
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// Revision 1.18 2003/01/13 14:14:41 simont
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// Revision 1.18 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.17 2002/11/05 17:23:54 simont
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// Revision 1.17 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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//
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//
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// Revision 1.16 2002/10/28 14:55:00 simont
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// Revision 1.16 2002/10/28 14:55:00 simont
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// fix bug in interface to external data ram
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// fix bug in interface to external data ram
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//
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//
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// Revision 1.15 2002/10/23 16:53:39 simont
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// Revision 1.15 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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//
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//
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// Revision 1.14 2002/10/17 18:50:00 simont
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// Revision 1.14 2002/10/17 18:50:00 simont
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// cahnge interface to instruction rom
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// cahnge interface to instruction rom
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//
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//
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// Revision 1.13 2002/09/30 17:33:59 simont
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// Revision 1.13 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_top (wb_rst_i, wb_clk_i,
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module oc8051_top (wb_rst_i, wb_clk_i,
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//interface to instruction rom
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//interface to instruction rom
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wbi_adr_o,
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wbi_adr_o,
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wbi_dat_i,
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wbi_dat_i,
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wbi_stb_o,
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wbi_stb_o,
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wbi_ack_i,
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wbi_ack_i,
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wbi_cyc_o,
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wbi_cyc_o,
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wbi_err_i,
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wbi_err_i,
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//interface to data ram
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//interface to data ram
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wbd_dat_i,
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wbd_dat_i,
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wbd_dat_o,
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wbd_dat_o,
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wbd_adr_o,
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wbd_adr_o,
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wbd_we_o,
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wbd_we_o,
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wbd_ack_i,
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wbd_ack_i,
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wbd_stb_o,
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wbd_stb_o,
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wbd_cyc_o,
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wbd_cyc_o,
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wbd_err_i,
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wbd_err_i,
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// interrupt interface
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// interrupt interface
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int0_i,
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int0_i,
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int1_i,
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int1_i,
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// port interface
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// port interface
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_i,
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p0_i,
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p0_o,
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p0_o,
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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p1_i,
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p1_i,
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p1_o,
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p1_o,
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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p2_i,
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p2_i,
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p2_o,
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p2_o,
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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p3_i,
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p3_i,
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p3_o,
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p3_o,
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`endif
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`endif
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`endif
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`endif
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// serial interface
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// serial interface
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`ifdef OC8051_UART
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`ifdef OC8051_UART
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rxd_i, txd_o,
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rxd_i, txd_o,
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`endif
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`endif
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// counter interface
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// counter interface
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`ifdef OC8051_TC01
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`ifdef OC8051_TC01
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t0_i, t1_i,
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t0_i, t1_i,
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`endif
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`endif
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`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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t2_i, t2ex_i,
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t2_i, t2ex_i,
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`endif
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`endif
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// BIST
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// BIST
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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scanb_rst,
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scanb_rst,
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scanb_clk,
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scanb_clk,
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scanb_si,
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scanb_si,
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scanb_so,
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scanb_so,
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scanb_en,
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scanb_en,
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`endif
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`endif
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// external access (active low)
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// external access (active low)
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ea_in
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ea_in
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);
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);
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input wb_rst_i, // reset input
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input wb_rst_i, // reset input
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wb_clk_i, // clock input
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wb_clk_i, // clock input
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int0_i, // interrupt 0
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int0_i, // interrupt 0
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int1_i, // interrupt 1
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int1_i, // interrupt 1
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ea_in, // external access
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ea_in, // external access
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wbd_ack_i, // data acknowalge
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wbd_ack_i, // data acknowalge
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wbi_ack_i, // instruction acknowlage
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wbi_ack_i, // instruction acknowlage
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wbd_err_i, // data error
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wbd_err_i, // data error
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wbi_err_i; // instruction error
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wbi_err_i; // instruction error
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input [7:0] wbd_dat_i; // ram data input
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input [7:0] wbd_dat_i; // ram data input
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input [31:0] wbi_dat_i; // rom data input
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input [31:0] wbi_dat_i; // rom data input
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output wbd_we_o, // data write enable
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output wbd_we_o, // data write enable
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wbd_stb_o, // data strobe
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wbd_stb_o, // data strobe
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wbd_cyc_o, // data cycle
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wbd_cyc_o, // data cycle
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wbi_stb_o, // instruction strobe
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wbi_stb_o, // instruction strobe
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wbi_cyc_o; // instruction cycle
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wbi_cyc_o; // instruction cycle
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output [7:0] wbd_dat_o; // data output
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output [7:0] wbd_dat_o; // data output
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output [15:0] wbd_adr_o, // data address
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output [15:0] wbd_adr_o, // data address
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wbi_adr_o; // instruction address
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wbi_adr_o; // instruction address
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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input [7:0] p0_i; // port 0 input
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input [7:0] p0_i; // port 0 input
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output [7:0] p0_o; // port 0 output
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output [7:0] p0_o; // port 0 output
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`endif
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`endif
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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input [7:0] p1_i; // port 1 input
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input [7:0] p1_i; // port 1 input
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output [7:0] p1_o; // port 1 output
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output [7:0] p1_o; // port 1 output
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`endif
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`endif
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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input [7:0] p2_i; // port 2 input
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input [7:0] p2_i; // port 2 input
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output [7:0] p2_o; // port 2 output
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output [7:0] p2_o; // port 2 output
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`endif
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`endif
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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input [7:0] p3_i; // port 3 input
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input [7:0] p3_i; // port 3 input
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output [7:0] p3_o; // port 3 output
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output [7:0] p3_o; // port 3 output
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`endif
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`endif
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`endif
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`endif
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`ifdef OC8051_UART
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`ifdef OC8051_UART
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input rxd_i; // receive
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input rxd_i; // receive
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output txd_o; // transnmit
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output txd_o; // transnmit
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`endif
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`endif
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`ifdef OC8051_TC01
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`ifdef OC8051_TC01
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input t0_i, // counter 0 input
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input t0_i, // counter 0 input
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t1_i; // counter 1 input
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t1_i; // counter 1 input
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`endif
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`endif
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`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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input t2_i, // counter 2 input
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input t2_i, // counter 2 input
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t2ex_i; //
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t2ex_i; //
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`endif
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`endif
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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input scanb_rst;
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input scanb_rst;
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input scanb_clk;
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input scanb_clk;
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input scanb_si;
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input scanb_si;
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output scanb_so;
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output scanb_so;
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input scanb_en;
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input scanb_en;
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wire scanb_soi;
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wire scanb_soi;
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`endif
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`endif
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wire [7:0] dptr_hi,
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wire [7:0] dptr_hi,
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dptr_lo,
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dptr_lo,
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ri,
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ri,
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data_out,
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data_out,
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op1,
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op1,
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op2,
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op2,
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op3,
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op3,
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acc,
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acc,
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p0_out,
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p0_out,
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p1_out,
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p1_out,
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p2_out,
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p2_out,
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p3_out,
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p3_out,
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sp,
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sp,
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sp_w;
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sp_w;
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wire [31:0] idat_onchip;
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wire [31:0] idat_onchip;
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wire [15:0] pc;
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wire [15:0] pc;
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assign wbd_cyc_o = wbd_stb_o;
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assign wbd_cyc_o = wbd_stb_o;
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wire src_sel3;
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wire src_sel3;
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wire [1:0] wr_sfr,
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wire [1:0] wr_sfr,
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src_sel2;
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src_sel2;
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wire [2:0] ram_rd_sel, // ram read
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wire [2:0] ram_rd_sel, // ram read
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ram_wr_sel, // ram write
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ram_wr_sel, // ram write
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src_sel1;
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src_sel1;
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wire [7:0] ram_data,
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wire [7:0] ram_data,
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ram_out, //data from ram
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ram_out, //data from ram
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sfr_out,
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sfr_out,
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wr_dat,
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wr_dat,
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wr_addr, //ram write addres
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wr_addr, //ram write addres
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rd_addr; //data ram read addres
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rd_addr; //data ram read addres
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wire sfr_bit;
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wire sfr_bit;
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wire [1:0] cy_sel, //carry select; from decoder to cy_selct1
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wire [1:0] cy_sel, //carry select; from decoder to cy_selct1
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bank_sel;
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bank_sel;
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wire rom_addr_sel, //rom addres select; alu or pc
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wire rom_addr_sel, //rom addres select; alu or pc
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rmw,
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rmw,
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ea_int;
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ea_int;
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wire reti,
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wire reti,
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intr,
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intr,
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int_ack,
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int_ack,
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istb;
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istb;
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wire [7:0] int_src;
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wire [7:0] int_src;
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wire mem_wait;
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wire mem_wait;
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wire [2:0] mem_act;
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wire [2:0] mem_act;
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wire [3:0] alu_op; //alu operation (from decoder)
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wire [3:0] alu_op; //alu operation (from decoder)
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wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)
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wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)
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|
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wire [7:0] src1, //alu sources 1
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wire [7:0] src1, //alu sources 1
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src2, //alu sources 2
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src2, //alu sources 2
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src3, //alu sources 3
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src3, //alu sources 3
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des_acc,
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des_acc,
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des1, //alu destination 1
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des1, //alu destination 1
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des2; //alu destinations 2
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des2; //alu destinations 2
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wire desCy, //carry out
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wire desCy, //carry out
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desAc,
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desAc,
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desOv, //overflow
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desOv, //overflow
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alu_cy,
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alu_cy,
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wr, //write to data ram
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wr, //write to data ram
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wr_o;
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wr_o;
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wire rd, //read program rom
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wire rd, //read program rom
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pc_wr;
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pc_wr;
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wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)
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wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)
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wire [7:0] op1_n, //from memory_interface to decoder
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wire [7:0] op1_n, //from memory_interface to decoder
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op2_n,
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op2_n,
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op3_n;
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op3_n;
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wire [1:0] comp_sel; //select source1 and source2 to compare
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wire [1:0] comp_sel; //select source1 and source2 to compare
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wire eq, //result (from comp1 to decoder)
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wire eq, //result (from comp1 to decoder)
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srcAc,
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srcAc,
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cy,
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cy,
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rd_ind,
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rd_ind,
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wr_ind,
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wr_ind,
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comp_wait;
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comp_wait;
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wire [2:0] op1_cur;
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wire [2:0] op1_cur;
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|
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wire bit_addr, //bit addresable instruction
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wire bit_addr, //bit addresable instruction
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bit_data, //bit data from ram to ram_select
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bit_data, //bit data from ram to ram_select
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bit_out, //bit data from ram_select to alu and cy_select
|
bit_out, //bit data from ram_select to alu and cy_select
|
bit_addr_o,
|
bit_addr_o,
|
wait_data;
|
wait_data;
|
|
|
//
|
//
|
// cpu to cache/wb_interface
|
// cpu to cache/wb_interface
|
wire iack_i,
|
wire iack_i,
|
istb_o,
|
istb_o,
|
icyc_o;
|
icyc_o;
|
wire [31:0] idat_i;
|
wire [31:0] idat_i;
|
wire [15:0] iadr_o;
|
wire [15:0] iadr_o;
|
|
|
|
|
//
|
//
|
// decoder
|
// decoder
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
|
.rst(wb_rst_i),
|
.rst(wb_rst_i),
|
.op_in(op1_n),
|
.op_in(op1_n),
|
.op1_c(op1_cur),
|
.op1_c(op1_cur),
|
.ram_rd_sel_o(ram_rd_sel),
|
.ram_rd_sel_o(ram_rd_sel),
|
.ram_wr_sel_o(ram_wr_sel),
|
.ram_wr_sel_o(ram_wr_sel),
|
.bit_addr(bit_addr),
|
.bit_addr(bit_addr),
|
|
|
.src_sel1(src_sel1),
|
.src_sel1(src_sel1),
|
.src_sel2(src_sel2),
|
.src_sel2(src_sel2),
|
.src_sel3(src_sel3),
|
.src_sel3(src_sel3),
|
|
|
.alu_op_o(alu_op),
|
.alu_op_o(alu_op),
|
.psw_set(psw_set),
|
.psw_set(psw_set),
|
.cy_sel(cy_sel),
|
.cy_sel(cy_sel),
|
.wr_o(wr),
|
.wr_o(wr),
|
.pc_wr(pc_wr),
|
.pc_wr(pc_wr),
|
.pc_sel(pc_wr_sel),
|
.pc_sel(pc_wr_sel),
|
.comp_sel(comp_sel),
|
.comp_sel(comp_sel),
|
.eq(eq),
|
.eq(eq),
|
.wr_sfr_o(wr_sfr),
|
.wr_sfr_o(wr_sfr),
|
.rd(rd),
|
.rd(rd),
|
.rmw(rmw),
|
.rmw(rmw),
|
.istb(istb),
|
.istb(istb),
|
.mem_act(mem_act),
|
.mem_act(mem_act),
|
.mem_wait(mem_wait),
|
.mem_wait(mem_wait),
|
.wait_data(wait_data));
|
.wait_data(wait_data));
|
|
|
|
|
wire [7:0] sub_result;
|
wire [7:0] sub_result;
|
//
|
//
|
//alu
|
//alu
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
|
.clk(wb_clk_i),
|
.clk(wb_clk_i),
|
.op_code(alu_op),
|
.op_code(alu_op),
|
.src1(src1),
|
.src1(src1),
|
.src2(src2),
|
.src2(src2),
|
.src3(src3),
|
.src3(src3),
|
.srcCy(alu_cy),
|
.srcCy(alu_cy),
|
.srcAc(srcAc),
|
.srcAc(srcAc),
|
.des_acc(des_acc),
|
.des_acc(des_acc),
|
.sub_result(sub_result),
|
.sub_result(sub_result),
|
.des1(des1),
|
.des1(des1),
|
.des2(des2),
|
.des2(des2),
|
.desCy(desCy),
|
.desCy(desCy),
|
.desAc(desAc),
|
.desAc(desAc),
|
.desOv(desOv),
|
.desOv(desOv),
|
.bit_in(bit_out));
|
.bit_in(bit_out));
|
|
|
//
|
//
|
//data ram
|
//data ram
|
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
|
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
|
.rst(wb_rst_i),
|
.rst(wb_rst_i),
|
.rd_addr(rd_addr),
|
.rd_addr(rd_addr),
|
.rd_data(ram_data),
|
.rd_data(ram_data),
|
.wr_addr(wr_addr),
|
.wr_addr(wr_addr),
|
.bit_addr(bit_addr_o),
|
.bit_addr(bit_addr_o),
|
.wr_data(wr_dat),
|
.wr_data(wr_dat),
|
.wr(wr_o && (!wr_addr[7] || wr_ind)),
|
.wr(wr_o && (!wr_addr[7] || wr_ind)),
|
.bit_data_in(desCy),
|
.bit_data_in(desCy),
|
.bit_data_out(bit_data)
|
.bit_data_out(bit_data)
|
`ifdef OC8051_BIST
|
`ifdef OC8051_BIST
|
,
|
,
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
.scanb_si(scanb_soi),
|
.scanb_si(scanb_soi),
|
.scanb_so(scanb_so),
|
.scanb_so(scanb_so),
|
.scanb_en(scanb_en)
|
.scanb_en(scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
//
|
//
|
|
|
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
|
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
|
.rst(wb_rst_i),
|
.rst(wb_rst_i),
|
.rd(rd),
|
.rd(rd),
|
|
|
.sel1(src_sel1),
|
.sel1(src_sel1),
|
.sel2(src_sel2),
|
.sel2(src_sel2),
|
.sel3(src_sel3),
|
.sel3(src_sel3),
|
|
|
.acc(acc),
|
.acc(acc),
|
.ram(ram_out),
|
.ram(ram_out),
|
.pc(pc),
|
.pc(pc),
|
.dptr({dptr_hi, dptr_lo}),
|
.dptr({dptr_hi, dptr_lo}),
|
.op1(op1_n),
|
.op1(op1_n),
|
.op2(op2_n),
|
.op2(op2_n),
|
.op3(op3_n),
|
.op3(op3_n),
|
|
|
.src1(src1),
|
.src1(src1),
|
.src2(src2),
|
.src2(src2),
|
.src3(src3));
|
.src3(src3));
|
|
|
|
|
//
|
//
|
//
|
//
|
oc8051_comp oc8051_comp1(.sel(comp_sel),
|
oc8051_comp oc8051_comp1(.sel(comp_sel),
|
.eq(eq),
|
.eq(eq),
|
.b_in(bit_out),
|
.b_in(bit_out),
|
.cy(cy),
|
.cy(cy),
|
.acc(acc),
|
.acc(acc),
|
.des(sub_result)
|
.des(sub_result)
|
);
|
);
|
|
|
|
|
//
|
//
|
//program rom
|
//program rom
|
`ifdef OC8051_ROM
|
`ifdef OC8051_ROM
|
oc8051_rom oc8051_rom1(.rst(wb_rst_i),
|
oc8051_rom oc8051_rom1(.rst(wb_rst_i),
|
.clk(wb_clk_i),
|
.clk(wb_clk_i),
|
.ea_int(ea_int),
|
.ea_int(ea_int),
|
.addr(iadr_o),
|
.addr(iadr_o),
|
.data_o(idat_onchip)
|
.data_o(idat_onchip)
|
);
|
);
|
`else
|
`else
|
assign ea_int = 1'b0;
|
assign ea_int = 1'b0;
|
assign idat_onchip = 32'h0;
|
assign idat_onchip = 32'h0;
|
|
|
|
`ifdef OC8051_SIMULATION
|
|
|
|
initial
|
|
begin
|
|
$display("\t * ");
|
|
$display("\t * Internal rom disabled!!!");
|
|
$display("\t * ");
|
|
end
|
|
|
|
`endif
|
|
|
`endif
|
`endif
|
|
|
//
|
//
|
//
|
//
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
|
.cy_in(cy),
|
.cy_in(cy),
|
.data_in(bit_out),
|
.data_in(bit_out),
|
.data_out(alu_cy));
|
.data_out(alu_cy));
|
//
|
//
|
//
|
//
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
|
.rst(wb_rst_i),
|
.rst(wb_rst_i),
|
.wr_addr(wr_addr),
|
.wr_addr(wr_addr),
|
.data_in(wr_dat),
|
.data_in(wr_dat),
|
.wr(wr_o),
|
.wr(wr_o),
|
.wr_bit(bit_addr_o),
|
.wr_bit(bit_addr_o),
|
.ri_out(ri),
|
.ri_out(ri),
|
.sel(op1_cur[0]),
|
.sel(op1_cur[0]),
|
.bank(bank_sel));
|
.bank(bank_sel));
|
|
|
|
|
|
|
assign icyc_o = istb_o;
|
assign icyc_o = istb_o;
|
//
|
//
|
//
|
//
|
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
|
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
|
.rst(wb_rst_i),
|
.rst(wb_rst_i),
|
// internal ram
|
// internal ram
|
.wr_i(wr),
|
.wr_i(wr),
|
.wr_o(wr_o),
|
.wr_o(wr_o),
|
.wr_bit_i(bit_addr),
|
.wr_bit_i(bit_addr),
|
.wr_bit_o(bit_addr_o),
|
.wr_bit_o(bit_addr_o),
|
.wr_dat(wr_dat),
|
.wr_dat(wr_dat),
|
.des_acc(des_acc),
|
.des_acc(des_acc),
|
.des1(des1),
|
.des1(des1),
|
.des2(des2),
|
.des2(des2),
|
.rd_addr(rd_addr),
|
.rd_addr(rd_addr),
|
.wr_addr(wr_addr),
|
.wr_addr(wr_addr),
|
.wr_ind(wr_ind),
|
.wr_ind(wr_ind),
|
.bit_in(bit_data),
|
.bit_in(bit_data),
|
.in_ram(ram_data),
|
.in_ram(ram_data),
|
.sfr(sfr_out),
|
.sfr(sfr_out),
|
.sfr_bit(sfr_bit),
|
.sfr_bit(sfr_bit),
|
.bit_out(bit_out),
|
.bit_out(bit_out),
|
.iram_out(ram_out),
|
.iram_out(ram_out),
|
|
|
// external instrauction rom
|
// external instrauction rom
|
.iack_i(iack_i),
|
.iack_i(iack_i),
|
.iadr_o(iadr_o),
|
.iadr_o(iadr_o),
|
.idat_i(idat_i),
|
.idat_i(idat_i),
|
.istb_o(istb_o),
|
.istb_o(istb_o),
|
|
|
// internal instruction rom
|
// internal instruction rom
|
.idat_onchip(idat_onchip),
|
.idat_onchip(idat_onchip),
|
|
|
// data memory
|
// data memory
|
.dadr_o(wbd_adr_o),
|
.dadr_o(wbd_adr_o),
|
.ddat_o(wbd_dat_o),
|
.ddat_o(wbd_dat_o),
|
.dwe_o(wbd_we_o),
|
.dwe_o(wbd_we_o),
|
.dstb_o(wbd_stb_o),
|
.dstb_o(wbd_stb_o),
|
.ddat_i(wbd_dat_i),
|
.ddat_i(wbd_dat_i),
|
.dack_i(wbd_ack_i),
|
.dack_i(wbd_ack_i),
|
|
|
// from decoder
|
// from decoder
|
.rd_sel(ram_rd_sel),
|
.rd_sel(ram_rd_sel),
|
.wr_sel(ram_wr_sel),
|
.wr_sel(ram_wr_sel),
|
.rn({bank_sel, op1_cur}),
|
.rn({bank_sel, op1_cur}),
|
.rd_ind(rd_ind),
|
.rd_ind(rd_ind),
|
.rd(rd),
|
.rd(rd),
|
.mem_act(mem_act),
|
.mem_act(mem_act),
|
.mem_wait(mem_wait),
|
.mem_wait(mem_wait),
|
|
|
// external access
|
// external access
|
.ea(ea_in),
|
.ea(ea_in),
|
.ea_int(ea_int),
|
.ea_int(ea_int),
|
|
|
// instructions outputs to cpu
|
// instructions outputs to cpu
|
.op1_out(op1_n),
|
.op1_out(op1_n),
|
.op2_out(op2_n),
|
.op2_out(op2_n),
|
.op3_out(op3_n),
|
.op3_out(op3_n),
|
|
|
// interrupt interface
|
// interrupt interface
|
.intr(intr),
|
.intr(intr),
|
.int_v(int_src),
|
.int_v(int_src),
|
.int_ack(int_ack),
|
.int_ack(int_ack),
|
.istb(istb),
|
.istb(istb),
|
.reti(reti),
|
.reti(reti),
|
|
|
//pc
|
//pc
|
.pc_wr_sel(pc_wr_sel),
|
.pc_wr_sel(pc_wr_sel),
|
.pc_wr(pc_wr & comp_wait),
|
.pc_wr(pc_wr & comp_wait),
|
.pc(pc),
|
.pc(pc),
|
|
|
// sfr's
|
// sfr's
|
.sp_w(sp_w),
|
.sp_w(sp_w),
|
.dptr({dptr_hi, dptr_lo}),
|
.dptr({dptr_hi, dptr_lo}),
|
.ri(ri),
|
.ri(ri),
|
.acc(acc),
|
.acc(acc),
|
.sp(sp)
|
.sp(sp)
|
);
|
);
|
|
|
|
|
//
|
//
|
//
|
//
|
|
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
|
.clk(wb_clk_i),
|
.clk(wb_clk_i),
|
.adr0(rd_addr[7:0]),
|
.adr0(rd_addr[7:0]),
|
.adr1(wr_addr[7:0]),
|
.adr1(wr_addr[7:0]),
|
.dat0(sfr_out),
|
.dat0(sfr_out),
|
.dat1(wr_dat),
|
.dat1(wr_dat),
|
.dat2(des2),
|
.dat2(des2),
|
.des_acc(des_acc),
|
.des_acc(des_acc),
|
.we(wr_o && !wr_ind),
|
.we(wr_o && !wr_ind),
|
.bit_in(desCy),
|
.bit_in(desCy),
|
.bit_out(sfr_bit),
|
.bit_out(sfr_bit),
|
.wr_bit(bit_addr_o),
|
.wr_bit(bit_addr_o),
|
.ram_rd_sel(ram_rd_sel),
|
.ram_rd_sel(ram_rd_sel),
|
.ram_wr_sel(ram_wr_sel),
|
.ram_wr_sel(ram_wr_sel),
|
.wr_sfr(wr_sfr),
|
.wr_sfr(wr_sfr),
|
.comp_sel(comp_sel),
|
.comp_sel(comp_sel),
|
.comp_wait(comp_wait),
|
.comp_wait(comp_wait),
|
// acc
|
// acc
|
.acc(acc),
|
.acc(acc),
|
// sp
|
// sp
|
.sp(sp),
|
.sp(sp),
|
.sp_w(sp_w),
|
.sp_w(sp_w),
|
// psw
|
// psw
|
.bank_sel(bank_sel),
|
.bank_sel(bank_sel),
|
.desAc(desAc),
|
.desAc(desAc),
|
.desOv(desOv),
|
.desOv(desOv),
|
.psw_set(psw_set),
|
.psw_set(psw_set),
|
.srcAc(srcAc),
|
.srcAc(srcAc),
|
.cy(cy),
|
.cy(cy),
|
// ports
|
// ports
|
.rmw(rmw),
|
.rmw(rmw),
|
|
|
`ifdef OC8051_PORTS
|
`ifdef OC8051_PORTS
|
`ifdef OC8051_PORT0
|
`ifdef OC8051_PORT0
|
.p0_out(p0_o),
|
.p0_out(p0_o),
|
.p0_in(p0_i),
|
.p0_in(p0_i),
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT1
|
`ifdef OC8051_PORT1
|
.p1_out(p1_o),
|
.p1_out(p1_o),
|
.p1_in(p1_i),
|
.p1_in(p1_i),
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT2
|
`ifdef OC8051_PORT2
|
.p2_out(p2_o),
|
.p2_out(p2_o),
|
.p2_in(p2_i),
|
.p2_in(p2_i),
|
`endif
|
`endif
|
|
|
`ifdef OC8051_PORT3
|
`ifdef OC8051_PORT3
|
.p3_out(p3_o),
|
.p3_out(p3_o),
|
.p3_in(p3_i),
|
.p3_in(p3_i),
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
// uart
|
// uart
|
`ifdef OC8051_UART
|
`ifdef OC8051_UART
|
.rxd(rxd_i), .txd(txd_o),
|
.rxd(rxd_i), .txd(txd_o),
|
`endif
|
`endif
|
|
|
// int
|
// int
|
.int_ack(int_ack),
|
.int_ack(int_ack),
|
.intr(intr),
|
.intr(intr),
|
.int0(int0_i),
|
.int0(int0_i),
|
.int1(int1_i),
|
.int1(int1_i),
|
.reti(reti),
|
.reti(reti),
|
.int_src(int_src),
|
.int_src(int_src),
|
|
|
// t/c 0,1
|
// t/c 0,1
|
`ifdef OC8051_TC01
|
`ifdef OC8051_TC01
|
.t0(t0_i),
|
.t0(t0_i),
|
.t1(t1_i),
|
.t1(t1_i),
|
`endif
|
`endif
|
|
|
// t/c 2
|
// t/c 2
|
`ifdef OC8051_TC2
|
`ifdef OC8051_TC2
|
.t2(t2_i),
|
.t2(t2_i),
|
.t2ex(t2ex_i),
|
.t2ex(t2ex_i),
|
`endif
|
`endif
|
|
|
// dptr
|
// dptr
|
.dptr_hi(dptr_hi),
|
.dptr_hi(dptr_hi),
|
.dptr_lo(dptr_lo),
|
.dptr_lo(dptr_lo),
|
.wait_data(wait_data)
|
.wait_data(wait_data)
|
);
|
);
|
|
|
|
|
|
|
|
|
`ifdef OC8051_CACHE
|
`ifdef OC8051_CACHE
|
|
|
|
|
oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
|
oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
|
// cpu
|
// cpu
|
.adr_i(iadr_o),
|
.adr_i(iadr_o),
|
.dat_o(idat_i),
|
.dat_o(idat_i),
|
.stb_i(istb_o),
|
.stb_i(istb_o),
|
.ack_o(iack_i),
|
.ack_o(iack_i),
|
.cyc_i(icyc_o),
|
.cyc_i(icyc_o),
|
// pins
|
// pins
|
.dat_i(wbi_dat_i),
|
.dat_i(wbi_dat_i),
|
.stb_o(wbi_stb_o),
|
.stb_o(wbi_stb_o),
|
.adr_o(wbi_adr_o),
|
.adr_o(wbi_adr_o),
|
.ack_i(wbi_ack_i),
|
.ack_i(wbi_ack_i),
|
.cyc_o(wbi_cyc_o)
|
.cyc_o(wbi_cyc_o)
|
`ifdef OC8051_BIST
|
`ifdef OC8051_BIST
|
,
|
,
|
.scanb_rst(scanb_rst),
|
.scanb_rst(scanb_rst),
|
.scanb_clk(scanb_clk),
|
.scanb_clk(scanb_clk),
|
.scanb_si(scanb_si),
|
.scanb_si(scanb_si),
|
.scanb_so(scanb_soi),
|
.scanb_so(scanb_soi),
|
.scanb_en(scanb_en)
|
.scanb_en(scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
|
defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
|
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
|
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
|
defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
|
defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
|
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
|
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
|
|
|
|
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
initial
|
|
$display(" Instruction cache enabled");
|
|
|
|
|
initial
|
|
begin
|
|
#1
|
|
$display("\t * ");
|
|
$display("\t * External rom interface: cache");
|
|
$display("\t * ");
|
|
end
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
//
|
//
|
// no cache
|
// no cache
|
//
|
//
|
`else
|
`else
|
|
|
`ifdef OC8051_BIST
|
`ifdef OC8051_BIST
|
assign scanb_soi=scanb_si;
|
assign scanb_soi=scanb_si;
|
`endif
|
`endif
|
|
|
`ifdef OC8051_WB
|
`ifdef OC8051_WB
|
|
|
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
|
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
|
// cpu
|
// cpu
|
.adr_i(iadr_o),
|
.adr_i(iadr_o),
|
.dat_o(idat_i),
|
.dat_o(idat_i),
|
.stb_i(istb_o),
|
.stb_i(istb_o),
|
.ack_o(iack_i),
|
.ack_o(iack_i),
|
.cyc_i(icyc_o),
|
.cyc_i(icyc_o),
|
// external rom
|
// external rom
|
.dat_i(wbi_dat_i),
|
.dat_i(wbi_dat_i),
|
.stb_o(wbi_stb_o),
|
.stb_o(wbi_stb_o),
|
.adr_o(wbi_adr_o),
|
.adr_o(wbi_adr_o),
|
.ack_i(wbi_ack_i),
|
.ack_i(wbi_ack_i),
|
.cyc_o(wbi_cyc_o));
|
.cyc_o(wbi_cyc_o));
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
initial
|
|
$display(" Wishbone instruction interface enabled");
|
|
|
|
|
initial
|
|
begin
|
|
#1
|
|
$display("\t * ");
|
|
$display("\t * External rom interface: WB interface");
|
|
$display("\t * ");
|
|
end
|
|
|
`endif
|
`endif
|
|
|
`else
|
`else
|
|
|
assign wbi_adr_o = iadr_o ;
|
assign wbi_adr_o = iadr_o ;
|
assign idat_i = wbi_dat_i ;
|
assign idat_i = wbi_dat_i ;
|
assign wbi_stb_o = 1'b1 ;
|
assign wbi_stb_o = 1'b1 ;
|
assign iack_i = wbi_ack_i ;
|
assign iack_i = wbi_ack_i ;
|
assign wbi_cyc_o = 1'b1 ;
|
assign wbi_cyc_o = 1'b1 ;
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
|
|
initial
|
initial
|
$display(" Pipelined instruction interface enabled");
|
begin
|
|
#1
|
|
$display("\t * ");
|
|
$display("\t * External rom interface: Pipelined interface");
|
|
$display("\t * ");
|
|
end
|
|
|
`endif
|
`endif
|
|
|
|
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
