//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 top level test bench ////
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//// 8051 top level test bench ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// top level test bench. ////
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//// top level test bench. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/10/24 13:36:53 simont
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// add instruction cache and DELAY parameters for external ram, rom
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//
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// Revision 1.5 2002/10/17 19:00:50 simont
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// Revision 1.5 2002/10/17 19:00:50 simont
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// add external rom
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// add external rom
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//
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//
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// Revision 1.4 2002/09/30 17:33:58 simont
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// Revision 1.4 2002/09/30 17:33:58 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_tb;
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module oc8051_tb;
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reg rst, clk;
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reg rst, clk;
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reg [15:0] pc_in;
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reg [15:0] pc_in;
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reg [7:0] p0_in, p1_in, p2_in;
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reg [7:0] p0_in, p1_in, p2_in;
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wire [31:0] idat_i;
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wire [31:0] idat_i;
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wire [15:0] ext_addr, iadr_o;
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wire [15:0] ext_addr, iadr_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i, ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i, ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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///
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///
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/// buffer for test vectors
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/// buffer for test vectors
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///
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///
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//
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//
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// buffer
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// buffer
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reg [23:0] buff [255:0];
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reg [23:0] buff [255:0];
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reg ea [1:0];
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reg ea [1:0];
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integer num;
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integer num;
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//
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//
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// oc8051 controller
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// oc8051 controller
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//
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//
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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.dat_i(data_in), .dat_o(data_out),
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.dat_i(data_in), .dat_o(data_out),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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//
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//
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// external data ram
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// external data ram
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//
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//
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
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defparam oc8051_xram1.DELAY = 2;
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defparam oc8051_xram1.DELAY = 2;
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//
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//
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// external uart
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// external uart
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//
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//
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
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//
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//
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// exteranl program rom
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// exteranl program rom
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//
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//
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// cache
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// cache
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//
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//
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//
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//
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`ifdef OC8051_CACHE
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wire istb_i, icyc_i, iack_o;
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wire istb_i, icyc_i, iack_o;
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wire [15:0] iadr_i;
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wire [15:0] iadr_i;
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wire [31:0] idat_o;
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wire [31:0] idat_o;
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`ifdef OC8051_CACHE
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
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// oc8051
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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.cyc_i(icyc_o),
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// external rom
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32)
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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//
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//
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// no cache
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// no cache
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//
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//
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`else
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`else
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(rst), .clk(clk),
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.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
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// oc8051
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.adr_i(iadr_o), .dat_o(idat_i), .stb_i(istb_o), .ack_o(iack_i),
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.cyc_i(icyc_o),
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// external rom
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.dat_i(idat_o), .stb_o(istb_i), .adr_o(iadr_i), .ack_i(iack_o),
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.cyc_o(icyc_i));
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oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_i), .data(idat_o),
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.stb_i(istb_i), .cyc_i(icyc_i), .ack_o(iack_o));
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`endif
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`endif
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//
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//
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//
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//
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//
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//
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defparam oc8051_xrom1.DELAY = 5;
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defparam oc8051_xrom1.DELAY = 5;
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//
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// test wb interface
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//
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reg [31:0] log_file;
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initial
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begin
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log_file = $fopen("log_file");
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$fdisplay(log_file, "file open");
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end
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// cache/cpu to instruction rom
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//
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WB_BUS_MON wb_bus_mon1(.CLK_I(clk), .RST_I(rst), .ACK_I(iack_o), .ADDR_O({16'h0000, iadr_i}), .CYC_O(icyc_i),
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.DAT_I(idat_o), .DAT_O(32'd0), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(istb_i),
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.WE_O(1'b0), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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// cpu to data ram
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//
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WB_BUS_MON wb_bus_mon3(.CLK_I(clk), .RST_I(rst), .ACK_I(ack_i), .ADDR_O({16'h0000, ext_addr}), .CYC_O(cyc_o),
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.DAT_I({24'h000000, data_in}), .DAT_O({24'h000000, data_out}), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(stb_o),
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.WE_O(write), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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//
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//
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//
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//
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign p3_in = {7'b000000, bit_out, int_uart};
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assign p3_in = {7'b000000, bit_out, int_uart};
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assign t0 = p3_out[5];
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assign t0 = p3_out[5];
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assign t1 = p3_out[6];
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assign t1 = p3_out[6];
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assign int0 = p3_out[3];
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assign int0 = p3_out[3];
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assign int1 = p3_out[4];
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assign int1 = p3_out[4];
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initial begin
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initial begin
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clk= 1'b0;
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clk= 1'b0;
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rst= 1'b1;
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rst= 1'b1;
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pc_in = 16'h0000;
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pc_in = 16'h0000;
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p0_in = 8'h00;
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p0_in = 8'h00;
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p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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#22
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#22
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rst = 1'b0;
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rst = 1'b0;
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//#444000
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//#444000
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#7000000
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#7000000
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$fclose(log_file);
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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end
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end
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always clk = #5 ~clk;
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always clk = #5 ~clk;
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initial
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initial
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$readmemh("../../../asm/vec/oc8051_test.vec", buff);
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$readmemh("../../../asm/vec/oc8051_test.vec", buff);
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initial
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initial
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$readmemb("../oc8051_ea.in", ea);
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$readmemb("../oc8051_ea.in", ea);
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initial num= 0;
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initial num= 0;
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always @(p0_out or p1_out or p2_out)
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always @(p0_out or p1_out or p2_out)
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begin
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begin
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if ({p0_out, p1_out, p2_out} != buff[num])
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if ({p0_out, p1_out, p2_out} != buff[num])
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begin
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begin
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display("time ",$time, " faulire: mismatch on ports in step %d", num);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out);
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$display(" testvecp %h", buff[num]);
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$display(" testvecp %h", buff[num]);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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$display(" p_out %h%h%h", p0_out, p1_out, p2_out);
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#22
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#22
|
|
$fclose(log_file);
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$finish;
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$finish;
|
end
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end
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else begin
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else begin
|
$display("time ",$time, " step %d", num, ": pass");
|
$display("time ",$time, " step %d", num, ": pass");
|
num = num+1;
|
num = num+1;
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if (buff[num]===24'hxxxxxx)
|
if (buff[num]===24'hxxxxxx)
|
begin
|
begin
|
$display("");
|
$display("");
|
$display(" Done!");
|
$display(" Done!");
|
|
$fclose(log_file);
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$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
end
|
end
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|
|
|
|
initial $dumpvars;
|
initial $dumpvars;
|
|
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//initial $monitor("time ",$time," acc %h", data_out, " dptr %h", ext_addr, " write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out);
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//initial $monitor("time ",$time," acc %h", data_out, " dptr %h", ext_addr, " write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out);
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//initial $monitor("time ",$time, " p0_out ", p0_out);
|
//initial $monitor("time ",$time, " p0_out ", p0_out);
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|
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//initial $monitor("time ",$time," write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out, " p3_out %h", p3_out);
|
//initial $monitor("time ",$time," write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out, " p3_out %h", p3_out);
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|
|
endmodule
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endmodule
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|
