//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// alu for 8051 Core ////
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//// alu for 8051 Core ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of aritmetic unit according to ////
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//// Implementation of aritmetic unit according to ////
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//// 8051 IP core specification document. Uses divide.v and ////
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//// 8051 IP core specification document. Uses divide.v and ////
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//// multiply.v ////
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//// multiply.v ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// pc signed add ////
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//// pc signed add ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
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module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in, des1, des2, des1_r, desCy, desAc, desOv);
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//
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//
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// op_code (in) operation code [oc8051_decoder.alu_op -r]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src1 (in) first operand [oc8051_alu_src1_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src2 (in) second operand [oc8051_alu_src2_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// src3 (in) third operand [oc8051_alu_src3_sel.des]
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// srcCy (in) carry input [oc8051_cy_select.data_out]
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// srcCy (in) carry input [oc8051_cy_select.data_out]
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// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
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// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
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// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
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// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
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// des1 (out)
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// des1 (out)
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// des1_r (out)
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// des1_r (out)
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// des2 (out)
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// des2 (out)
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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// desOv (out) Overflow output [oc8051_psw.ov_in]
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//
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//
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input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
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input srcCy, srcAc, bit_in, clk, rst; input [3:0] op_code; input [7:0] src1, src2, src3;
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output desCy, desAc, desOv;
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output desCy, desAc, desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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output [7:0] des1_r;
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output [7:0] des1_r;
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reg desCy, desAc, desOv;
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reg desCy, desAc, desOv;
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reg [7:0] des1, des2;
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reg [7:0] des1, des2;
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reg [7:0] des1_r;
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reg [7:0] des1_r;
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//
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//
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//add
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//add
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//
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//
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wire [4:0] add1, add2, add3, add4;
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wire [4:0] add1, add2, add3, add4;
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wire [3:0] add5, add6, add7, add8;
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wire [3:0] add5, add6, add7, add8;
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wire [1:0] add9, adda, addb, addc;
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wire [1:0] add9, adda, addb, addc;
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//
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//
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//sub
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//sub
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//
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//
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wire [4:0] sub1, sub2, sub3, sub4;
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wire [4:0] sub1, sub2, sub3, sub4;
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wire [3:0] sub5, sub6, sub7, sub8;
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wire [3:0] sub5, sub6, sub7, sub8;
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wire [1:0] sub9, suba, subb, subc;
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wire [1:0] sub9, suba, subb, subc;
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//
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//
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//mul
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//mul
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//
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//
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wire [7:0] mulsrc1, mulsrc2;
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wire [7:0] mulsrc1, mulsrc2;
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wire mulOv;
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wire mulOv;
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reg enable_mul;
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reg enable_mul;
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//
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//
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//div
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//div
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//
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//
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wire [7:0] divsrc1,divsrc2;
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wire [7:0] divsrc1,divsrc2;
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wire divOv;
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wire divOv;
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reg enable_div;
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reg enable_div;
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//
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//
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//da
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//da
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//
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//
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reg da_tmp;
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reg da_tmp;
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//reg [8:0] da1;
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//reg [8:0] da1;
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oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
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oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
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oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
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oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
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/* Add */
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/* Add */
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assign add1 = {1'b0,src1[3:0]};
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assign add1 = {1'b0,src1[3:0]};
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assign add2 = {1'b0,src2[3:0]};
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assign add2 = {1'b0,src2[3:0]};
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assign add3 = {3'b000,srcCy};
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assign add3 = {3'b000,srcCy};
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assign add4 = add1+add2+add3;
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assign add4 = add1+add2+add3;
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assign add5 = {1'b0,src1[6:4]};
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assign add5 = {1'b0,src1[6:4]};
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assign add6 = {1'b0,src2[6:4]};
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assign add6 = {1'b0,src2[6:4]};
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assign add7 = {1'b0,1'b0,1'b0,add4[4]};
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assign add7 = {1'b0,1'b0,1'b0,add4[4]};
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assign add8 = add5+add6+add7;
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assign add8 = add5+add6+add7;
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assign add9 = {1'b0,src1[7]};
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assign add9 = {1'b0,src1[7]};
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assign adda = {1'b0,src2[7]};
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assign adda = {1'b0,src2[7]};
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assign addb = {1'b0,add8[3]};
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assign addb = {1'b0,add8[3]};
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assign addc = add9+adda+addb;
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assign addc = add9+adda+addb;
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/* Sub */
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/* Sub */
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assign sub1 = {1'b1,src1[3:0]};
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assign sub1 = {1'b1,src1[3:0]};
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assign sub2 = {1'b0,src2[3:0]};
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assign sub2 = {1'b0,src2[3:0]};
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assign sub3 = {1'b0,1'b0,1'b0,srcCy};
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assign sub3 = {1'b0,1'b0,1'b0,srcCy};
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assign sub4 = sub1-sub2-sub3;
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assign sub4 = sub1-sub2-sub3;
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assign sub5 = {1'b1,src1[6:4]};
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assign sub5 = {1'b1,src1[6:4]};
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assign sub6 = {1'b0,src2[6:4]};
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assign sub6 = {1'b0,src2[6:4]};
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assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
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assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
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assign sub8 = sub5-sub6-sub7;
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assign sub8 = sub5-sub6-sub7;
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assign sub9 = {1'b1,src1[7]};
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assign sub9 = {1'b1,src1[7]};
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assign suba = {1'b0,src2[7]};
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assign suba = {1'b0,src2[7]};
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assign subb = {1'b0,!sub8[3]};
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assign subb = {1'b0,!sub8[3]};
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assign subc = sub9-suba-subb;
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assign subc = sub9-suba-subb;
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always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1 or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4 or sub4 or sub8 or subc or da_tmp)
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always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1 or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4 or sub4 or sub8 or subc or da_tmp)
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begin
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begin
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case (op_code)
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case (op_code)
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//operation add
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//operation add
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`OC8051_ALU_ADD: begin
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`OC8051_ALU_ADD: begin
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des1 = {addc[0],add8[2:0],add4[3:0]};
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des1 = {addc[0],add8[2:0],add4[3:0]};
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des2 = src3+ {7'b0, addc[1]};
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des2 = src3+ {7'b0, addc[1]};
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desCy = addc[1];
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desCy = addc[1];
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desAc = add4[4];
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desAc = add4[4];
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desOv = addc[1] ^ add8[3];
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desOv = addc[1] ^ add8[3];
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation subtract
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//operation subtract
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`OC8051_ALU_SUB: begin
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`OC8051_ALU_SUB: begin
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des1 = {subc[0],sub8[2:0],sub4[3:0]};
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des1 = {subc[0],sub8[2:0],sub4[3:0]};
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = !subc[1];
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desCy = !subc[1];
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desAc = !sub4[4];
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desAc = !sub4[4];
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desOv = !subc[1] ^ sub8[3];
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desOv = !subc[1] ^ sub8[3];
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation multiply
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//operation multiply
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`OC8051_ALU_MUL: begin
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`OC8051_ALU_MUL: begin
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des1 = mulsrc2;
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des1 = mulsrc1;
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des2 = mulsrc1;
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des2 = mulsrc2;
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desOv = mulOv;
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desOv = mulOv;
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desCy = 1'b0;
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desCy = 1'b0;
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desAc = 1'bx;
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desAc = 1'bx;
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enable_mul = 1'b1;
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enable_mul = 1'b1;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation divide
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//operation divide
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`OC8051_ALU_DIV: begin
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`OC8051_ALU_DIV: begin
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des1 = divsrc2;
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des1 = divsrc1;
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des2 = divsrc1;
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des2 = divsrc2;
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desOv = divOv;
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desOv = divOv;
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desAc = 1'bx;
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desAc = 1'bx;
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desCy = 1'b0;
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desCy = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b1;
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enable_div = 1'b1;
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end
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end
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//operation decimal adjustment
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//operation decimal adjustment
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`OC8051_ALU_DA: begin
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`OC8051_ALU_DA: begin
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/* da1= {1'b0, src1};
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/* da1= {1'b0, src1};
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if (srcAc==1'b1 | da1[3:0]>4'b1001) da1= da1+ 9'b0_0000_0110;
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if (srcAc==1'b1 | da1[3:0]>4'b1001) da1= da1+ 9'b0_0000_0110;
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da1[8]= da1[8] | srcCy;
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da1[8]= da1[8] | srcCy;
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if (da1[8]==1'b1) da1=da1+ 9'b0_0110_0000;
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if (da1[8]==1'b1) da1=da1+ 9'b0_0110_0000;
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des1=da1[7:0];
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des1=da1[7:0];
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des2=8'h00;
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des2=8'h00;
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desCy=da1[8];*/
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desCy=da1[8];*/
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if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des1[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
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if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des1[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
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else {da_tmp, des1[3:0]} = {1'b0, src1[3:0]};
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else {da_tmp, des1[3:0]} = {1'b0, src1[3:0]};
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if (srcCy==1'b1 | src1[7:4]>4'b1001)
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if (srcCy==1'b1 | src1[7:4]>4'b1001)
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{desCy, des1[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
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{desCy, des1[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
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else {desCy, des1[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
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else {desCy, des1[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
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des2 = 8'h00;
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des2 = 8'h00;
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desAc = 1'b0;
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desAc = 1'b0;
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desOv = 1'b0;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation not
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//operation not
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// bit operation not
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// bit operation not
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`OC8051_ALU_NOT: begin
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`OC8051_ALU_NOT: begin
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des1 = ~src1;
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des1 = ~src1;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = !srcCy;
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desCy = !srcCy;
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desAc = 1'bx;
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desAc = 1'bx;
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desOv = 1'bx;
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desOv = 1'bx;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
|
enable_div = 1'b0;
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end
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end
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//operation and
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//operation and
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//bit operation and
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//bit operation and
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`OC8051_ALU_AND: begin
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`OC8051_ALU_AND: begin
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des1 = src1 & src2;
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des1 = src1 & src2;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = srcCy & bit_in;
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desCy = srcCy & bit_in;
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desAc = 1'bx;
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desAc = 1'bx;
|
desOv = 1'bx;
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desOv = 1'bx;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation xor
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//operation xor
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// bit operation xor
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// bit operation xor
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`OC8051_ALU_XOR: begin
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`OC8051_ALU_XOR: begin
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des1 = src1 ^ src2;
|
des1 = src1 ^ src2;
|
des2 = 8'h00;
|
des2 = 8'h00;
|
desCy = srcCy ^ bit_in;
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desCy = srcCy ^ bit_in;
|
desAc = 1'bx;
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desAc = 1'bx;
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desOv = 1'bx;
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desOv = 1'bx;
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enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
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end
|
//operation or
|
//operation or
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// bit operation or
|
// bit operation or
|
`OC8051_ALU_OR: begin
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`OC8051_ALU_OR: begin
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des1 = src1 | src2;
|
des1 = src1 | src2;
|
des2 = 8'h00;
|
des2 = 8'h00;
|
desCy = srcCy | bit_in;
|
desCy = srcCy | bit_in;
|
desAc = 1'bx;
|
desAc = 1'bx;
|
desOv = 1'bx;
|
desOv = 1'bx;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation rotate left
|
//operation rotate left
|
// bit operation cy= cy or (not ram)
|
// bit operation cy= cy or (not ram)
|
`OC8051_ALU_RL: begin
|
`OC8051_ALU_RL: begin
|
des1 = {src1[6:0], src1[7]};
|
des1 = {src1[6:0], src1[7]};
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des2 = 8'h00;
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des2 = 8'h00;
|
desCy = srcCy | !bit_in;
|
desCy = srcCy | !bit_in;
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desAc = 1'bx;
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desAc = 1'bx;
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desOv = 1'bx;
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desOv = 1'bx;
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enable_mul = 1'b0;
|
enable_mul = 1'b0;
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enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation rotate left with carry and swap nibbles
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//operation rotate left with carry and swap nibbles
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`OC8051_ALU_RLC: begin
|
`OC8051_ALU_RLC: begin
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des1 = {src1[6:0], srcCy};
|
des1 = {src1[6:0], srcCy};
|
des2 = {src1[3:0], src1[7:4]};
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des2 = {src1[3:0], src1[7:4]};
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desCy = src1[7];
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desCy = src1[7];
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desAc = 1'b0;
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desAc = 1'b0;
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desOv = 1'b0;
|
desOv = 1'b0;
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enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation rotate right
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//operation rotate right
|
`OC8051_ALU_RR: begin
|
`OC8051_ALU_RR: begin
|
des1 = {src1[0], src1[7:1]};
|
des1 = {src1[0], src1[7:1]};
|
des2 = 8'h00;
|
des2 = 8'h00;
|
desCy = srcCy & !bit_in;
|
desCy = srcCy & !bit_in;
|
desAc = 1'b0;
|
desAc = 1'b0;
|
desOv = 1'b0;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation rotate right with carry
|
//operation rotate right with carry
|
`OC8051_ALU_RRC: begin
|
`OC8051_ALU_RRC: begin
|
des1 = {srcCy, src1[7:1]};
|
des1 = {srcCy, src1[7:1]};
|
des2 = 8'h00;
|
des2 = 8'h00;
|
desCy = src1[0];
|
desCy = src1[0];
|
desAc = 1'b0;
|
desAc = 1'b0;
|
desOv = 1'b0;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation pcs Add
|
//operation pcs Add
|
`OC8051_ALU_PCS: begin
|
`OC8051_ALU_PCS: begin
|
if (src1[7]) begin
|
if (src1[7]) begin
|
des1 = src2+src1;
|
des1 = src2+src1;
|
des2 = src3;
|
des2 = src3;
|
end else {des2, des1} = {src3,src2} + {8'h00, src1};
|
end else {des2, des1} = {src3,src2} + {8'h00, src1};
|
desCy = 1'b0;
|
desCy = 1'b0;
|
desAc = 1'b0;
|
desAc = 1'b0;
|
desOv = 1'b0;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
//operation exchange
|
//operation exchange
|
//if carry = 0 exchange low order digit
|
//if carry = 0 exchange low order digit
|
`OC8051_ALU_XCH: begin
|
`OC8051_ALU_XCH: begin
|
if (srcCy)
|
if (srcCy)
|
begin
|
begin
|
des1 = src2;
|
des1 = src2;
|
des2 = src1;
|
des2 = src1;
|
end else begin
|
end else begin
|
des1 = {src1[7:4],src2[3:0]};
|
des1 = {src1[7:4],src2[3:0]};
|
des2 = {src2[7:4],src1[3:0]};
|
des2 = {src2[7:4],src1[3:0]};
|
end
|
end
|
desCy = 1'b0;
|
desCy = 1'b0;
|
desAc = 1'b0;
|
desAc = 1'b0;
|
desOv = 1'b0;
|
desOv = 1'b0;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
default: begin
|
default: begin
|
des1 = src1;
|
des1 = src1;
|
des2 = src2;
|
des2 = src2;
|
desCy = srcCy;
|
desCy = srcCy;
|
desAc = srcAc;
|
desAc = srcAc;
|
desOv = 1'bx;
|
desOv = 1'bx;
|
enable_mul = 1'b0;
|
enable_mul = 1'b0;
|
enable_div = 1'b0;
|
enable_div = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
des1_r <= #1 8'h0;
|
des1_r <= #1 8'h0;
|
end else begin
|
end else begin
|
des1_r <= #1 des1;
|
des1_r <= #1 des1;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|