//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 port output ////
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//// 8051 port output ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 8051 special function registers: port 0:3 - output ////
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//// 8051 special function registers: port 0:3 - output ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// ver: 1
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
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module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
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p0_in, p1_in, p2_in, p3_in);
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p0_in, p1_in, p2_in, p3_in);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// bit_in (in) bit input [oc8051_alu.desCy]
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// bit_in (in) bit input [oc8051_alu.desCy]
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// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
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// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// wr_addr (in) write address [oc8051_ram_wr_sel.out]
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// wr_addr (in) write address [oc8051_ram_wr_sel.out]
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// rd_addr (in) read address [oc8051_ram_rd_sel.out]
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// rd_addr (in) read address [oc8051_ram_rd_sel.out]
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// rmw (in) read modify write feature [oc8051_decoder.rmw]
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// rmw (in) read modify write feature [oc8051_decoder.rmw]
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// data_out (out) data output [oc8051_ram_sel.ports_in]
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// data_out (out) data output [oc8051_ram_sel.ports_in]
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// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
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// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
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// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
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// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
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//
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//
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input clk, rst, wr, wr_bit, bit_in, rmw;
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input clk, rst, wr, wr_bit, bit_in, rmw;
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input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
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input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
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output bit_out;
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output bit_out;
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output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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reg bit_out;
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reg bit_out;
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reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
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//
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//
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// case of writing to port
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// case of writing to port
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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p0_out <= #1 `OC8051_RST_P0;
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p0_out <= #1 `OC8051_RST_P0;
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p1_out <= #1 `OC8051_RST_P1;
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p1_out <= #1 `OC8051_RST_P1;
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p2_out <= #1 `OC8051_RST_P2;
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p2_out <= #1 `OC8051_RST_P2;
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p3_out <= #1 `OC8051_RST_P3;
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p3_out <= #1 `OC8051_RST_P3;
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end else if (wr) begin
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end else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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case (wr_addr)
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case (wr_addr)
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//
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//
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// bytaddresable
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// bytaddresable
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`OC8051_SFR_P0: p0_out <= #1 data_in;
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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endcase
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endcase
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end else begin
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end else begin
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case (wr_addr[7:3])
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case (wr_addr[7:3])
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//
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//
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// bit addressable
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// bit addressable
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
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//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rmw) begin
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if (rst)
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data_out <= #1 8'h0;
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else if (rmw) begin
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if ((rd_addr==wr_addr) & wr & !wr_bit)
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data_out <= #1 data_in;
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else begin
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case (rd_addr[5:4])
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case (rd_addr[5:4])
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2'b00: data_out = p0_out;
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2'b00: data_out <= #1 p0_out;
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2'b01: data_out = p1_out;
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2'b01: data_out <= #1 p1_out;
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2'b10: data_out = p2_out;
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2'b10: data_out <= #1 p2_out;
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2'b11: data_out = p3_out;
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2'b11: data_out <= #1 p3_out;
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endcase
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endcase
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end
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end else
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end else
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case (rd_addr[5:4])
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case (rd_addr[5:4])
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2'b00: data_out = p0_in;
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2'b00: data_out <= #1 p0_in;
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2'b01: data_out = p1_in;
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2'b01: data_out <= #1 p1_in;
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2'b10: data_out = p2_in;
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2'b10: data_out <= #1 p2_in;
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2'b11: data_out = p3_in;
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2'b11: data_out <= #1 p3_in;
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endcase
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endcase
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end
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end
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always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
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//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rmw) begin
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if (rst)
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bit_out <= #1 1'b0;
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else if (rmw) begin
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if ((wr_addr==rd_addr) & wr & wr_bit)
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bit_out <= #1 bit_in;
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else begin
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case (rd_addr[7:3])
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case (rd_addr[7:3])
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`OC8051_SFR_B_P0: bit_out = p0_out[rd_addr[2:0]];
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`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out = p1_out[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out = p2_out[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
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default: bit_out = p3_out[rd_addr[2:0]];
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default: bit_out <= #1 p3_out[rd_addr[2:0]];
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endcase
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endcase
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end
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end else begin
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end else begin
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case (rd_addr[7:3])
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case (rd_addr[7:3])
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`OC8051_SFR_B_P0: bit_out = p0_in[rd_addr[2:0]];
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`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out = p1_in[rd_addr[2:0]];
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`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out = p2_in[rd_addr[2:0]];
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`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
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default: bit_out = p3_in[rd_addr[2:0]];
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default: bit_out <= #1 p3_in[rd_addr[2:0]];
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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