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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
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module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
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rxd, txd, intr, t1_ow);
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rxd, txd, intr, t1_ow);
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input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
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input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
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input [7:0] rd_addr, data_in, wr_addr;
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input [7:0] rd_addr, data_in, wr_addr;
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output txd, intr, bit_out;
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output txd, intr, bit_out;
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output [7:0] data_out;
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output [7:0] data_out;
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reg txd, bit_out;
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reg txd, bit_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
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reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
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reg receive, receive_buf, rxd_buf, r_int;
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reg receive, receive_buf, rxd_buf, r_int;
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//
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//
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// mode 2 counter
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// mode 2 counter
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reg [2:0] mode2_count;
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reg [2:0] mode2_count;
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reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
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reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
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reg [10:0] sbuf_rxd_tmp;
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reg [10:0] sbuf_rxd_tmp;
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//
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//
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//tr_count trancive counter
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//tr_count trancive counter
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//re_count receive counter
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//re_count receive counter
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reg [3:0] tr_count, re_count;
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reg [3:0] tr_count, re_count;
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//
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//
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// sam_cnt sample counter
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// sam_cnt sample counter
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reg [2:0] sam_cnt, sample;
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reg [2:0] sam_cnt, sample;
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assign intr = scon[1] | scon [0];
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assign intr = scon[1] | scon [0];
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//
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//
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//serial port control register
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//serial port control register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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scon <= #1 `OC8051_RST_SCON;
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scon <= #1 `OC8051_RST_SCON;
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
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scon <= #1 data_in;
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scon <= #1 data_in;
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
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scon[wr_addr[2:0]] <= #1 bit_in;
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scon[wr_addr[2:0]] <= #1 bit_in;
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else if ((trans_buf) & !(trans))
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else if ((trans_buf) & !(trans))
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scon[1] <= #1 1'b1;
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scon[1] <= #1 1'b1;
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else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
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else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: scon[0] <= #1 1'b1;
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2'b00: scon[0] <= #1 1'b1;
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default: begin
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default: begin
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if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
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if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
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scon[2] <= #1 sbuf_rxd_tmp[9];
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scon[2] <= #1 sbuf_rxd_tmp[9];
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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//
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//
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//serial port buffer (transmit)
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//serial port buffer (transmit)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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sbuf_txd <= #1 `OC8051_RST_SBUF;
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sbuf_txd <= #1 `OC8051_RST_SBUF;
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tr_start <= #1 1'b0;
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tr_start <= #1 1'b0;
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end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
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end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
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sbuf_txd <= #1 data_in;
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sbuf_txd <= #1 data_in;
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tr_start <= #1 1'b1;
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tr_start <= #1 1'b1;
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end else tr_start <= #1 1'b0;
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end else tr_start <= #1 1'b0;
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end
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end
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//
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//
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// transmit
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// transmit
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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tr_count <= #1 4'd0;
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tr_count <= #1 4'd0;
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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//
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//
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// start transmiting
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// start transmiting
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//
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//
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end else if (tr_start) begin
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end else if (tr_start) begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: begin // mode 0
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2'b00: begin // mode 0
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txd <= #1 sbuf_txd[0];
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txd <= #1 sbuf_txd[0];
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tr_count <= #1 4'd1;
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tr_count <= #1 4'd1;
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end
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end
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2'b10: begin
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2'b10: begin
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txd <= #1 1'b0;
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txd <= #1 1'b0;
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tr_count <= #1 4'd0;
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tr_count <= #1 4'd0;
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end
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end
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default: begin // mode 1 and mode 3
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default: begin // mode 1 and mode 3
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tr_count <= #1 4'b1111;
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tr_count <= #1 4'b1111;
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end
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end
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endcase
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endcase
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trans <= #1 1'b1;
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trans <= #1 1'b1;
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smod_cnt_t <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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mode2_count <= #1 3'b000;
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mode2_count <= #1 3'b000;
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//
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//
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// transmiting
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// transmiting
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//
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//
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end else if (trans)
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end else if (trans)
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begin
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begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: begin //mode 0
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2'b00: begin //mode 0
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if (tr_count==4'd8)
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if (tr_count==4'd8)
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begin
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begin
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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end else begin
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end else begin
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txd <= #1 sbuf_txd[tr_count];
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txd <= #1 sbuf_txd[tr_count];
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tr_count <= #1 tr_count + 4'b1;
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tr_count <= #1 tr_count + 4'b1;
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end
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end
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end
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end
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2'b01: begin // mode 1
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2'b01: begin // mode 1
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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if ((pcon[7]) | (smod_cnt_t))
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if ((pcon[7]) | (smod_cnt_t))
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begin
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begin
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case (tr_count)
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case (tr_count)
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4'd8: txd <= #1 1'b1; // stop bit
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4'd8: txd <= #1 1'b1; // stop bit
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4'd9: trans <= #1 1'b0;
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4'd9: trans <= #1 1'b0;
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4'b1111: txd <= #1 1'b0; //start bit
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4'b1111: txd <= #1 1'b0; //start bit
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default: txd <= #1 sbuf_txd[tr_count];
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default: txd <= #1 sbuf_txd[tr_count];
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endcase
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endcase
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tr_count <= #1 tr_count + 4'b1;
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tr_count <= #1 tr_count + 4'b1;
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smod_cnt_t <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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end else smod_cnt_t <= #1 1'b1;
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end else smod_cnt_t <= #1 1'b1;
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end
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end
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end
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end
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2'b10: begin // mode 2
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2'b10: begin // mode 2
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//
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//
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// if smod (pcon[7]) is 1 count to 4 else count to 6
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// if smod (pcon[7]) is 1 count to 4 else count to 6
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//
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//
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if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
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if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
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case (tr_count)
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case (tr_count)
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4'd8: begin
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4'd8: begin
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txd <= #1 scon[3];
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txd <= #1 scon[3];
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end
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end
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4'd9: begin
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4'd9: begin
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txd <= #1 1'b1; //stop bit
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txd <= #1 1'b1; //stop bit
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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end
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end
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default: begin
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default: begin
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txd <= #1 sbuf_txd[tr_count];
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txd <= #1 sbuf_txd[tr_count];
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end
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end
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endcase
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endcase
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tr_count <= #1 tr_count+1'b1;
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tr_count <= #1 tr_count+1'b1;
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mode2_count <= #1 3'd0;
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mode2_count <= #1 3'd0;
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end else begin
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end else begin
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mode2_count <= #1 mode2_count + 3'b1;
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mode2_count <= #1 mode2_count + 3'b1;
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end
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end
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end
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end
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default: begin // mode 3
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default: begin // mode 3
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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if ((pcon[7]) | (smod_cnt_t))
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if ((pcon[7]) | (smod_cnt_t))
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begin
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begin
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case (tr_count)
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case (tr_count)
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4'd8: begin
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4'd8: begin
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txd <= #1 scon[3];
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txd <= #1 scon[3];
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end
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end
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4'd9: begin
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4'd9: begin
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txd <= #1 1'b1; //stop bit
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txd <= #1 1'b1; //stop bit
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end
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end
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4'd10: begin
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4'd10: begin
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trans <= #1 1'b0;
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trans <= #1 1'b0;
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end
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end
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4'b1111: txd <= #1 1'b0; //start bit
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4'b1111: txd <= #1 1'b0; //start bit
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default: begin
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default: begin
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txd <= #1 sbuf_txd[tr_count];
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txd <= #1 sbuf_txd[tr_count];
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end
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end
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endcase
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endcase
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tr_count <= #1 tr_count+1'b1;
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tr_count <= #1 tr_count+1'b1;
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smod_cnt_t <= #1 1'b0;
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smod_cnt_t <= #1 1'b0;
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end else smod_cnt_t <= #1 1'b1;
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end else smod_cnt_t <= #1 1'b1;
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end
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end
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end
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end
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endcase
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endcase
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end else
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end else
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txd <= #1 1'b1;
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txd <= #1 1'b1;
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end
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end
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//
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//
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//power control register
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//power control register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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pcon <= #1 `OC8051_RST_PCON;
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pcon <= #1 `OC8051_RST_PCON;
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
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pcon <= #1 data_in;
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pcon <= #1 data_in;
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end
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end
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//
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//
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//serial port buffer (receive)
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//serial port buffer (receive)
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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sample <= #1 3'b000;
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sample <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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re_count <= #1 4'd0;
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re_count <= #1 4'd0;
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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sbuf_rxd <= #1 8'h00;
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sbuf_rxd <= #1 8'h00;
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sbuf_rxd_tmp <= #1 11'd0;
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sbuf_rxd_tmp <= #1 11'd0;
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smod_cnt_r <= #1 1'b0;
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smod_cnt_r <= #1 1'b0;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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re_start <= #1 1'b0;
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re_start <= #1 1'b0;
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end else if (receive) begin
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end else if (receive) begin
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case (scon[7:6])
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case (scon[7:6])
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2'b00: begin // mode 0
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2'b00: begin // mode 0
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if (re_count==4'd8) begin
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if (re_count==4'd8) begin
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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r_int <= #1 1'b1;
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r_int <= #1 1'b1;
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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end else begin
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end else begin
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sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
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sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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re_count <= #1 re_count + 4'd1;
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re_count <= #1 re_count + 4'd1;
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end
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end
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2'b01: begin // mode 1
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2'b01: begin // mode 1
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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if ((pcon[7]) | (smod_cnt_r))
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if ((pcon[7]) | (smod_cnt_r))
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begin
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begin
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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re_count <= #1 re_count + 4'd1;
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re_count <= #1 re_count + 4'd1;
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smod_cnt_r <= #1 1'b0;
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smod_cnt_r <= #1 1'b0;
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end else smod_cnt_r <= #1 1'b1;
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end else smod_cnt_r <= #1 1'b1;
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end else begin
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end else begin
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if (sam_cnt==3'b011) begin
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if (sam_cnt==3'b011) begin
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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sbuf_rxd_tmp[re_count] <= #1 sample[0];
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sbuf_rxd_tmp[re_count] <= #1 sample[0];
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else
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else
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sbuf_rxd_tmp[re_count] <= #1 sample[1];
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sbuf_rxd_tmp[re_count] <= #1 sample[1];
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if (re_count == 4'd9)
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if (re_count == 4'd9)
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begin
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begin
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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r_int <= #1 1'b1;
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r_int <= #1 1'b1;
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end else r_int <= #1 1'b0;
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end else r_int <= #1 1'b0;
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end else begin
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end else begin
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sample[sam_cnt[1:0]] <= #1 rxd;
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sample[sam_cnt[1:0]] <= #1 rxd;
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sam_cnt <= #1 sam_cnt +1'b1;
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sam_cnt <= #1 sam_cnt +1'b1;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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end
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end
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end
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end
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2'b10: begin // mode 2
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2'b10: begin // mode 2
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if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
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if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
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if (re_count==4'd11) begin
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if (re_count==4'd11) begin
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
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r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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end else begin
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end else begin
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sam_cnt <= #1 3'b001;
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sam_cnt <= #1 3'b001;
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sample[0] <= #1 rxd;
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sample[0] <= #1 rxd;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
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re_count <= #1 re_count + 4'd1;
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re_count <= #1 re_count + 4'd1;
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end else begin
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end else begin
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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|
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if (sam_cnt==3'b011) begin
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if (sam_cnt==3'b011) begin
|
if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
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sbuf_rxd_tmp[re_count] <= #1 sample[0];
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sbuf_rxd_tmp[re_count] <= #1 sample[0];
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else
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else
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sbuf_rxd_tmp[re_count] <= #1 sample[1];
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sbuf_rxd_tmp[re_count] <= #1 sample[1];
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end else begin
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end else begin
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sample[sam_cnt[1:0]] <= #1 rxd;
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sample[sam_cnt[1:0]] <= #1 rxd;
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end
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end
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sam_cnt <= #1 sam_cnt + 1'b1;
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sam_cnt <= #1 sam_cnt + 1'b1;
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end
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end
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end
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end
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default: begin // mode 3
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default: begin // mode 3
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if ((t1_ow) & !(t1_ow_buf))
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if ((t1_ow) & !(t1_ow_buf))
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begin
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begin
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if ((pcon[7]) | (smod_cnt_r))
|
if ((pcon[7]) | (smod_cnt_r))
|
begin
|
begin
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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|
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if (re_count==4'd11) begin
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if (re_count==4'd11) begin
|
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
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receive <= #1 1'b0;
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receive <= #1 1'b0;
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r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
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r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
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end else begin
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end else begin
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sam_cnt <= #1 3'b000;
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sam_cnt <= #1 3'b000;
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r_int <= #1 1'b0;
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r_int <= #1 1'b0;
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end
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end
|
|
|
re_count <= #1 re_count + 4'd1;
|
re_count <= #1 re_count + 4'd1;
|
smod_cnt_r <= #1 1'b0;
|
smod_cnt_r <= #1 1'b0;
|
end else smod_cnt_r <= #1 1'b1;
|
end else smod_cnt_r <= #1 1'b1;
|
end else begin
|
end else begin
|
r_int <= #1 1'b0;
|
r_int <= #1 1'b0;
|
if (sam_cnt==3'b011)
|
if (sam_cnt==3'b011)
|
if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
|
if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
|
sbuf_rxd_tmp[re_count] <= #1 sample[0];
|
sbuf_rxd_tmp[re_count] <= #1 sample[0];
|
else
|
else
|
sbuf_rxd_tmp[re_count] <= #1 sample[1];
|
sbuf_rxd_tmp[re_count] <= #1 sample[1];
|
else begin
|
else begin
|
sample[sam_cnt[1:0]] <= #1 rxd;
|
sample[sam_cnt[1:0]] <= #1 rxd;
|
sam_cnt <= #1 sam_cnt +1'b1;
|
sam_cnt <= #1 sam_cnt +1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end else begin
|
end else begin
|
case (scon[7:6])
|
case (scon[7:6])
|
2'b00: begin
|
2'b00: begin
|
if ((scon[4]) & !(scon[0]) & !(r_int)) begin
|
if ((scon[4]) & !(scon[0]) & !(r_int)) begin
|
receive <= #1 1'b1;
|
receive <= #1 1'b1;
|
end
|
end
|
end
|
end
|
2'b10: begin
|
2'b10: begin
|
if ((rxd_buf) & !(rxd)) begin
|
if ((rxd_buf) & !(rxd)) begin
|
receive <= #1 1'b1;
|
receive <= #1 1'b1;
|
end
|
end
|
end
|
end
|
default: begin
|
default: begin
|
if ((rxd_buf) & !(rxd)) begin
|
if ((rxd_buf) & !(rxd)) begin
|
re_start <= #1 1'b1;
|
re_start <= #1 1'b1;
|
end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
|
end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
|
re_start <= #1 1'b0;
|
re_start <= #1 1'b0;
|
receive <= 1'b1;
|
receive <= 1'b1;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
|
|
sample <= #1 3'b000;
|
sample <= #1 3'b000;
|
sam_cnt <= #1 3'b000;
|
sam_cnt <= #1 3'b000;
|
re_count <= #1 4'd0;
|
re_count <= #1 4'd0;
|
sbuf_rxd_tmp <= #1 11'd0;
|
sbuf_rxd_tmp <= #1 11'd0;
|
r_int <= #1 1'b0;
|
r_int <= #1 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) data_out <= #1 8'h0;
|
if (rst) data_out <= #1 8'h0;
|
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
|
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
|
(wr_addr==`OC8051_SFR_SCON))) begin
|
(wr_addr==`OC8051_SFR_SCON))) begin
|
data_out <= #1 data_in;
|
data_out <= #1 data_in;
|
end else begin
|
end else begin
|
case (rd_addr)
|
case (rd_addr)
|
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
|
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
|
`OC8051_SFR_PCON: data_out <= #1 pcon;
|
`OC8051_SFR_PCON: data_out <= #1 pcon;
|
default: data_out <= #1 scon;
|
default: data_out <= #1 scon;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
trans_buf <= #1 1'b0;
|
trans_buf <= #1 1'b0;
|
receive_buf <= #1 1'b0;
|
receive_buf <= #1 1'b0;
|
t1_ow_buf <= #1 1'b0;
|
t1_ow_buf <= #1 1'b0;
|
rxd_buf <= #1 1'b0;
|
rxd_buf <= #1 1'b0;
|
end else begin
|
end else begin
|
trans_buf <= #1 trans;
|
trans_buf <= #1 trans;
|
receive_buf <= #1 receive;
|
receive_buf <= #1 receive;
|
t1_ow_buf <= #1 t1_ow;
|
t1_ow_buf <= #1 t1_ow;
|
rxd_buf <= #1 rxd;
|
rxd_buf <= #1 rxd;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) bit_out <= #1 1'b0;
|
if (rst) bit_out <= #1 1'b0;
|
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
|
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
|
bit_out <= #1 bit_in;
|
bit_out <= #1 bit_in;
|
end else
|
end else
|
bit_out <= #1 scon[rd_addr[2:0]];
|
bit_out <= #1 scon[rd_addr[2:0]];
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|