//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// 8051 wishbone interface to instruction rom ////
|
//// 8051 wishbone interface to instruction rom ////
|
//// ////
|
//// ////
|
//// This file is part of the 8051 cores project ////
|
//// This file is part of the 8051 cores project ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// http://www.opencores.org/cores/8051/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2003/04/03 19:19:02 simont
|
|
// change adr_i and adr_o length.
|
|
//
|
// Revision 1.2 2003/01/13 14:14:41 simont
|
// Revision 1.2 2003/01/13 14:14:41 simont
|
// replace some modules
|
// replace some modules
|
//
|
//
|
// Revision 1.1 2002/10/28 16:42:08 simont
|
// Revision 1.1 2002/10/28 16:42:08 simont
|
// initial import
|
// initial import
|
//
|
//
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "oc8051_timescale.v"
|
`include "oc8051_timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
|
|
module oc8051_wb_iinterface(rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
|
module oc8051_wb_iinterface(rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
|
dat_i, cyc_o, adr_o, ack_i, stb_o);
|
dat_i, cyc_o, adr_o, ack_i, stb_o);
|
//
|
//
|
// rst (in) reset - pin
|
// rst (in) reset - pin
|
// clk (in) clock - pini
|
// clk (in) clock - pini
|
input rst, clk;
|
input rst, clk;
|
|
|
//
|
//
|
// interface to oc8051 cpu
|
// interface to oc8051 cpu
|
//
|
//
|
// adr_i (in) address
|
// adr_i (in) address
|
// dat_o (out) data output
|
// dat_o (out) data output
|
// stb_i (in) strobe
|
// stb_i (in) strobe
|
// ack_o (out) acknowledge
|
// ack_o (out) acknowledge
|
// cyc_i (in) cycle
|
// cyc_i (in) cycle
|
input stb_i, cyc_i;
|
input stb_i, cyc_i;
|
input [15:0] adr_i;
|
input [15:0] adr_i;
|
output ack_o;
|
output ack_o;
|
output [31:0] dat_o;
|
output [31:0] dat_o;
|
|
|
//
|
//
|
// interface to instruction rom
|
// interface to instruction rom
|
//
|
//
|
// adr_o (out) address
|
// adr_o (out) address
|
// dat_i (in) data input
|
// dat_i (in) data input
|
// stb_o (out) strobe
|
// stb_o (out) strobe
|
// ack_i (in) acknowledge
|
// ack_i (in) acknowledge
|
// cyc_o (out) cycle
|
// cyc_o (out) cycle
|
input ack_i;
|
input ack_i;
|
input [31:0] dat_i;
|
input [31:0] dat_i;
|
output stb_o, cyc_o;
|
output stb_o, cyc_o;
|
output [15:0] adr_o;
|
output [15:0] adr_o;
|
|
|
//
|
//
|
// internal bufers and wires
|
// internal bufers and wires
|
//
|
//
|
reg [15:0] adr;
|
reg [15:0] adr;
|
reg stb;
|
//reg stb;
|
|
|
assign ack_o = ack_i;
|
assign ack_o = ack_i;
|
assign dat_o = dat_i;
|
assign dat_o = dat_i;
|
assign stb_o = stb || ack_i;
|
assign stb_o = stb_i || ack_i;
|
assign cyc_o = stb;
|
assign cyc_o = stb_i || ack_i;
|
assign adr_o = ack_i ? adr : adr_i;
|
assign adr_o = ack_i ? adr : adr_i;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
stb <= #1 1'b0;
|
// stb <= #1 1'b0;
|
adr <= #1 16'h0000;
|
adr <= #1 16'h0000;
|
end else begin
|
end else begin
|
stb <= #1 stb_i;
|
// stb <= #1 stb_i;
|
adr <= #1 adr_i;
|
adr <= #1 adr_i;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
