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AVRASM ver. 1.30 COUNTER.ASM Sun Jul 07 15:58:37 2002
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AVRASM ver. 1.30 COUNTER.ASM Sun Jul 07 15:58:37 2002
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; This program is for simulation purpose
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; This program is for simulation purpose
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; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D)
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; It demo how the MCU output 3, 2 and 1 to each port (Port B, Port C and Port D)
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; There are 3 approaches used in accomplishing the above task
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; There are 3 approaches used in accomplishing the above task
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.include "riscmcu.inc"
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.include "riscmcu.inc"
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;***** I/O Register Definitions
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;***** I/O Register Definitions
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.equ SREG =$3f
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.equ SREG =$3f
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.equ GIMSK =$3b
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.equ GIMSK =$3b
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.equ TIMSK =$39
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.equ TIMSK =$39
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.equ TIFR =$38
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.equ TIFR =$38
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.equ MCUCR =$35
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.equ MCUCR =$35
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.equ TCCR0 =$33
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.equ TCCR0 =$33
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.equ TCNT0 =$32
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.equ TCNT0 =$32
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.equ PORTB =$18
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.equ PORTB =$18
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.equ DDRB =$17
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.equ DDRB =$17
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.equ PINB =$16
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.equ PINB =$16
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.equ PORTC =$15
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.equ PORTC =$15
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.equ DDRC =$14
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.equ DDRC =$14
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.equ PINC =$13
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.equ PINC =$13
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.equ PORTD =$12
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.equ PORTD =$12
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.equ DDRD =$11
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.equ DDRD =$11
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.equ PIND =$10
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.equ PIND =$10
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;***** Bit Definitions
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;***** Bit Definitions
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.equ INT0 =6
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.equ INT0 =6
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.equ TOIE0 =1
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.equ TOIE0 =1
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.equ TOV0 =1
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.equ TOV0 =1
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.equ ISC01 =1
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.equ ISC01 =1
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.equ ISC00 =0
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.equ ISC00 =0
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.equ CS02 =2
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.equ CS02 =2
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.equ CS01 =1
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.equ CS01 =1
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.equ CS00 =0
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.equ CS00 =0
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.def ZP =r30
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.def ZP =r30
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.def B = r16
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.def B = r16
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.def C = r17
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.def C = r17
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.def D = r18
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.def D = r18
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.def TEMP = r19
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.def TEMP = r19
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000000 c002 rjmp reset ; reset vector
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000000 c002 rjmp reset ; reset vector
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000001 9508 ret ; external interrupt vertor(not use)
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000001 9508 ret ; external interrupt vertor(not use)
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000002 9508 ret ; timer overflow interrupt vertor (not use)
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000002 9508 ret ; timer overflow interrupt vertor (not use)
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reset:
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reset:
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000003 2733 clr TEMP ; r19 = 00
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000003 2733 clr TEMP ; r19 = 00
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000004 9530 com TEMP ; r19 = FF
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000004 9530 com TEMP ; r19 = FF
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000005 bb37 out DDRB,TEMP ; set all Port B pins as output
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000005 bb37 out DDRB,TEMP ; set all Port B pins as output
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000006 bb34 out DDRC,TEMP ; set all Port C pins as output
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000006 bb34 out DDRC,TEMP ; set all Port C pins as output
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000007 bb31 out DDRD,TEMP ; set all Port D pins as output
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000007 bb31 out DDRD,TEMP ; set all Port D pins as output
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; Approach 1, output to Port B
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; Approach 1, output to Port B
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000008 e003 ldi B,3 ; r16 = 03
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000008 e003 ldi B,3 ; r16 = 03
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000009 bb08 again1: out PORTB,B ; Port B now output 03
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000009 bb08 again1: out PORTB,B ; Port B now output 03
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00000a 950a dec B ; r16 = r16 - 1
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00000a 950a dec B ; r16 = r16 - 1
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00000b 3000 cpi B,0 ; if r16 = 0,
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00000b 3000 cpi B,0 ; if r16 = 0,
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00000c f7e1 brne again1 ; branch to again1
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00000c f7e1 brne again1 ; branch to again1
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; Approach 2, output to Port C
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; Approach 2, output to Port C
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00000d 2733 clr TEMP ; r19 = 00
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00000d 2733 clr TEMP ; r19 = 00
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00000e 9513 inc C ; r17 = 01
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00000e 9513 inc C ; r17 = 01
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00000f 9513 inc C ; r17 = 02
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00000f 9513 inc C ; r17 = 02
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000010 9513 inc C ; r17 = 03
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000010 9513 inc C ; r17 = 03
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000011 bb15 again2: out PORTC,C ; Port C now output 03
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000011 bb15 again2: out PORTC,C ; Port C now output 03
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000012 5011 subi C,1 ; r17 = r17 - 1
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000012 5011 subi C,1 ; r17 = r17 - 1
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000013 1313 cpse C,TEMP ; if r17 != r19 (means if r17 != 0),
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000013 1313 cpse C,TEMP ; if r17 != r19 (means if r17 != 0),
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000014 cffc rjmp again2 ; branch to again2
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000014 cffc rjmp again2 ; branch to again2
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; Approach 3, output to Port D
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; Approach 3, output to Port D
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000015 2722 clr D ; r18 = 00
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000015 2722 clr D ; r18 = 00
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000016 5f2d subi D,-3 ; r18 = r18 - (-3) = 03
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000016 5f2d subi D,-3 ; r18 = r18 - (-3) = 03
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000017 bb22 again3: out PORTD,D ; Port D now output 03
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000017 bb22 again3: out PORTD,D ; Port D now output 03
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000018 952a dec D ; r18 = r18 -1
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000018 952a dec D ; r18 = r18 -1
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000019 b73f in TEMP,SREG ; transfer the value of SR to R19
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000019 b73f in TEMP,SREG ; transfer the value of SR to R19
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00001a ff31 sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction
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00001a ff31 sbrs TEMP,1 ; if bit 1 in R19 (the Z-flag) is set, skip the next instruction
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00001b cffb rjmp again3 ; else branch to again3
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00001b cffb rjmp again3 ; else branch to again3
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00001c cfff end: rjmp end ; Branch Forever
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00001c cfff end: rjmp end ; Branch Forever
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00001d 9478 sei ; (Set I-Bit in SR) This 2 instructions won't execute
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00001d 9478 sei ; (Set I-Bit in SR) This 2 instructions won't execute
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00001e 9468 set ; (Set T-Bit in SR) even they are fetched to the IR
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00001e 9468 set ; (Set T-Bit in SR) even they are fetched to the IR
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Assembly complete with no errors.
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Assembly complete with no errors.
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