----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- WISHBONE RISCMCU IP Core ----
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---- WISHBONE RISCMCU IP Core ----
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---- ----
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---- ----
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---- This file is part of the RISCMCU project ----
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---- This file is part of the RISCMCU project ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library lpm;
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library lpm;
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use lpm.lpm_components.all;
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use lpm.lpm_components.all;
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entity v_alu is
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entity v_alu is
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port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
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port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
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c2a, c2b : in std_logic;
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c2a, c2b : in std_logic;
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asel : in integer range 0 to 1;
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asel : in integer range 0 to 1;
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bsel : in integer range 0 to 3;
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bsel : in integer range 0 to 3;
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bitsel : in integer range 0 to 7;
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bitsel : in integer range 0 to 7;
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set : in std_logic;
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set : in std_logic;
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c_flag, t_flag : in std_logic;
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c_flag, t_flag : in std_logic;
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add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
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add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
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cpse, skiptest : in std_logic;
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cpse, skiptest : in std_logic;
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wcarry : in std_logic;
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wcarry : in std_logic;
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logicsel : in integer range 0 to 3;
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logicsel : in integer range 0 to 3;
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rightsel : in integer range 0 to 2;
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rightsel : in integer range 0 to 2;
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dirsel : in integer range 0 to 1;
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dirsel : in integer range 0 to 1;
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clk, clrn : in std_logic;
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clk, clrn : in std_logic;
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c : buffer std_logic_vector(7 downto 0);
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c : buffer std_logic_vector(7 downto 0);
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tosr : buffer std_logic_vector (6 downto 0);
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tosr : buffer std_logic_vector (6 downto 0);
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skip : out std_logic
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skip : out std_logic
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);
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);
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end v_alu;
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end v_alu;
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architecture alu of v_alu is
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architecture alu of v_alu is
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signal a, b : std_logic_vector(7 downto 0);
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signal a, b : std_logic_vector(7 downto 0);
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signal sr : std_logic_vector(6 downto 0);
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signal sr : std_logic_vector(6 downto 0);
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signal cin, overflow, cout : std_logic;
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signal cin, overflow, cout : std_logic;
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signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);
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signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);
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begin
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begin
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-- Operand Fetch Unit --
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-- Operand Fetch Unit --
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process(clrn, clk)
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process(clrn, clk)
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begin
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begin
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if clrn = '0' then
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if clrn = '0' then
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a <= "00000000";
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a <= "00000000";
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b <= "00000000";
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b <= "00000000";
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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case asel is
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case asel is
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when 0 =>
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when 0 =>
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if c2a = '1' then
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if c2a = '1' then
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a <= c;
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a <= c;
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else
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else
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a <= reg_rd;
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a <= reg_rd;
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end if;
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end if;
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when 1 =>
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when 1 =>
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a <= "00000000";
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a <= "00000000";
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end case;
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end case;
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case bsel is
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case bsel is
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when 0 =>
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when 0 =>
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if c2b = '1' then
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if c2b = '1' then
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b <= c;
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b <= c;
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else
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else
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b <= reg_rr;
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b <= reg_rr;
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end if;
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end if;
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when 1 =>
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when 1 =>
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b <= reg_rd;
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b <= reg_rd;
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when 2 =>
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when 2 =>
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b <= imm_value;
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b <= imm_value;
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when 3 =>
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when 3 =>
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b <= "00000001";
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b <= "00000001";
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- Execution Unit --
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-- Execution Unit --
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cin <= c_flag when add = '1' and wcarry = '1' else
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cin <= c_flag when add = '1' and wcarry = '1' else
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'0' when add = '1' and wcarry = '0' else
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'0' when add = '1' and wcarry = '0' else
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not c_flag when wcarry = '1' else
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not c_flag when wcarry = '1' else
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'1';
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'1';
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-- Adder-Subtracter
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-- Adder-Subtracter
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adder1 : lpm_add_sub
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adder1 : lpm_add_sub
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generic map(lpm_width => 8)
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generic map(lpm_width => 8)
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port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
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port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
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-- Logic Unit
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-- Logic Unit
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with logicsel select
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with logicsel select
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logic_out <= a and b when 0, -- and, andi
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logic_out <= a and b when 0, -- and, andi
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a or b when 1, -- or, ori
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a or b when 1, -- or, ori
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a xor b when 2, -- eor
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a xor b when 2, -- eor
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not a when 3; -- com
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not a when 3; -- com
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-- Shifter
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-- Shifter
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right_out(6 downto 0) <= a(7 downto 1);
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right_out(6 downto 0) <= a(7 downto 1);
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with rightsel select
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with rightsel select
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right_out(7) <= '0' when 0, -- lsr
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right_out(7) <= '0' when 0, -- lsr
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c_flag when 1, -- ror
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c_flag when 1, -- ror
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a(7) when 2; -- asr
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a(7) when 2; -- asr
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-- Direct Unit
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-- Direct Unit
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with dirsel select
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with dirsel select
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dir_out <= b when 0, -- ldi, mov
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dir_out <= b when 0, -- ldi, mov
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(a(3 downto 0) & a(7 downto 4)) when 1; -- swap
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(a(3 downto 0) & a(7 downto 4)) when 1; -- swap
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-- Bit Loader
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-- Bit Loader
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process(bld, bitsel, a, t_flag, set)
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process(bld, bitsel, a, t_flag, set)
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begin
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begin
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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if i /= bitsel then
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if i /= bitsel then
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bldcbi_out(i) <= a(i);
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bldcbi_out(i) <= a(i);
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elsif bld = '1' then
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elsif bld = '1' then
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bldcbi_out(i) <= t_flag;
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bldcbi_out(i) <= t_flag;
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else
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else
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bldcbi_out(i) <= set;
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bldcbi_out(i) <= set;
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end if;
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end if;
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end loop;
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end loop;
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end process;
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end process;
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-- Results to Data Bus
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-- Results to Data Bus
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process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
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process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
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begin
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begin
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c <= "ZZZZZZZZ";
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c <= "ZZZZZZZZ";
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-- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg
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-- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg
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if add = '1' or subcp = '1' then
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if add = '1' or subcp = '1' then
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c <= sum;
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c <= sum;
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end if;
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end if;
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-- and, andi, or, ori, eor, com
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-- and, andi, or, ori, eor, com
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if logic = '1' then
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if logic = '1' then
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c <= logic_out;
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c <= logic_out;
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end if;
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end if;
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-- lsr, lsr, asr
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-- lsr, lsr, asr
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if right = '1' then
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if right = '1' then
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c <= right_out;
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c <= right_out;
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end if;
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end if;
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-- ldi, mov, swap
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-- ldi, mov, swap
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if dir = '1' then
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if dir = '1' then
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c <= dir_out;
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c <= dir_out;
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end if;
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end if;
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-- bld, cbisbi
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-- bld, cbisbi
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if bld = '1' or cbisbi = '1' then
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if bld = '1' or cbisbi = '1' then
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c <= bldcbi_out;
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c <= bldcbi_out;
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end if;
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end if;
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-- out, st z, st z+, st -z
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-- out, st z, st z+, st -z
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if pass_a = '1' then
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if pass_a = '1' then
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c <= a;
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c <= a;
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end if;
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end if;
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end process;
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end process;
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-- Skip Evaluation Unit --
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-- Skip Evaluation Unit --
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process(cpse, skiptest, a, b, set, bitsel, c)
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process(cpse, skiptest, a, b, set, bitsel, c)
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begin
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begin
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skip <= '0';
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skip <= '0';
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-- cpse
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-- cpse
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if cpse = '1' then
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if cpse = '1' then
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if a = b then
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if a = b then
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skip <= '1';
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skip <= '1';
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end if;
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end if;
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-- sbrc, sbrs
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-- sbrc, sbrs
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elsif skiptest = '1' then
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elsif skiptest = '1' then
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if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then
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if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then
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skip <= '1';
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skip <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Flags Evaluation Unit --
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-- Flags Evaluation Unit --
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process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
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process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
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begin
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begin
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-- C sr(0)
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-- C sr(0)
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if add = '1' then
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if add = '1' then
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sr(0) <= cout;
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sr(0) <= cout;
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elsif right = '1' then
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elsif right = '1' then
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sr(0) <= a(0);
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sr(0) <= a(0);
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elsif logic = '1' then -- com
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elsif logic = '1' then -- com
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sr(0) <= '1';
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sr(0) <= '1';
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else -- subcp
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else -- subcp
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sr(0) <= not cout;
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sr(0) <= not cout;
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--sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));
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--sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));
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end if;
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end if;
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-- Z sr(1)
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-- Z sr(1)
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if (add = '1' or subcp = '1') and sum = "00000000" then
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if (add = '1' or subcp = '1') and sum = "00000000" then
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sr(1) <= '1';
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sr(1) <= '1';
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elsif logic = '1' and logic_out = "00000000" then
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elsif logic = '1' and logic_out = "00000000" then
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sr(1) <= '1';
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sr(1) <= '1';
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elsif right = '1' and right_out = "00000000" then
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elsif right = '1' and right_out = "00000000" then
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sr(1) <= '1';
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sr(1) <= '1';
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else
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else
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sr(1) <= '0';
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sr(1) <= '0';
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end if;
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end if;
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-- N sr(2)
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-- N sr(2)
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if (add = '1' or subcp = '1') and sum(7) = '1' then
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if (add = '1' or subcp = '1') and sum(7) = '1' then
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sr(2) <= '1';
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sr(2) <= '1';
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elsif logic = '1' and logic_out(7) = '1' then
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elsif logic = '1' and logic_out(7) = '1' then
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sr(2) <= '1';
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sr(2) <= '1';
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elsif right = '1' and right_out(7) = '1' then
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elsif right = '1' and right_out(7) = '1' then
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sr(2) <= '1';
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sr(2) <= '1';
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else
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else
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sr(2) <= '0';
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sr(2) <= '0';
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end if;
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end if;
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-- V sr(3)
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-- V sr(3)
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if right = '1' then
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if right = '1' then
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sr(3) <= right_out(7) xor a(0);
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sr(3) <= right_out(7) xor a(0);
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elsif logic = '1' then
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elsif logic = '1' then
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sr(3) <= '0';
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sr(3) <= '0';
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else
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else
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sr(3) <= overflow;
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sr(3) <= overflow;
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end if;
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end if;
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-- S sr(4)
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-- S sr(4)
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sr(4) <= sr(2) xor sr(3);
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sr(4) <= sr(2) xor sr(3);
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|
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-- H sr(5)
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-- H sr(5)
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if add = '1' then
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if add = '1' then
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sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));
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sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));
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else -- subcp
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else -- subcp
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sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));
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sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));
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end if;
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end if;
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-- T sr(6)
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-- T sr(6)
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sr(6) <= a(bitsel);
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sr(6) <= a(bitsel);
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|
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end process;
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end process;
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tosr <= sr;
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tosr <= sr;
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end alu;
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end alu;
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