----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- WISHBONE RISCMCU IP Core ----
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---- WISHBONE RISCMCU IP Core ----
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---- ----
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---- ----
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---- This file is part of the RISCMCU project ----
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---- This file is part of the RISCMCU project ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity v_rom is
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entity v_rom is
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port( pc : in std_logic_vector(8 downto 0);
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port( pc : in std_logic_vector(8 downto 0);
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instruction : out std_logic_vector(15 downto 0));
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instruction : out std_logic_vector(15 downto 0));
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end v_rom;
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end v_rom;
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architecture rom of v_rom is
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architecture rom of v_rom is
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component LPM_ROM
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component LPM_ROM
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generic (
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generic (
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LPM_WIDTH: integer := 16;
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LPM_WIDTH: integer := 16;
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LPM_WIDTHAD: integer := 9;
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LPM_WIDTHAD: integer := 9;
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LPM_NUMWORDS: integer := 512;
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LPM_NUMWORDS: integer := 512;
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LPM_FILE: string := "program.mif";
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LPM_FILE: string := "program.mif";
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LPM_ADDRESS_CONTROL: string := "UNREGISTERED";
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LPM_ADDRESS_CONTROL: string := "UNREGISTERED";
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LPM_OUTDATA: string := "UNREGISTERED"
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LPM_OUTDATA: string := "UNREGISTERED"
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);
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);
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port (
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port (
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ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
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ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
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inclock: IN STD_LOGIC := '0';
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inclock: IN STD_LOGIC := '0';
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outclock: IN STD_LOGIC := '0';
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outclock: IN STD_LOGIC := '0';
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memenab: IN STD_LOGIC := '1';
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memenab: IN STD_LOGIC := '1';
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Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
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Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
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);
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);
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end component;
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end component;
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signal gnd, vcc : std_logic;
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signal gnd, vcc : std_logic;
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begin
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begin
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vcc <= '1';
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vcc <= '1';
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gnd <= '0';
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gnd <= '0';
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v1 : LPM_ROM
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v1 : LPM_ROM
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port map (address => pc, memenab => vcc, q => instruction);
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port map (address => pc, memenab => vcc, q => instruction);
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end rom;
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end rom;
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