-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- TB_vdu8 Test Bench
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-- TB_vdu8 Test Bench
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- (c) Bertrand Cuzeau
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-- (c) Bertrand Cuzeau
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--
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--
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Library IEEE;
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Library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use STD.textio.all;
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use STD.textio.all;
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use IEEE.std_logic_textio.all;
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use IEEE.std_logic_textio.all;
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Entity TB_vdu8 is end;
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Entity TB_vdu8 is end;
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Architecture TEST of tb_vdu8 is
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Architecture TEST of tb_vdu8 is
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subtype Byte is std_logic_vector (7 downto 0);
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subtype Byte is std_logic_vector (7 downto 0);
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signal vdu_clk_in : std_logic := '0';
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signal vdu_clk_in : std_logic := '0';
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signal cpu_clk_out : std_logic;
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signal cpu_clk_out : std_logic;
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signal vdu_rst : std_logic;
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signal vdu_rst : std_logic;
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signal vdu_cs : std_logic := '0';
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signal vdu_cs : std_logic := '0';
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signal vdu_rw : std_logic := '1';
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signal vdu_rw : std_logic := '1';
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signal vdu_addr : std_logic_vector(2 downto 0) := "000";
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signal vdu_addr : std_logic_vector(2 downto 0) := "000";
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signal vdu_data_in : std_logic_vector(7 downto 0);
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signal vdu_data_in : std_logic_vector(7 downto 0);
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signal vdu_data_out : std_logic_vector(7 downto 0);
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signal vdu_data_out : std_logic_vector(7 downto 0);
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signal vga_red_o : std_logic;
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signal vga_red_o : std_logic;
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signal vga_green_o : std_logic;
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signal vga_green_o : std_logic;
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signal vga_blue_o : std_logic;
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signal vga_blue_o : std_logic;
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signal vga_hsync_o : std_logic;
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signal vga_hsync_o : std_logic;
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signal vga_vsync_o : std_logic;
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signal vga_vsync_o : std_logic;
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constant Msg : string := "Hello! X";
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constant Msg : string := "Hello! X";
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signal done : boolean;
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signal done : boolean;
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constant Period : time := 10 ns;
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constant Period : time := 10 ns;
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begin
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begin
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vdu_clk_in <= '0' when Done else not vdu_clk_in after Period / 2;
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vdu_clk_in <= '0' when Done else not vdu_clk_in after Period / 2;
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vdu_rst <= '1', '0' after 16 * Period;
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vdu_rst <= '1', '0' after 16 * Period;
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vdu: Entity work.vdu8
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vdu: Entity work.vdu8
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port map (
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port map (
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vdu_clk_in => vdu_clk_in ,
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vdu_clk_in => vdu_clk_in ,
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cpu_clk_out => cpu_clk_out ,
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cpu_clk_out => cpu_clk_out ,
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vdu_rst => vdu_rst ,
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vdu_rst => vdu_rst ,
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vdu_cs => vdu_cs ,
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vdu_cs => vdu_cs ,
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vdu_rw => vdu_rw ,
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vdu_rw => vdu_rw ,
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vdu_addr => vdu_addr ,
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vdu_addr => vdu_addr ,
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vdu_data_in => vdu_data_in ,
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vdu_data_in => vdu_data_in ,
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vdu_data_out => vdu_data_out ,
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vdu_data_out => vdu_data_out ,
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vga_red_o => vga_red_o ,
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vga_red_o => vga_red_o ,
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vga_green_o => vga_green_o ,
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vga_green_o => vga_green_o ,
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vga_blue_o => vga_blue_o ,
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vga_blue_o => vga_blue_o ,
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vga_hsync_o => vga_hsync_o ,
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vga_hsync_o => vga_hsync_o ,
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vga_vsync_o => vga_vsync_o
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vga_vsync_o => vga_vsync_o
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);
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);
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process
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process
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procedure Writebyte (b : Byte; Addr : integer) is
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procedure Writebyte (b : Byte; Addr : integer) is
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begin
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begin
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wait for 500 ns;
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wait for 500 ns;
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vdu_cs <= '1';
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vdu_cs <= '1';
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vdu_data_in <= b;
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vdu_data_in <= b;
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vdu_addr <= std_logic_vector(to_unsigned(Addr,3));
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vdu_addr <= std_logic_vector(to_unsigned(Addr,3));
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wait for 100 ns;
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wait for 100 ns;
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vdu_rw <= '0';
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vdu_rw <= '0';
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wait for 200 ns;
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wait for 200 ns;
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vdu_rw <= '1';
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vdu_rw <= '1';
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vdu_cs <= '0';
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vdu_cs <= '0';
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end procedure;
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end procedure;
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procedure WriteChar (c : character; color:byte; x:integer; y:integer; offs:integer) is
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procedure WriteChar (c : character; color:byte; x:integer; y:integer; offs:integer) is
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begin
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begin
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WriteByte(std_logic_vector(to_unsigned(character'pos(c),8)),0);
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WriteByte(std_logic_vector(to_unsigned(character'pos(c),8)),0);
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WriteByte(color,1);
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WriteByte(color,1);
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WriteByte(std_logic_vector(to_unsigned(x,8)),2);
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WriteByte(std_logic_vector(to_unsigned(x,8)),2);
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WriteByte(std_logic_vector(to_unsigned(y,8)),3);
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WriteByte(std_logic_vector(to_unsigned(y,8)),3);
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WriteByte(std_logic_vector(to_unsigned(offs,8)),4);
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WriteByte(std_logic_vector(to_unsigned(offs,8)),4);
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end procedure;
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end procedure;
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begin
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begin
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vdu_data_in <= x"00";
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vdu_data_in <= x"00";
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wait until vga_hsync_o='0';
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wait until vga_hsync_o='0';
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for i in Msg'range loop
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for i in Msg'range loop
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WriteChar(Msg(i), x"17",i,i,1); -- ?? bgB bgG bgR Blink?? fgB fgG fgR <<< TBV
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WriteChar(Msg(i), x"17",i,i,1); -- ?? bgB bgG bgR Blink?? fgB fgG fgR <<< TBV
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end loop;
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end loop;
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wait until vga_vsync_o='0';
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wait until vga_vsync_o='0';
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wait for 5 ms;
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wait for 5 ms;
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report "End of Simulation";
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report "End of Simulation";
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done <= true;
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done <= true;
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wait;
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wait;
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end process;
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end process;
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end architecture TEST;
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end architecture TEST;
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