-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- ACIA Clock Divider for System09
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-- ACIA Clock Divider for System09
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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|
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package bit_funcs is
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package bit_funcs is
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function log2(v: in natural) return natural;
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function log2(v: in natural) return natural;
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end package bit_funcs;
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end package bit_funcs;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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package body bit_funcs is
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package body bit_funcs is
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function log2(v: in natural) return natural is
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function log2(v: in natural) return natural is
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variable n: natural;
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variable n: natural;
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variable logn: natural;
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variable logn: natural;
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begin
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begin
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n := 1;
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n := 1;
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for i in 0 to 128 loop
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for i in 0 to 128 loop
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logn := i;
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logn := i;
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exit when (n>=v);
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exit when (n>=v);
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n := n * 2;
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n := n * 2;
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end loop;
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end loop;
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return logn;
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return logn;
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end function log2;
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end function log2;
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end package body bit_funcs;
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end package body bit_funcs;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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library work;
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library work;
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use work.bit_funcs.all;
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use work.bit_funcs.all;
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entity ACIA_Clock is
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entity ACIA_Clock is
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generic (
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generic (
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SYS_Clock_Frequency : integer;
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SYS_Clock_Frequency : integer;
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ACIA_Clock_Frequency : integer
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ACIA_Clock_Frequency : integer
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);
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);
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port(
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port(
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clk : in Std_Logic; -- System Clock input
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clk : in Std_Logic; -- System Clock input
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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);
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);
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end ACIA_Clock;
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end ACIA_Clock;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for ACIA_Clock
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-- Architecture for ACIA_Clock
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture rtl of ACIA_Clock is
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architecture rtl of ACIA_Clock is
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|
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constant FULL_CYCLE : integer := (SYS_Clock_Frequency / ACIA_Clock_Frequency);
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constant FULL_CYCLE : integer := (SYS_Clock_Frequency / ACIA_Clock_Frequency);
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constant HALF_CYCLE : integer := (FULL_CYCLE / 2);
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constant HALF_CYCLE : integer := (FULL_CYCLE / 2);
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signal ACIA_Count : Std_Logic_Vector(log2(FULL_CYCLE) downto 0) := (Others => '0');
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signal ACIA_Count : Std_Logic_Vector(log2(FULL_CYCLE) downto 0) := (Others => '0');
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|
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begin
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begin
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--
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--
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-- Baud Rate Clock Divider
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-- Baud Rate Clock Divider
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--
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--
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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--
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--
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--my_ACIA_clock: process( clk, ACIA_Count )
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--my_ACIA_clock: process( clk, ACIA_Count )
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my_ACIA_clock: process( clk )
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my_ACIA_clock: process( clk )
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begin
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begin
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if(clk'event and clk = '0') then
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if(clk'event and clk = '0') then
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if( ACIA_Count = (FULL_CYCLE - 1) ) then
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if( ACIA_Count = (FULL_CYCLE - 1) ) then
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ACIA_Clk <= '0';
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ACIA_Clk <= '0';
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ACIA_Count <= (others => '0'); --"000000";
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ACIA_Count <= (others => '0'); --"000000";
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else
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else
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if( ACIA_Count = (HALF_CYCLE - 1) ) then
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if( ACIA_Count = (HALF_CYCLE - 1) ) then
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ACIA_Clk <='1';
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ACIA_Clk <='1';
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end if;
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end if;
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ACIA_Count <= ACIA_Count + 1;
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ACIA_Count <= ACIA_Count + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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end rtl;
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end rtl;
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|
|
