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[/] [System09/] [rev_86/] [rtl/] [System09_Digilent_3S200/] [my_system09.ise] - Diff between revs 66 and 112

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Rev 66 Rev 112 
PK
 
PK
 

__OBJSTORE__/PK
 

__OBJSTORE__/PK
 
__OBJSTORE__/common/PK
 
__OBJSTORE__/common/PK
 
'__OBJSTORE__/common/HierarchicalDesign/PK
 
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VHDLOther MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE MixedModelsim-SE VerilogModelsim-SE VHDLISE Simulator (VHDL/Verilog)PROP_Synthesis_ToolXST (VHDL/Verilog)PROP_Top_Level_Module_TypeHDLPrecision (VHDL/Verilog)PROP_DevSpeed-5PROP_DevPackagepq208ft256PROP_DevDevicexc3s50xc3s200xc3s5000xc3s4000lxc3s4000xc3s2000xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s400vq100tq144-4PROP_TopDesignUnitArchitecture|my_system09|my_computerModule|my_system09PROP_tbwPostParTestbenchNamePROP_tbwTestbenchTargetLangVHDLVerilogPROP_tbwPostMapTestbenchNamePROP_tbwPostXlateTestbenchNamePROP_PostParSimModelName_timesim.vhdPROP_SimModelTargetmy_system09_timesim.vhdPROP_PostMapSimModelNamemy_system09_map.vhdPROP_PostXlateSimModelNamemy_system09_translate.vhdPROP_SimModelRenTopLevEntToPROP_SimModelGenArchOnlyPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROPEXT_xilxBitgCfg_Rate_spartan3Default (6)PROPEXT_xilxSynthAddBufg_spartan3PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on 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VHDLOther MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE MixedModelsim-SE VerilogModelsim-SE VHDLISE Simulator (VHDL/Verilog)PROP_Synthesis_ToolXST (VHDL/Verilog)PROP_Top_Level_Module_TypeHDLPrecision (VHDL/Verilog)PROP_DevSpeed-5PROP_DevPackagepq208ft256PROP_DevDevicexc3s50xc3s200xc3s5000xc3s4000lxc3s4000xc3s2000xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s400vq100tq144-4PROP_TopDesignUnitArchitecture|my_system09|my_computerModule|my_system09PROP_tbwPostParTestbenchNamePROP_tbwTestbenchTargetLangVHDLVerilogPROP_tbwPostMapTestbenchNamePROP_tbwPostXlateTestbenchNamePROP_PostParSimModelName_timesim.vhdPROP_SimModelTargetmy_system09_timesim.vhdPROP_PostMapSimModelNamemy_system09_map.vhdPROP_PostXlateSimModelNamemy_system09_translate.vhdPROP_SimModelRenTopLevEntToPROP_SimModelGenArchOnlyPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROPEXT_xilxBitgCfg_Rate_spartan3Default (6)PROPEXT_xilxSynthAddBufg_spartan3PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on 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