--===========================================================================--
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--===========================================================================--
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--
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--
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-- ACIA 6850 Test Bench
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-- ACIA 6850 Test Bench
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--
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--
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--
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--
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-- John Kent 6th February 2007
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-- John Kent 6th February 2007
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity ACIA_6850_testbench is
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entity ACIA_6850_testbench is
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end ACIA_6850_testbench;
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end ACIA_6850_testbench;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for ACIA 6850 Unit
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-- Architecture for ACIA 6850 Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of ACIA_6850_testbench is
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architecture behavior of ACIA_6850_testbench is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- CPU Interface signals
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal SysClk : Std_Logic;
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signal uart_reset : Std_Logic;
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signal uart_reset : Std_Logic;
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signal uart_cs : Std_Logic;
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signal uart_cs : Std_Logic;
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signal uart_rw : Std_Logic;
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signal uart_rw : Std_Logic;
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signal uart_addr : Std_Logic;
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signal uart_addr : Std_Logic;
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signal uart_data_in : Std_Logic_Vector(7 downto 0);
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signal uart_data_in : Std_Logic_Vector(7 downto 0);
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signal uart_data_out: Std_Logic_Vector(7 downto 0);
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signal uart_data_out: Std_Logic_Vector(7 downto 0);
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signal uart_irq : Std_Logic;
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signal uart_irq : Std_Logic;
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signal rxclk : Std_Logic;
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signal rxclk : Std_Logic;
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signal txclk : Std_Logic;
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signal txclk : Std_Logic;
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signal rxbit : Std_Logic;
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signal rxbit : Std_Logic;
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signal txbit : Std_Logic;
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signal txbit : Std_Logic;
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signal dcd_n : Std_Logic;
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signal dcd_n : Std_Logic;
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signal cts_n : Std_Logic;
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signal cts_n : Std_Logic;
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signal rts_n : Std_Logic;
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signal rts_n : Std_Logic;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- ACIA 6850 UART
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-- ACIA 6850 UART
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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component ACIA_6850
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component ACIA_6850
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port (
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port (
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--
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--
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-- CPU signals
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-- CPU signals
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--
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--
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clk : in Std_Logic; -- System Clock
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clk : in Std_Logic; -- System Clock
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rst : in Std_Logic; -- Reset input (active high)
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rst : in Std_Logic; -- Reset input (active high)
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cs : in Std_Logic; -- miniUART Chip Select
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cs : in Std_Logic; -- miniUART Chip Select
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rw : in Std_Logic; -- Read / Not Write
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rw : in Std_Logic; -- Read / Not Write
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irq : out Std_Logic; -- Interrupt
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irq : out Std_Logic; -- Interrupt
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Addr : in Std_Logic; -- Register Select
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Addr : in Std_Logic; -- Register Select
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DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
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DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
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DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
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DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
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--
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--
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-- Uart Signals
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-- Uart Signals
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--
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--
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RxC : in Std_Logic; -- Receive Baud Clock
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RxC : in Std_Logic; -- Receive Baud Clock
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TxC : in Std_Logic; -- Transmit Baud Clock
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TxC : in Std_Logic; -- Transmit Baud Clock
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RxD : in Std_Logic; -- Receive Data
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RxD : in Std_Logic; -- Receive Data
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TxD : out Std_Logic; -- Transmit Data
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TxD : out Std_Logic; -- Transmit Data
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DCD_n : in Std_Logic; -- Data Carrier Detect
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DCD_n : in Std_Logic; -- Data Carrier Detect
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CTS_n : in Std_Logic; -- Clear To Send
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CTS_n : in Std_Logic; -- Clear To Send
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RTS_n : out Std_Logic ); -- Request To send
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RTS_n : out Std_Logic ); -- Request To send
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end component; --================== End of entity ==============================--
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end component; --================== End of entity ==============================--
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Instantiation of internal components
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-- Instantiation of internal components
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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my_acia : ACIA_6850 port map (
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my_acia : ACIA_6850 port map (
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clk => SysClk,
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clk => SysClk,
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rst => uart_reset,
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rst => uart_reset,
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cs => uart_cs,
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cs => uart_cs,
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rw => uart_rw,
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rw => uart_rw,
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Irq => uart_irq,
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Irq => uart_irq,
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Addr => uart_addr,
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Addr => uart_addr,
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Datain => uart_data_in,
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Datain => uart_data_in,
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DataOut => uart_data_out,
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DataOut => uart_data_out,
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RxC => rxclk,
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RxC => rxclk,
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TxC => txclk,
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TxC => txclk,
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RxD => rxbit,
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RxD => rxbit,
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TxD => txbit,
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TxD => txbit,
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DCD_n => dcd_n,
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DCD_n => dcd_n,
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CTS_n => cts_n,
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CTS_n => cts_n,
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RTS_n => rts_n
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RTS_n => rts_n
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);
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);
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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tb : PROCESS
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variable count : integer;
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variable count : integer;
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BEGIN
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BEGIN
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cts_n <= '0';
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cts_n <= '0';
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dcd_n <= '0';
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dcd_n <= '0';
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for count in 0 to 4096 loop
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for count in 0 to 4096 loop
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if (count mod 16) = 0 then
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if (count mod 16) = 0 then
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rxclk <= '1';
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rxclk <= '1';
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txclk <= '1';
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txclk <= '1';
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elsif (count mod 16) = 8 then
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elsif (count mod 16) = 8 then
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rxclk <= '0';
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rxclk <= '0';
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txclk <= '0';
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txclk <= '0';
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end if;
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end if;
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case count is
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case count is
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when 0 =>
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when 0 =>
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uart_reset <= '1';
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uart_reset <= '1';
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uart_cs <= '0';
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uart_cs <= '0';
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uart_rw <= '1';
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uart_rw <= '1';
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uart_addr <= '0';
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uart_addr <= '0';
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uart_data_in <= "00000000";
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uart_data_in <= "00000000";
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rxbit <= '1';
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rxbit <= '1';
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when 1 =>
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when 1 =>
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uart_reset <= '0';
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uart_reset <= '0';
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when 3 =>
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when 3 =>
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uart_cs <= '1';
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uart_cs <= '1';
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uart_rw <= '0'; -- write control
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uart_rw <= '0'; -- write control
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uart_addr <= '0';
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uart_addr <= '0';
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uart_data_in <= "00010001";
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uart_data_in <= "00010001";
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when 4 =>
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when 4 =>
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uart_cs <= '0';
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uart_cs <= '0';
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uart_rw <= '1';
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uart_rw <= '1';
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uart_addr <= '0';
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uart_addr <= '0';
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uart_data_in <= "00000000";
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uart_data_in <= "00000000";
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when 5 =>
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when 5 =>
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uart_cs <= '1';
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uart_cs <= '1';
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uart_rw <= '0'; -- write data
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uart_rw <= '0'; -- write data
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uart_addr <= '1';
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uart_addr <= '1';
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uart_data_in <= "01010101";
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uart_data_in <= "01010101";
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when 6 =>
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when 6 =>
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uart_cs <= '0';
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uart_cs <= '0';
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uart_rw <= '1';
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uart_rw <= '1';
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uart_addr <= '1';
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uart_addr <= '1';
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uart_data_in <= "00000000";
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uart_data_in <= "00000000";
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when 256 =>
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when 256 =>
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rxbit <= '0'; -- start
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rxbit <= '0'; -- start
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when 512 =>
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when 512 =>
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rxbit <= '1'; -- bit 0
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rxbit <= '1'; -- bit 0
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when 768 =>
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when 768 =>
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rxbit <= '0'; -- bit 1
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rxbit <= '0'; -- bit 1
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when 1024 =>
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when 1024 =>
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rxbit <= '1'; -- bit 2
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rxbit <= '1'; -- bit 2
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when 1280 =>
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when 1280 =>
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rxbit <= '1'; -- bit3
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rxbit <= '1'; -- bit3
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when 1536 =>
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when 1536 =>
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rxbit <= '0'; -- bit 4
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rxbit <= '0'; -- bit 4
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when 1792 =>
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when 1792 =>
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rxbit <= '0'; -- bit 5
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rxbit <= '0'; -- bit 5
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when 2048 =>
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when 2048 =>
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rxbit <= '1'; -- bit 6
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rxbit <= '1'; -- bit 6
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when 2304 =>
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when 2304 =>
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rxbit <= '0'; -- bit 7
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rxbit <= '0'; -- bit 7
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when 2560 =>
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when 2560 =>
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rxbit <= '1'; -- stop 1
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rxbit <= '1'; -- stop 1
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when 2816 =>
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when 2816 =>
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rxbit <= '1'; -- stop 2
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rxbit <= '1'; -- stop 2
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when 3100 =>
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when 3100 =>
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uart_cs <= '1';
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uart_cs <= '1';
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uart_rw <= '1'; -- read control
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uart_rw <= '1'; -- read control
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uart_addr <= '0';
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uart_addr <= '0';
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when 3101 =>
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when 3101 =>
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uart_cs <= '0';
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uart_cs <= '0';
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uart_rw <= '1';
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uart_rw <= '1';
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uart_addr <= '0';
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uart_addr <= '0';
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when 3102 =>
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when 3102 =>
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uart_cs <= '1';
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uart_cs <= '1';
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uart_rw <= '1'; -- read data
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uart_rw <= '1'; -- read data
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uart_addr <= '1';
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uart_addr <= '1';
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when 3103 =>
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when 3103 =>
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uart_cs <= '0';
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uart_cs <= '0';
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uart_rw <= '1';
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uart_rw <= '1';
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uart_addr <= '1';
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uart_addr <= '1';
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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SysClk <= '1';
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SysClk <= '1';
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wait for 40 ns;
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wait for 40 ns;
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SysClk <= '0';
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SysClk <= '0';
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wait for 40 ns;
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wait for 40 ns;
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end loop;
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end loop;
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wait; -- will wait forever
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wait; -- will wait forever
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END PROCESS;
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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-- *** End Test Bench - User Defined Section ***
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end behavior; --===================== End of architecture =======================--
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end behavior; --===================== End of architecture =======================--
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