-- SPI bus master for System09 (http://members.optushome.com.au/jekent/system09/index.html)
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-- SPI bus master for System09 (http://members.optushome.com.au/jekent/system09/index.html)
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-- This core implements a SPI master interface. Transfer size is 4, 8, 12 or
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-- This core implements a SPI master interface. Transfer size is 4, 8, 12 or
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-- 16 bits. The SPI clock is 0 when idle, sampled on the rising edge of the SPI
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-- 16 bits. The SPI clock is 0 when idle, sampled on the rising edge of the SPI
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-- clock. The SPI clock is derived from the bus clock input divided
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-- clock. The SPI clock is derived from the bus clock input divided
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-- by 2, 4, 8 or 16.
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-- by 2, 4, 8 or 16.
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-- clk, reset, cs, rw, addr, data_in, data_out and irq represent the System09
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-- clk, reset, cs, rw, addr, data_in, data_out and irq represent the System09
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-- bus interface.
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-- bus interface.
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-- spi_clk, spi_mosi, spi_miso and spi_cs_n are the standard SPI signals meant
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-- spi_clk, spi_mosi, spi_miso and spi_cs_n are the standard SPI signals meant
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-- to be routed off-chip.
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-- to be routed off-chip.
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-- The SPI core provides for four register addresses that the CPU can read or
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-- The SPI core provides for four register addresses that the CPU can read or
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-- write:
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-- write:
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-- 0 -> DL: Data LSB
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-- 0 -> DL: Data LSB
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-- 1 -> DH: Data MSB
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-- 1 -> DH: Data MSB
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-- 2 -> CS: Command/Status
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-- 2 -> CS: Command/Status
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-- 3 -> CO: Config
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-- 3 -> CO: Config
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-- Write bits, CS:
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-- Write bits, CS:
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--
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--
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-- START CS[0]: Start transfer
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-- START CS[0]: Start transfer
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-- END CS[1]: Deselect device after transfer (or immediately if START = '0')
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-- END CS[1]: Deselect device after transfer (or immediately if START = '0')
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-- IRQEN CS[2]: Generate IRQ at end of transfer
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-- IRQEN CS[2]: Generate IRQ at end of transfer
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-- SPIAD CS[6:4]: SPI device address
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-- SPIAD CS[6:4]: SPI device address
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--
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--
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-- Read bits, CS:
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-- Read bits, CS:
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--
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--
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-- BUSY CS[0]: Currently transmitting data
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-- BUSY CS[0]: Currently transmitting data
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--
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--
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-- Write BITS, CO:
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-- Write BITS, CO:
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--
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--
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-- DIVIDE CO[1:0]: SPI clock divisor, 00=clk/2, 01=clk/4, 10=clk/8, 11=clk/16
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-- DIVIDE CO[1:0]: SPI clock divisor, 00=clk/2, 01=clk/4, 10=clk/8, 11=clk/16
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-- LENGTH CO[3:2]: Transfer length, 00=4 bits, 01=8 bits, 10=12 bits, 11=16 bits
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-- LENGTH CO[3:2]: Transfer length, 00=4 bits, 01=8 bits, 10=12 bits, 11=16 bits
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity spi_master is
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entity spi_master is
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port (
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port (
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clk, reset, cs, rw : in std_logic;
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clk, reset, cs, rw : in std_logic;
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addr : in std_logic_vector(1 downto 0);
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addr : in std_logic_vector(1 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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irq : out std_logic;
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spi_clk, spi_mosi : out std_logic;
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spi_clk, spi_mosi : out std_logic;
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spi_cs_n : out std_logic_vector(7 downto 0);
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spi_cs_n : out std_logic_vector(7 downto 0);
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spi_miso : in std_logic);
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spi_miso : in std_logic);
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end;
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end;
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architecture rtl of spi_master is
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architecture rtl of spi_master is
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-- State type of the SPI transfer state machine
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-- State type of the SPI transfer state machine
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type state_type is (s_idle, s_running);
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type state_type is (s_idle, s_running);
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signal state : state_type;
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signal state : state_type;
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-- Shift register
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-- Shift register
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signal shift_reg : std_logic_vector(15 downto 0);
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signal shift_reg : std_logic_vector(15 downto 0);
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-- Buffer to hold data to be sent
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-- Buffer to hold data to be sent
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signal spi_data_buf : std_logic_vector(15 downto 0);
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signal spi_data_buf : std_logic_vector(15 downto 0);
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-- Start transmission flag
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-- Start transmission flag
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signal start : std_logic;
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signal start : std_logic;
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-- Number of bits transfered
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-- Number of bits transfered
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signal count : std_logic_vector(3 downto 0);
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signal count : std_logic_vector(3 downto 0);
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-- Buffered SPI clock
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-- Buffered SPI clock
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signal spi_clk_buf : std_logic;
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signal spi_clk_buf : std_logic;
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-- Buffered SPI clock output
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-- Buffered SPI clock output
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signal spi_clk_out : std_logic;
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signal spi_clk_out : std_logic;
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-- Previous SPI clock state
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-- Previous SPI clock state
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signal prev_spi_clk : std_logic;
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signal prev_spi_clk : std_logic;
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-- Number of clk cycles-1 in this SPI clock period
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-- Number of clk cycles-1 in this SPI clock period
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signal spi_clk_count : std_logic_vector(2 downto 0);
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signal spi_clk_count : std_logic_vector(2 downto 0);
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-- SPI clock divisor
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-- SPI clock divisor
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signal spi_clk_divide : std_logic_vector(1 downto 0);
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signal spi_clk_divide : std_logic_vector(1 downto 0);
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-- SPI transfer length
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-- SPI transfer length
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signal transfer_length : std_logic_vector(1 downto 0);
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signal transfer_length : std_logic_vector(1 downto 0);
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-- Flag to indicate that the SPI slave should be deselected after the current
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-- Flag to indicate that the SPI slave should be deselected after the current
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-- transfer
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-- transfer
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signal deselect : std_logic;
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signal deselect : std_logic;
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-- Flag to indicate that an IRQ should be generated at the end of a transfer
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-- Flag to indicate that an IRQ should be generated at the end of a transfer
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signal irq_enable : std_logic;
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signal irq_enable : std_logic;
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-- Internal chip select signal, will be demultiplexed through the cs_mux
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-- Internal chip select signal, will be demultiplexed through the cs_mux
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signal spi_cs : std_logic;
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signal spi_cs : std_logic;
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-- Current SPI device address
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-- Current SPI device address
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signal spi_addr : std_logic_vector(2 downto 0);
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signal spi_addr : std_logic_vector(2 downto 0);
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begin
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begin
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-- Read CPU bus into internal registers
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-- Read CPU bus into internal registers
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cpu_write : process(clk, reset)
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cpu_write : process(clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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deselect <= '0';
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deselect <= '0';
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irq_enable <= '0';
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irq_enable <= '0';
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start <= '0';
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start <= '0';
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spi_clk_divide <= "11";
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spi_clk_divide <= "11";
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transfer_length <= "11";
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transfer_length <= "11";
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spi_data_buf <= (others => '0');
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spi_data_buf <= (others => '0');
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elsif falling_edge(clk) then
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elsif falling_edge(clk) then
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start <= '0';
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start <= '0';
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if cs = '1' and rw = '0' then
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if cs = '1' and rw = '0' then
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case addr is
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case addr is
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when "00" =>
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when "00" =>
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spi_data_buf(7 downto 0) <= data_in;
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spi_data_buf(7 downto 0) <= data_in;
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when "01" =>
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when "01" =>
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spi_data_buf(15 downto 8) <= data_in;
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spi_data_buf(15 downto 8) <= data_in;
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when "10" =>
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when "10" =>
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start <= data_in(0);
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start <= data_in(0);
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deselect <= data_in(1);
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deselect <= data_in(1);
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irq_enable <= data_in(2);
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irq_enable <= data_in(2);
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spi_addr <= data_in(6 downto 4);
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spi_addr <= data_in(6 downto 4);
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when "11" =>
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when "11" =>
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spi_clk_divide <= data_in(1 downto 0);
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spi_clk_divide <= data_in(1 downto 0);
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transfer_length <= data_in(3 downto 2);
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transfer_length <= data_in(3 downto 2);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Provide data for the CPU to read
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-- Provide data for the CPU to read
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cpu_read : process(shift_reg, addr, state, deselect, start)
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cpu_read : process(shift_reg, addr, state, deselect, start)
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begin
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begin
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data_out <= (others => '0');
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data_out <= (others => '0');
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case addr is
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case addr is
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when "00" =>
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when "00" =>
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data_out <= shift_reg(7 downto 0);
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data_out <= shift_reg(7 downto 0);
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when "01" =>
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when "01" =>
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data_out <= shift_reg(15 downto 8);
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data_out <= shift_reg(15 downto 8);
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when "10" =>
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when "10" =>
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if state = s_idle then
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if state = s_idle then
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data_out(0) <= '0';
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data_out(0) <= '0';
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else
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else
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data_out(0) <= '1';
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data_out(0) <= '1';
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end if;
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end if;
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data_out(1) <= deselect;
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data_out(1) <= deselect;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end process;
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end process;
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spi_cs_n <= "11111110" when spi_addr = "000" and spi_cs = '1' else
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spi_cs_n <= "11111110" when spi_addr = "000" and spi_cs = '1' else
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"11111101" when spi_addr = "001" and spi_cs = '1' else
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"11111101" when spi_addr = "001" and spi_cs = '1' else
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"11111011" when spi_addr = "010" and spi_cs = '1' else
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"11111011" when spi_addr = "010" and spi_cs = '1' else
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"11110111" when spi_addr = "011" and spi_cs = '1' else
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"11110111" when spi_addr = "011" and spi_cs = '1' else
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"11101111" when spi_addr = "100" and spi_cs = '1' else
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"11101111" when spi_addr = "100" and spi_cs = '1' else
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"11011111" when spi_addr = "101" and spi_cs = '1' else
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"11011111" when spi_addr = "101" and spi_cs = '1' else
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"10111111" when spi_addr = "110" and spi_cs = '1' else
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"10111111" when spi_addr = "110" and spi_cs = '1' else
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"01111111" when spi_addr = "111" and spi_cs = '1' else
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"01111111" when spi_addr = "111" and spi_cs = '1' else
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"11111111";
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"11111111";
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-- SPI transfer state machine
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-- SPI transfer state machine
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spi_proc : process(clk, reset)
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spi_proc : process(clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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count <= (others => '0');
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count <= (others => '0');
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shift_reg <= (others => '0');
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shift_reg <= (others => '0');
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prev_spi_clk <= '0';
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prev_spi_clk <= '0';
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spi_clk_out <= '0';
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spi_clk_out <= '0';
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spi_cs <= '0';
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spi_cs <= '0';
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state <= s_idle;
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state <= s_idle;
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irq <= 'Z';
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irq <= 'Z';
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elsif falling_edge(clk) then
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elsif falling_edge(clk) then
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prev_spi_clk <= spi_clk_buf;
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prev_spi_clk <= spi_clk_buf;
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irq <= 'Z';
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irq <= 'Z';
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case state is
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case state is
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when s_idle =>
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when s_idle =>
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if start = '1' then
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if start = '1' then
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count <= (others => '0');
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count <= (others => '0');
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shift_reg <= spi_data_buf;
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shift_reg <= spi_data_buf;
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spi_cs <= '1';
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spi_cs <= '1';
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state <= s_running;
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state <= s_running;
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elsif deselect = '1' then
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elsif deselect = '1' then
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spi_cs <= '0';
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spi_cs <= '0';
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end if;
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end if;
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when s_running =>
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when s_running =>
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if prev_spi_clk = '1' and spi_clk_buf = '0' then
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if prev_spi_clk = '1' and spi_clk_buf = '0' then
|
spi_clk_out <= '0';
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spi_clk_out <= '0';
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count <= count + "0001";
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count <= count + "0001";
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shift_reg <= shift_reg(14 downto 0) & spi_miso;
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shift_reg <= shift_reg(14 downto 0) & spi_miso;
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if ((count = "0011" and transfer_length = "00")
|
if ((count = "0011" and transfer_length = "00")
|
or (count = "0111" and transfer_length = "01")
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or (count = "0111" and transfer_length = "01")
|
or (count = "1011" and transfer_length = "10")
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or (count = "1011" and transfer_length = "10")
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or (count = "1111" and transfer_length = "11")) then
|
or (count = "1111" and transfer_length = "11")) then
|
if deselect = '1' then
|
if deselect = '1' then
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spi_cs <= '0';
|
spi_cs <= '0';
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end if;
|
end if;
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if irq_enable = '1' then
|
if irq_enable = '1' then
|
irq <= '1';
|
irq <= '1';
|
end if;
|
end if;
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state <= s_idle;
|
state <= s_idle;
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end if;
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end if;
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elsif prev_spi_clk = '0' and spi_clk_buf = '1' then
|
elsif prev_spi_clk = '0' and spi_clk_buf = '1' then
|
spi_clk_out <= '1';
|
spi_clk_out <= '1';
|
end if;
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end if;
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when others =>
|
when others =>
|
null;
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null;
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end case;
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end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Generate SPI clock
|
-- Generate SPI clock
|
spi_clock_gen : process(clk, reset)
|
spi_clock_gen : process(clk, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
spi_clk_count <= (others => '0');
|
spi_clk_count <= (others => '0');
|
spi_clk_buf <= '0';
|
spi_clk_buf <= '0';
|
elsif falling_edge(clk) then
|
elsif falling_edge(clk) then
|
if state = s_running then
|
if state = s_running then
|
if ((spi_clk_divide = "00")
|
if ((spi_clk_divide = "00")
|
or (spi_clk_divide = "01" and spi_clk_count = "001")
|
or (spi_clk_divide = "01" and spi_clk_count = "001")
|
or (spi_clk_divide = "10" and spi_clk_count = "011")
|
or (spi_clk_divide = "10" and spi_clk_count = "011")
|
or (spi_clk_divide = "11" and spi_clk_count = "111")) then
|
or (spi_clk_divide = "11" and spi_clk_count = "111")) then
|
spi_clk_buf <= not spi_clk_buf;
|
spi_clk_buf <= not spi_clk_buf;
|
spi_clk_count <= (others => '0');
|
spi_clk_count <= (others => '0');
|
else
|
else
|
spi_clk_count <= spi_clk_count + "001";
|
spi_clk_count <= spi_clk_count + "001";
|
end if;
|
end if;
|
else
|
else
|
spi_clk_buf <= '0';
|
spi_clk_buf <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
spi_mosi_mux : process(shift_reg, transfer_length)
|
spi_mosi_mux : process(shift_reg, transfer_length)
|
begin
|
begin
|
case transfer_length is
|
case transfer_length is
|
when "00" =>
|
when "00" =>
|
spi_mosi <= shift_reg(3);
|
spi_mosi <= shift_reg(3);
|
when "01" =>
|
when "01" =>
|
spi_mosi <= shift_reg(7);
|
spi_mosi <= shift_reg(7);
|
when "10" =>
|
when "10" =>
|
spi_mosi <= shift_reg(11);
|
spi_mosi <= shift_reg(11);
|
when "11" =>
|
when "11" =>
|
spi_mosi <= shift_reg(15);
|
spi_mosi <= shift_reg(15);
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
spi_clk <= spi_clk_out;
|
spi_clk <= spi_clk_out;
|
|
|
end rtl;
|
end rtl;
|
|
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