--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
--
|
--
|
-- www.OpenCores.Org - September 2003
|
-- www.OpenCores.Org - September 2003
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- File name : System09.vhd
|
-- File name : System09.vhd
|
--
|
--
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
|
-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
|
-- Implemented With BurchED B5-X300 FPGA board,
|
-- Implemented With BurchED B5-X300 FPGA board,
|
-- B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module
|
-- B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Dependencies : ieee.Std_Logic_1164
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
--
|
--
|
-- Uses : boot_rom (sbug.vhd) Monitor ROM
|
-- Uses : boot_rom (sbug.vhd) Monitor ROM
|
-- cpu09 (cpu09.vhd) CPU core
|
-- cpu09 (cpu09.vhd) CPU core
|
-- dat_ram (datram.vhd) Dynamic Address Translation
|
-- dat_ram (datram.vhd) Dynamic Address Translation
|
-- miniuart (minitUART2.vhd) ACIA / MiniUART
|
-- miniuart (minitUART2.vhd) ACIA / MiniUART
|
-- (rxunit2.vhd)
|
-- (rxunit2.vhd)
|
-- (tx_unit2.vhd)
|
-- (tx_unit2.vhd)
|
-- (clkunit2.vhd)
|
-- (clkunit2.vhd)
|
-- timer (timer.vhd) Timer module
|
-- timer (timer.vhd) Timer module
|
--
|
--
|
-- Author : John E. Kent
|
-- Author : John E. Kent
|
-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
--
|
--
|
--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
--===========================================================================--
|
--===========================================================================--
|
-- Version 0.1 - 20 March 2003
|
-- Version 0.1 - 20 March 2003
|
-- Version 0.2 - 30 March 2003
|
-- Version 0.2 - 30 March 2003
|
-- Version 0.3 - 29 April 2003
|
-- Version 0.3 - 29 April 2003
|
-- Version 0.4 - 29 June 2003
|
-- Version 0.4 - 29 June 2003
|
-- Version 0.5 - 19 July 2003
|
-- Version 0.5 - 19 July 2003
|
-- prints out "Hello World"
|
-- prints out "Hello World"
|
-- Version 0.6 - 5 September 2003
|
-- Version 0.6 - 5 September 2003
|
-- Runs SBUG
|
-- Runs SBUG
|
-- Version 1.0- 6 Sep 2003 - John Kent
|
-- Version 1.0- 6 Sep 2003 - John Kent
|
-- Inverted SysClk
|
-- Inverted SysClk
|
-- Initial release to Open Cores
|
-- Initial release to Open Cores
|
--
|
--
|
--===========================================================================--
|
--===========================================================================--
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
entity System09 is
|
entity System09 is
|
port(
|
port(
|
SysClk : in Std_Logic; -- System Clock input
|
SysClk : in Std_Logic; -- System Clock input
|
Reset_n : in Std_logic; -- Master Reset input (active low)
|
Reset_n : in Std_logic; -- Master Reset input (active low)
|
LED : out std_logic; -- Diagnostic LED Flasher
|
LED : out std_logic; -- Diagnostic LED Flasher
|
|
|
-- Memory Interface signals
|
-- Memory Interface signals
|
ram_csn : out Std_Logic;
|
ram_csn : out Std_Logic;
|
ram_wrln : out Std_Logic;
|
ram_wrln : out Std_Logic;
|
ram_wrun : out Std_Logic;
|
ram_wrun : out Std_Logic;
|
ram_addr : out Std_Logic_Vector(16 downto 0);
|
ram_addr : out Std_Logic_Vector(16 downto 0);
|
ram_data : inout Std_Logic_Vector(15 downto 0);
|
ram_data : inout Std_Logic_Vector(15 downto 0);
|
|
|
-- Stuff on the peripheral board
|
-- Stuff on the peripheral board
|
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
|
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
|
|
|
-- PS/2 Mouse interface
|
-- PS/2 Mouse interface
|
-- mouse_clock : in Std_Logic;
|
-- mouse_clock : in Std_Logic;
|
-- mouse_data : in Std_Logic;
|
-- mouse_data : in Std_Logic;
|
|
|
-- Uart Interface
|
-- Uart Interface
|
rxbit : in Std_Logic;
|
rxbit : in Std_Logic;
|
txbit : out Std_Logic;
|
txbit : out Std_Logic;
|
rts_n : out Std_Logic;
|
rts_n : out Std_Logic;
|
cts_n : in Std_Logic;
|
cts_n : in Std_Logic;
|
|
|
-- CRTC output signals
|
-- CRTC output signals
|
-- v_drive : out Std_Logic;
|
-- v_drive : out Std_Logic;
|
-- h_drive : out Std_Logic;
|
-- h_drive : out Std_Logic;
|
-- blue_lo : out std_logic;
|
-- blue_lo : out std_logic;
|
-- blue_hi : out std_logic;
|
-- blue_hi : out std_logic;
|
-- green_lo : out std_logic;
|
-- green_lo : out std_logic;
|
-- green_hi : out std_logic;
|
-- green_hi : out std_logic;
|
-- red_lo : out std_logic;
|
-- red_lo : out std_logic;
|
-- red_hi : out std_logic;
|
-- red_hi : out std_logic;
|
-- buzzer : out std_logic;
|
-- buzzer : out std_logic;
|
|
|
-- Compact Flash
|
-- Compact Flash
|
cf_rst_n : out std_logic;
|
cf_rst_n : out std_logic;
|
cf_cs0_n : out std_logic;
|
cf_cs0_n : out std_logic;
|
cf_cs1_n : out std_logic;
|
cf_cs1_n : out std_logic;
|
cf_rd_n : out std_logic;
|
cf_rd_n : out std_logic;
|
cf_wr_n : out std_logic;
|
cf_wr_n : out std_logic;
|
cf_cs16_n : out std_logic;
|
cf_cs16_n : out std_logic;
|
cf_a : out std_logic_vector(2 downto 0);
|
cf_a : out std_logic_vector(2 downto 0);
|
cf_d : inout std_logic_vector(15 downto 0);
|
cf_d : inout std_logic_vector(15 downto 0);
|
|
|
-- Parallel I/O port
|
-- Parallel I/O port
|
-- porta : inout std_logic_vector(7 downto 0);
|
-- porta : inout std_logic_vector(7 downto 0);
|
-- portb : inout std_logic_vector(7 downto 0);
|
-- portb : inout std_logic_vector(7 downto 0);
|
-- timer_out : out std_logic;
|
-- timer_out : out std_logic;
|
|
|
-- Test Pins
|
-- Test Pins
|
test_alu : out std_logic_vector(15 downto 0);
|
test_alu : out std_logic_vector(15 downto 0);
|
test_cc : out std_logic_vector(7 downto 0)
|
test_cc : out std_logic_vector(7 downto 0)
|
);
|
);
|
end System09;
|
end System09;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for memio Controller Unit
|
-- Architecture for memio Controller Unit
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture my_computer of System09 is
|
architecture my_computer of System09 is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- BOOT ROM
|
-- BOOT ROM
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- UART Interface signals
|
-- UART Interface signals
|
signal uart_data_out : Std_Logic_Vector(7 downto 0);
|
signal uart_data_out : Std_Logic_Vector(7 downto 0);
|
signal uart_cs : Std_Logic;
|
signal uart_cs : Std_Logic;
|
signal uart_irq : Std_Logic;
|
signal uart_irq : Std_Logic;
|
|
|
-- timer
|
-- timer
|
-- signal timer_data_out : std_logic_vector(7 downto 0);
|
-- signal timer_data_out : std_logic_vector(7 downto 0);
|
-- signal timer_cs : std_logic;
|
-- signal timer_cs : std_logic;
|
-- signal timer_irq : std_logic;
|
-- signal timer_irq : std_logic;
|
|
|
-- Parallel I/O port
|
-- Parallel I/O port
|
-- signal ioport_data_out : std_logic_vector(7 downto 0);
|
-- signal ioport_data_out : std_logic_vector(7 downto 0);
|
-- signal ioport_cs : std_logic;
|
-- signal ioport_cs : std_logic;
|
|
|
-- compact flash port
|
-- compact flash port
|
signal cf_data_out : std_logic_vector(7 downto 0);
|
signal cf_data_out : std_logic_vector(7 downto 0);
|
signal cf_cs : std_logic;
|
signal cf_cs : std_logic;
|
signal cf_rd : std_logic;
|
signal cf_rd : std_logic;
|
signal cf_wr : std_logic;
|
signal cf_wr : std_logic;
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_wrl : std_logic; -- memory write lower
|
signal ram_wrl : std_logic; -- memory write lower
|
signal ram_wru : std_logic; -- memory write upper
|
signal ram_wru : std_logic; -- memory write upper
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_reset : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_out: std_logic_vector(7 downto 0);
|
signal cpu_data_out: std_logic_vector(7 downto 0);
|
|
|
-- Dynamic address translation
|
-- Dynamic address translation
|
signal dat_cs : std_logic;
|
signal dat_cs : std_logic;
|
signal dat_addr : std_logic_vector(7 downto 0);
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
-- Boot ROM Map switch
|
-- Boot ROM Map switch
|
-- signal map_cs : Std_Logic;
|
-- signal map_cs : Std_Logic;
|
-- signal map_sw : Std_Logic;
|
-- signal map_sw : Std_Logic;
|
|
|
-- synchronous RAM
|
-- synchronous RAM
|
-- signal xram_data_out : std_logic_vector(7 downto 0);
|
-- signal xram_data_out : std_logic_vector(7 downto 0);
|
-- signal xram_cs : std_logic;
|
-- signal xram_cs : std_logic;
|
|
|
-- Flashing Led test signals
|
-- Flashing Led test signals
|
signal countL : std_logic_vector(23 downto 0);
|
signal countL : std_logic_vector(23 downto 0);
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
rw: out std_logic; -- Asynchronous memory interface
|
rw: out std_logic; -- Asynchronous memory interface
|
vma: out std_logic;
|
vma: out std_logic;
|
address: out std_logic_vector(15 downto 0);
|
address: out std_logic_vector(15 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
halt: in std_logic;
|
halt: in std_logic;
|
hold: in std_logic;
|
hold: in std_logic;
|
irq: in std_logic;
|
irq: in std_logic;
|
nmi: in std_logic;
|
nmi: in std_logic;
|
firq: in std_logic;
|
firq: in std_logic;
|
test_alu: out std_logic_vector(15 downto 0);
|
test_alu: out std_logic_vector(15 downto 0);
|
test_cc: out std_logic_vector(7 downto 0)
|
test_cc: out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- Open Cores Mini UART
|
-- Open Cores Mini UART
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component miniUART
|
component miniUART
|
port (
|
port (
|
SysClk : in Std_Logic; -- System Clock
|
SysClk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input
|
rst : in Std_Logic; -- Reset input
|
cs : in Std_Logic;
|
cs : in Std_Logic;
|
rw : in Std_Logic;
|
rw : in Std_Logic;
|
RxD : in Std_Logic;
|
RxD : in Std_Logic;
|
TxD : out Std_Logic;
|
TxD : out Std_Logic;
|
CTS_n : in Std_Logic;
|
CTS_n : in Std_Logic;
|
RTS_n : out Std_Logic;
|
RTS_n : out Std_Logic;
|
Irq : out Std_logic;
|
Irq : out Std_logic;
|
Addr : in Std_Logic;
|
Addr : in Std_Logic;
|
DataIn : in Std_Logic_Vector(7 downto 0); --
|
DataIn : in Std_Logic_Vector(7 downto 0); --
|
DataOut : out Std_Logic_Vector(7 downto 0)); --
|
DataOut : out Std_Logic_Vector(7 downto 0)); --
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer module
|
-- Timer module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
--component timer
|
--component timer
|
-- port (
|
-- port (
|
-- clk : in std_logic;
|
-- clk : in std_logic;
|
-- rst : in std_logic;
|
-- rst : in std_logic;
|
-- cs : in std_logic;
|
-- cs : in std_logic;
|
-- rw : in std_logic;
|
-- rw : in std_logic;
|
-- addr : in std_logic;
|
-- addr : in std_logic;
|
-- data_in : in std_logic_vector(7 downto 0);
|
-- data_in : in std_logic_vector(7 downto 0);
|
-- data_out : out std_logic_vector(7 downto 0);
|
-- data_out : out std_logic_vector(7 downto 0);
|
-- irq : out std_logic;
|
-- irq : out std_logic;
|
-- timer_in : in std_logic;
|
-- timer_in : in std_logic;
|
-- timer_out : out std_logic
|
-- timer_out : out std_logic
|
-- );
|
-- );
|
--end component;
|
--end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Dual 8 bit Parallel I/O module
|
-- Dual 8 bit Parallel I/O module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
--component ioport
|
--component ioport
|
-- port (
|
-- port (
|
-- clk : in std_logic;
|
-- clk : in std_logic;
|
-- rst : in std_logic;
|
-- rst : in std_logic;
|
-- cs : in std_logic;
|
-- cs : in std_logic;
|
-- rw : in std_logic;
|
-- rw : in std_logic;
|
-- addr : in std_logic_vector(1 downto 0);
|
-- addr : in std_logic_vector(1 downto 0);
|
-- data_in : in std_logic_vector(7 downto 0);
|
-- data_in : in std_logic_vector(7 downto 0);
|
-- data_out : out std_logic_vector(7 downto 0);
|
-- data_out : out std_logic_vector(7 downto 0);
|
-- porta_io : inout std_logic_vector(7 downto 0);
|
-- porta_io : inout std_logic_vector(7 downto 0);
|
-- portb_io : inout std_logic_vector(7 downto 0)
|
-- portb_io : inout std_logic_vector(7 downto 0)
|
-- );
|
-- );
|
--end component;
|
--end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- SBUG Slice Monitor ROM
|
-- SBUG Slice Monitor ROM
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component boot_rom
|
component boot_rom
|
port (
|
port (
|
addr : in Std_Logic_Vector(10 downto 0); -- 2K byte boot rom
|
addr : in Std_Logic_Vector(10 downto 0); -- 2K byte boot rom
|
data : out Std_Logic_Vector(7 downto 0));
|
data : out Std_Logic_Vector(7 downto 0));
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- SBUG Block RAM Monitor ROM
|
-- SBUG Block RAM Monitor ROM
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
--component sbug_rom
|
--component sbug_rom
|
-- Port (
|
-- Port (
|
-- MEMclk : in std_logic;
|
-- MEMclk : in std_logic;
|
-- MEMaddr : in std_logic_vector (10 downto 0);
|
-- MEMaddr : in std_logic_vector (10 downto 0);
|
-- MEMrdata : out std_logic_vector (7 downto 0)
|
-- MEMrdata : out std_logic_vector (7 downto 0)
|
-- );
|
-- );
|
--end component;
|
--end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Dynamic Address Translation Registers
|
-- Dynamic Address Translation Registers
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component dat_ram
|
component dat_ram
|
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
cs: in std_logic;
|
cs: in std_logic;
|
rw: in std_logic;
|
rw: in std_logic;
|
addr_lo: in std_logic_vector(3 downto 0);
|
addr_lo: in std_logic_vector(3 downto 0);
|
addr_hi: in std_logic_vector(3 downto 0);
|
addr_hi: in std_logic_vector(3 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0)
|
data_out: out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Block RAM module
|
-- Block RAM module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
-- component block_ram
|
-- component block_ram
|
-- Port (
|
-- Port (
|
-- MEMclk : in std_logic;
|
-- MEMclk : in std_logic;
|
-- MEMcs : in std_logic;
|
-- MEMcs : in std_logic;
|
-- MEMrw : in std_logic;
|
-- MEMrw : in std_logic;
|
-- MEMaddr : in std_logic_vector (10 downto 0);
|
-- MEMaddr : in std_logic_vector (10 downto 0);
|
-- MEMrdata : out std_logic_vector (7 downto 0);
|
-- MEMrdata : out std_logic_vector (7 downto 0);
|
-- MEMwdata : in std_logic_vector (7 downto 0)
|
-- MEMwdata : in std_logic_vector (7 downto 0)
|
-- );
|
-- );
|
--end component;
|
--end component;
|
|
|
|
|
-- component BUFG
|
-- component BUFG
|
-- port (
|
-- port (
|
-- i: in std_logic;
|
-- i: in std_logic;
|
-- o: out std_logic
|
-- o: out std_logic
|
-- );
|
-- );
|
-- end component;
|
-- end component;
|
|
|
begin
|
begin
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09 port map (
|
clk => SysClk,
|
clk => SysClk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
address => cpu_addr(15 downto 0),
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
halt => cpu_halt,
|
halt => cpu_halt,
|
hold => cpu_hold,
|
hold => cpu_hold,
|
irq => cpu_irq,
|
irq => cpu_irq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
firq => cpu_firq,
|
firq => cpu_firq,
|
test_alu => test_alu,
|
test_alu => test_alu,
|
test_cc => test_cc
|
test_cc => test_cc
|
);
|
);
|
|
|
|
|
my_uart : miniUART port map (
|
my_uart : miniUART port map (
|
SysClk => SysClk,
|
SysClk => SysClk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => uart_cs,
|
cs => uart_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
RxD => rxbit,
|
RxD => rxbit,
|
TxD => txbit,
|
TxD => txbit,
|
CTS_n => cts_n,
|
CTS_n => cts_n,
|
RTS_n => rts_n,
|
RTS_n => rts_n,
|
Irq => uart_irq,
|
Irq => uart_irq,
|
Addr => cpu_addr(0),
|
Addr => cpu_addr(0),
|
Datain => cpu_data_out,
|
Datain => cpu_data_out,
|
DataOut => uart_data_out
|
DataOut => uart_data_out
|
);
|
);
|
|
|
--my_timer : timer port map (
|
--my_timer : timer port map (
|
-- clk => SysClk,
|
-- clk => SysClk,
|
-- rst => cpu_reset,
|
-- rst => cpu_reset,
|
-- cs => timer_cs,
|
-- cs => timer_cs,
|
-- rw => cpu_rw,
|
-- rw => cpu_rw,
|
-- addr => cpu_addr(0),
|
-- addr => cpu_addr(0),
|
-- data_in => cpu_data_out,
|
-- data_in => cpu_data_out,
|
-- data_out => timer_data_out,
|
-- data_out => timer_data_out,
|
-- irq => timer_irq,
|
-- irq => timer_irq,
|
-- timer_in => CountL(5),
|
-- timer_in => CountL(5),
|
-- timer_out => timer_out
|
-- timer_out => timer_out
|
-- );
|
-- );
|
|
|
--my_ioport : ioport port map (
|
--my_ioport : ioport port map (
|
-- clk => SysClk,
|
-- clk => SysClk,
|
-- rst => cpu_reset,
|
-- rst => cpu_reset,
|
-- cs => ioport_cs,
|
-- cs => ioport_cs,
|
-- rw => cpu_rw,
|
-- rw => cpu_rw,
|
-- addr => cpu_addr(1 downto 0),
|
-- addr => cpu_addr(1 downto 0),
|
-- data_in => cpu_data_out,
|
-- data_in => cpu_data_out,
|
-- data_out => ioport_data_out,
|
-- data_out => ioport_data_out,
|
-- porta_io => porta,
|
-- porta_io => porta,
|
-- portb_io => portb
|
-- portb_io => portb
|
-- );
|
-- );
|
|
|
my_rom : boot_rom port map (
|
my_rom : boot_rom port map (
|
addr => cpu_addr(10 downto 0),
|
addr => cpu_addr(10 downto 0),
|
data => rom_data_out
|
data => rom_data_out
|
);
|
);
|
|
|
--my_rom : sbug_rom port map (
|
--my_rom : sbug_rom port map (
|
-- MEMclk => SysClk,
|
-- MEMclk => SysClk,
|
-- MEMaddr => cpu_addr(10 downto 0),
|
-- MEMaddr => cpu_addr(10 downto 0),
|
-- MEMrdata => rom_data_out
|
-- MEMrdata => rom_data_out
|
-- );
|
-- );
|
|
|
my_dat : dat_ram port map (
|
my_dat : dat_ram port map (
|
clk => SysClk,
|
clk => SysClk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => dat_cs,
|
cs => dat_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr_hi => cpu_addr(15 downto 12),
|
addr_hi => cpu_addr(15 downto 12),
|
addr_lo => cpu_addr(3 downto 0),
|
addr_lo => cpu_addr(3 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => dat_addr(7 downto 0)
|
data_out => dat_addr(7 downto 0)
|
);
|
);
|
|
|
--my_ram : block_ram port map (
|
--my_ram : block_ram port map (
|
-- MEMclk => SysClk,
|
-- MEMclk => SysClk,
|
-- MEMcs => xram_cs,
|
-- MEMcs => xram_cs,
|
-- MEMrw => cpu_rw,
|
-- MEMrw => cpu_rw,
|
-- MEMaddr => cpu_addr(10 downto 0),
|
-- MEMaddr => cpu_addr(10 downto 0),
|
-- MEMwdata => cpu_data_out,
|
-- MEMwdata => cpu_data_out,
|
-- MEMrdata => xram_data_out
|
-- MEMrdata => xram_data_out
|
-- );
|
-- );
|
|
|
-- clk_buffer : BUFG port map(
|
-- clk_buffer : BUFG port map(
|
-- i => e_clk,
|
-- i => e_clk,
|
-- o => cpu_clk
|
-- o => cpu_clk
|
-- );
|
-- );
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( SysClk, Reset_n,
|
mem_decode: process( SysClk, Reset_n,
|
cpu_addr, cpu_rw, cpu_vma,
|
cpu_addr, cpu_rw, cpu_vma,
|
dat_cs, dat_addr,
|
dat_cs, dat_addr,
|
-- map_cs, map_sw,
|
-- map_cs, map_sw,
|
rom_data_out, ram_data_out,
|
rom_data_out, ram_data_out,
|
-- xram_data_out,
|
-- xram_data_out,
|
cf_data_out,
|
cf_data_out,
|
-- timer_data_out, ioport_data_out,
|
-- timer_data_out, ioport_data_out,
|
uart_data_out )
|
uart_data_out )
|
begin
|
begin
|
case cpu_addr(15 downto 11) is
|
case cpu_addr(15 downto 11) is
|
--
|
--
|
-- SBUG Monitor ROM $F800 - $FFFF
|
-- SBUG Monitor ROM $F800 - $FFFF
|
--
|
--
|
when "11111" => -- $F800 - $FFFF
|
when "11111" => -- $F800 - $FFFF
|
cpu_data_in <= rom_data_out; -- read ROM
|
cpu_data_in <= rom_data_out; -- read ROM
|
dat_cs <= cpu_vma; -- write DAT
|
dat_cs <= cpu_vma; -- write DAT
|
ram_cs <= '0';
|
ram_cs <= '0';
|
uart_cs <= '0';
|
uart_cs <= '0';
|
cf_cs <= '0';
|
cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- xram_cs <= '0';
|
-- xram_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
|
|
--
|
--
|
-- Shadow RAM Monitor switch
|
-- Shadow RAM Monitor switch
|
--
|
--
|
-- when "11101" => -- $E800 - $EFFF
|
-- when "11101" => -- $E800 - $EFFF
|
-- when "11111" => -- $F800 - $FFFF
|
-- when "11111" => -- $F800 - $FFFF
|
-- if map_sw = '1' then
|
-- if map_sw = '1' then
|
-- cpu_data_in <= rom_data_out; -- read ROM
|
-- cpu_data_in <= rom_data_out; -- read ROM
|
-- dat_cs <= '0'; -- disable write to DAT
|
-- dat_cs <= '0'; -- disable write to DAT
|
-- ram_cs <= cpu_vma; -- enable write to RAM
|
-- ram_cs <= cpu_vma; -- enable write to RAM
|
-- else
|
-- else
|
-- cpu_data_in <= ram_data_out; -- read RAM
|
-- cpu_data_in <= ram_data_out; -- read RAM
|
-- dat_cs <= cpu_vma; -- enable write DAT
|
-- dat_cs <= cpu_vma; -- enable write DAT
|
-- ram_cs <= cpu_vma and cpu_rw; -- disable write to RAM
|
-- ram_cs <= cpu_vma and cpu_rw; -- disable write to RAM
|
-- end if;
|
-- end if;
|
-- uart_cs <= '0';
|
-- uart_cs <= '0';
|
-- cf_cs <= '0';
|
-- cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- xram_cs <= cpu_vma;
|
-- xram_cs <= cpu_vma;
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
|
|
--
|
--
|
-- Synchronous Block RAM $F000 - $F7FF
|
-- Synchronous Block RAM $F000 - $F7FF
|
--
|
--
|
-- when "11110" => -- $F000 - $F7FF
|
-- when "11110" => -- $F000 - $F7FF
|
-- cpu_data_in <= xram_data_out;
|
-- cpu_data_in <= xram_data_out;
|
-- dat_cs <= '0';
|
-- dat_cs <= '0';
|
-- ram_cs <= '0';
|
-- ram_cs <= '0';
|
-- uart_cs <= '0';
|
-- uart_cs <= '0';
|
-- cf_cs <= '0';
|
-- cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- xram_cs <= cpu_vma;
|
-- xram_cs <= cpu_vma;
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
|
|
--
|
--
|
-- IO Devices $E000 - $E7FF
|
-- IO Devices $E000 - $E7FF
|
--
|
--
|
when "11100" => -- $E000 - $E7FF
|
when "11100" => -- $E000 - $E7FF
|
dat_cs <= '0';
|
dat_cs <= '0';
|
ram_cs <= '0';
|
ram_cs <= '0';
|
-- xram_cs <= '0';
|
-- xram_cs <= '0';
|
case cpu_addr(7 downto 4) is
|
case cpu_addr(7 downto 4) is
|
--
|
--
|
-- UART / ACIA $E000
|
-- UART / ACIA $E000
|
--
|
--
|
when "0000" => -- $E000
|
when "0000" => -- $E000
|
cpu_data_in <= uart_data_out;
|
cpu_data_in <= uart_data_out;
|
uart_cs <= cpu_vma;
|
uart_cs <= cpu_vma;
|
cf_cs <= '0';
|
cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
--
|
--
|
-- Compact Flash $E010 - $E01F
|
-- Compact Flash $E010 - $E01F
|
--
|
--
|
when "0001" => -- $E010
|
when "0001" => -- $E010
|
cpu_data_in <= cf_data_out;
|
cpu_data_in <= cf_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
cf_cs <= cpu_vma;
|
cf_cs <= cpu_vma;
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
--
|
--
|
-- Timer $E020 - $E02F
|
-- Timer $E020 - $E02F
|
--
|
--
|
-- when "0010" => -- $E020
|
-- when "0010" => -- $E020
|
-- cpu_data_in <= timer_data_out;
|
-- cpu_data_in <= timer_data_out;
|
-- uart_cs <= '0';
|
-- uart_cs <= '0';
|
-- cf_cs <= '0';
|
-- cf_cs <= '0';
|
-- timer_cs <= cpu_vma;
|
-- timer_cs <= cpu_vma;
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
|
|
--
|
--
|
-- ROM Map switch $E030
|
-- ROM Map switch $E030
|
--
|
--
|
-- when "0011" => -- $E030
|
-- when "0011" => -- $E030
|
-- cpu_data_in <= "00000000";
|
-- cpu_data_in <= "00000000";
|
-- uart_cs <= '0';
|
-- uart_cs <= '0';
|
-- cf_cs <= '0';
|
-- cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- map_cs <= cpu_vma;
|
-- map_cs <= cpu_vma;
|
|
|
--
|
--
|
-- I/O port $E040 - $E04F
|
-- I/O port $E040 - $E04F
|
--
|
--
|
-- when "0100" => -- $E040
|
-- when "0100" => -- $E040
|
-- cpu_data_in <= ioport_data_out;
|
-- cpu_data_in <= ioport_data_out;
|
-- uart_cs <= '0';
|
-- uart_cs <= '0';
|
-- cf_cs <= '0';
|
-- cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= cpu_vma;
|
-- ioport_cs <= cpu_vma;
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
|
|
when others => -- $E040 to $E7FF
|
when others => -- $E040 to $E7FF
|
cpu_data_in <= "00000000";
|
cpu_data_in <= "00000000";
|
uart_cs <= '0';
|
uart_cs <= '0';
|
cf_cs <= '0';
|
cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
end case;
|
end case;
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
when others =>
|
when others =>
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
dat_cs <= '0';
|
dat_cs <= '0';
|
uart_cs <= '0';
|
uart_cs <= '0';
|
cf_cs <= '0';
|
cf_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- ioport_cs <= '0';
|
-- ioport_cs <= '0';
|
-- xram_cs <= '0';
|
-- xram_cs <= '0';
|
-- map_cs <= '0';
|
-- map_cs <= '0';
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- B3-SRAM Control
|
-- B3-SRAM Control
|
-- Processes to read and write memory based on bus signals
|
-- Processes to read and write memory based on bus signals
|
--
|
--
|
ram_process: process( SysClk, Reset_n,
|
ram_process: process( SysClk, Reset_n,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
dat_addr,
|
dat_addr,
|
ram_cs, ram_wrl, ram_wru, ram_data_out )
|
ram_cs, ram_wrl, ram_wru, ram_data_out )
|
begin
|
begin
|
ram_csn <= not( ram_cs and Reset_n );
|
ram_csn <= not( ram_cs and Reset_n );
|
ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
|
ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
|
ram_wrln <= not (ram_wrl);
|
ram_wrln <= not (ram_wrl);
|
ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;
|
ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;
|
ram_wrun <= not (ram_wru);
|
ram_wrun <= not (ram_wru);
|
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
|
ram_addr(16 downto 12) <= dat_addr(4 downto 0);
|
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
|
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
|
|
|
if ram_wrl = '1' then
|
if ram_wrl = '1' then
|
ram_data(7 downto 0) <= cpu_data_out;
|
ram_data(7 downto 0) <= cpu_data_out;
|
else
|
else
|
ram_data(7 downto 0) <= "ZZZZZZZZ";
|
ram_data(7 downto 0) <= "ZZZZZZZZ";
|
end if;
|
end if;
|
|
|
if ram_wru = '1' then
|
if ram_wru = '1' then
|
ram_data(15 downto 8) <= cpu_data_out;
|
ram_data(15 downto 8) <= cpu_data_out;
|
else
|
else
|
ram_data(15 downto 8) <= "ZZZZZZZZ";
|
ram_data(15 downto 8) <= "ZZZZZZZZ";
|
end if;
|
end if;
|
|
|
if dat_addr(5) = '1' then
|
if dat_addr(5) = '1' then
|
ram_data_out <= ram_data(15 downto 8);
|
ram_data_out <= ram_data(15 downto 8);
|
else
|
else
|
ram_data_out <= ram_data(7 downto 0);
|
ram_data_out <= ram_data(7 downto 0);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Compact Flash Control
|
-- Compact Flash Control
|
--
|
--
|
compact_flash: process( SysClk, Reset_n,
|
compact_flash: process( SysClk, Reset_n,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
cf_cs, cf_rd, cf_wr, cf_data_out )
|
cf_cs, cf_rd, cf_wr, cf_data_out )
|
begin
|
begin
|
cf_rst_n <= Reset_n;
|
cf_rst_n <= Reset_n;
|
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
|
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
|
cf_cs1_n <= not( cf_cs and cpu_addr(3));
|
cf_cs1_n <= not( cf_cs and cpu_addr(3));
|
cf_cs16_n <= '1';
|
cf_cs16_n <= '1';
|
cf_wr <= cf_cs and (not cpu_rw);
|
cf_wr <= cf_cs and (not cpu_rw);
|
cf_rd <= cf_cs and cpu_rw;
|
cf_rd <= cf_cs and cpu_rw;
|
cf_wr_n <= not cf_wr;
|
cf_wr_n <= not cf_wr;
|
cf_rd_n <= not cf_rd;
|
cf_rd_n <= not cf_rd;
|
cf_a <= cpu_addr(2 downto 0);
|
cf_a <= cpu_addr(2 downto 0);
|
if cf_wr = '1' then
|
if cf_wr = '1' then
|
cf_d(7 downto 0) <= cpu_data_out;
|
cf_d(7 downto 0) <= cpu_data_out;
|
else
|
else
|
cf_d(7 downto 0) <= "ZZZZZZZZ";
|
cf_d(7 downto 0) <= "ZZZZZZZZ";
|
end if;
|
end if;
|
cf_data_out <= cf_d(7 downto 0);
|
cf_data_out <= cf_d(7 downto 0);
|
cf_d(15 downto 8) <= "ZZZZZZZZ";
|
cf_d(15 downto 8) <= "ZZZZZZZZ";
|
end process;
|
end process;
|
|
|
--
|
--
|
-- ROM Map switch
|
-- ROM Map switch
|
-- The Map switch output is initially set
|
-- The Map switch output is initially set
|
-- On a Write to the Map Switch port, clear the Map Switch
|
-- On a Write to the Map Switch port, clear the Map Switch
|
-- and map the RAM in place of the boot ROM.
|
-- and map the RAM in place of the boot ROM.
|
--
|
--
|
--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )
|
--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )
|
--begin
|
--begin
|
-- if SysClk'event and SysClk = '0' then
|
-- if SysClk'event and SysClk = '0' then
|
-- if Reset_n = '0' then
|
-- if Reset_n = '0' then
|
-- map_sw <= '1';
|
-- map_sw <= '1';
|
-- else
|
-- else
|
-- if (map_cs = '1') and (cpu_rw = '0') then
|
-- if (map_cs = '1') and (cpu_rw = '0') then
|
-- map_sw <= '0';
|
-- map_sw <= '0';
|
-- else
|
-- else
|
-- map_sw <= map_sw;
|
-- map_sw <= map_sw;
|
-- end if;
|
-- end if;
|
-- end if;
|
-- end if;
|
-- end if;
|
-- end if;
|
--end process;
|
--end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( Reset_n, uart_irq
|
interrupts : process( Reset_n, uart_irq
|
-- ,timer_irq
|
-- ,timer_irq
|
)
|
)
|
begin
|
begin
|
cpu_reset <= not Reset_n; -- CPU reset is active high
|
cpu_reset <= not Reset_n; -- CPU reset is active high
|
cpu_irq <= uart_irq;
|
cpu_irq <= uart_irq;
|
-- cpu_nmi <= timer_irq;
|
-- cpu_nmi <= timer_irq;
|
cpu_nmi <= '0';
|
cpu_nmi <= '0';
|
cpu_firq <= '0';
|
cpu_firq <= '0';
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0';
|
cpu_hold <= '0';
|
end process;
|
end process;
|
|
|
--
|
--
|
-- flash led to indicate code is working
|
-- flash led to indicate code is working
|
--
|
--
|
increment: process (SysClk, CountL )
|
increment: process (SysClk, CountL )
|
begin
|
begin
|
if(SysClk'event and SysClk = '0') then
|
if(SysClk'event and SysClk = '0') then
|
countL <= countL + 1;
|
countL <= countL + 1;
|
end if;
|
end if;
|
LED <= countL(21);
|
LED <= countL(21);
|
end process;
|
end process;
|
|
|
end my_computer; --===================== End of architecture =======================--
|
end my_computer; --===================== End of architecture =======================--
|
|
|
|
|
