--===========================================================================--
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--===========================================================================--
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--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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--
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-- www.OpenCores.Org - January 2000
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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-- Design units : miniUART core for the System68
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-- Design units : miniUART core for the System68
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--
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--
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-- File name : clkunit2.vhd
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-- File name : clkunit2.vhd
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--
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the CPU68 processor and the Host computer through
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-- between the CPU68 processor and the Host computer through
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-- an RS-232 communication protocol.
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-- an RS-232 communication protocol.
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--
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--
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-- Dependencies : ieee.std_logic_1164
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-- Dependencies : ieee.std_logic_1164
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-- ieee.numeric_std
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-- ieee.numeric_std
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--
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--
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--===========================================================================--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision list
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-- Revision list
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-- Version Author Date Changes
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-- Version Author Date Changes
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--
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- olupas@opencores.org
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-- olupas@opencores.org
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--
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--
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-- 2.0 John Kent 10 November 2002 Added programmable baud rate
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-- 2.0 John Kent 10 November 2002 Added programmable baud rate
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-- 3.0 John Kent 15 December 2002 Fix TX clock divider
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-- 3.0 John Kent 15 December 2002 Fix TX clock divider
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-- 3.1 John kent 12 January 2003 Changed divide by 1 for 38.4Kbps
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-- 3.1 John kent 12 January 2003 Changed divide by 1 for 38.4Kbps
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-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
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-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Generates the Baud clock and enable signals for RX & TX
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-- Description : Generates the Baud clock and enable signals for RX & TX
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-- units.
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-- units.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Entity for Baud rate generator Unit - 9600 baudrate --
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-- Entity for Baud rate generator Unit - 9600 baudrate --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Baud rate generator
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-- Baud rate generator
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity ClkUnit is
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entity ClkUnit is
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port (
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port (
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Clk : in Std_Logic; -- System Clock
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Clk : in Std_Logic; -- System Clock
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Reset : in Std_Logic; -- Reset input
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Reset : in Std_Logic; -- Reset input
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EnableRx : out Std_Logic; -- Control signal
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EnableRx : out Std_Logic; -- Control signal
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EnableTx : out Std_Logic; -- Control signal
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EnableTx : out Std_Logic; -- Control signal
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BaudRate : in Std_Logic_Vector(1 downto 0));
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BaudRate : in Std_Logic_Vector(1 downto 0));
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end; --================== End of entity ==============================--
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end; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for Baud rate generator Unit
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-- Architecture for Baud rate generator Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture Behaviour of ClkUnit is
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architecture Behaviour of ClkUnit is
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signal tmpEnRx : std_logic;
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signal tmpEnRx : std_logic;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Divides the system clock of 40 MHz div 260 gives 153KHz for 9600bps
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-- Divides the system clock of 40 MHz div 260 gives 153KHz for 9600bps
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-- 48 MHz div 156 gives 306KHz for 19.2Kbps
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-- 48 MHz div 156 gives 306KHz for 19.2Kbps
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-- 24 MHz div 156 gives 153KHz for 9600bps
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-- 24 MHz div 156 gives 153KHz for 9600bps
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-- 9.8304MHz div 32 gives 306KHz for 19.2Kbps
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-- 9.8304MHz div 32 gives 306KHz for 19.2Kbps
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-- 4.9152MHz div 32 gives 153KHz for 9600bps
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-- 4.9152MHz div 32 gives 153KHz for 9600bps
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DivClk : process(Clk,Reset,tmpEnRx, BaudRate)
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DivClk : process(Clk,Reset,tmpEnRx, BaudRate)
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variable Count : unsigned(7 downto 0);
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variable Count : unsigned(7 downto 0);
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constant CntOne : Unsigned(7 downto 0):="00000001";
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constant CntOne : Unsigned(7 downto 0):="00000001";
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begin
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begin
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if Clk'event and Clk = '0' then
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if Clk'event and Clk = '0' then
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if Reset = '1' then
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if Reset = '1' then
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Count := "00000000";
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Count := "00000000";
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tmpEnRx <= '0';
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tmpEnRx <= '0';
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else
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else
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if Count = "00000000" then
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if Count = "00000000" then
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tmpEnRx <= '1';
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tmpEnRx <= '1';
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case BaudRate is
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case BaudRate is
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when "00" =>
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when "00" =>
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-- 6850 divide by 1 ((1*2)-1) (synchronous)
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-- 6850 divide by 1 ((1*2)-1) (synchronous)
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-- miniUart 9.83MHz div 16 = 38.4Kbps
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-- miniUart 9.83MHz div 16 = 38.4Kbps
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Count := "00001111";
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Count := "00001111";
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when "01" =>
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when "01" =>
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-- 6850 divide by 16 ((16*2)-1) (9600 Baud)
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-- 6850 divide by 16 ((16*2)-1) (9600 Baud)
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-- miniUart 9.83MHz div 32 = 19.2Kbps
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-- miniUart 9.83MHz div 32 = 19.2Kbps
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Count := "00011111";
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Count := "00011111";
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when "10" =>
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when "10" =>
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-- 6850 divide by 64 ((64*2)-1) (2400 Baud)
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-- 6850 divide by 64 ((64*2)-1) (2400 Baud)
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-- miniUart 9.83MHz div 128 = 4800bps
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-- miniUart 9.83MHz div 128 = 4800bps
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Count := "01111111";
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Count := "01111111";
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when others =>
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when others =>
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-- when "11" => -- reset
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-- when "11" => -- reset
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Count := "00000000";
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Count := "00000000";
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null;
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null;
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end case;
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end case;
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else
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else
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tmpEnRx <= '0';
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tmpEnRx <= '0';
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Count := Count - CntOne;
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Count := Count - CntOne;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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EnableRx <= tmpEnRx;
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EnableRx <= tmpEnRx;
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end process;
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end process;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Provides the EnableTX signal, at 9.6 KHz
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-- Provides the EnableTX signal, at 9.6 KHz
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-- Divide by 16
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-- Divide by 16
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-- Except it wasn't ... it counted up to "10010" (18)
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-- Except it wasn't ... it counted up to "10010" (18)
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DivClk16 : process(Clk,Reset,tmpEnRX)
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DivClk16 : process(Clk,Reset,tmpEnRX)
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variable Cnt16 : unsigned(4 downto 0);
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variable Cnt16 : unsigned(4 downto 0);
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constant CntOne : Unsigned(4 downto 0):="00001";
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constant CntOne : Unsigned(4 downto 0):="00001";
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begin
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begin
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if Clk'event and Clk = '0' then
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if Clk'event and Clk = '0' then
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if Reset = '1' then
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if Reset = '1' then
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Cnt16 := "00000";
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Cnt16 := "00000";
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EnableTX <= '0';
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EnableTX <= '0';
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else
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else
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case Cnt16 is
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case Cnt16 is
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when "00000" =>
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when "00000" =>
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if tmpEnRx = '1' then
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if tmpEnRx = '1' then
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Cnt16 := "01111";
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Cnt16 := "01111";
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EnableTx <='1';
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EnableTx <='1';
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else
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else
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Cnt16 := Cnt16;
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Cnt16 := Cnt16;
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EnableTx <= '0';
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EnableTx <= '0';
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end if;
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end if;
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when others =>
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when others =>
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if tmpEnRx = '1' then
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if tmpEnRx = '1' then
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Cnt16 := Cnt16 - CntOne;
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Cnt16 := Cnt16 - CntOne;
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else
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else
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Cnt16 := Cnt16;
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Cnt16 := Cnt16;
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end if;
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end if;
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EnableTX <= '0';
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EnableTX <= '0';
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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