--===========================================================================--
|
--===========================================================================--
|
--
|
--
|
-- S Y N T H E Z I A B L E miniUART C O R E
|
-- S Y N T H E Z I A B L E miniUART C O R E
|
--
|
--
|
-- www.OpenCores.Org - January 2000
|
-- www.OpenCores.Org - January 2000
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- Design units : miniUART core for the System68
|
-- Design units : miniUART core for the System68
|
--
|
--
|
-- File name : miniuart2.vhd
|
-- File name : miniuart2.vhd
|
--
|
--
|
-- Purpose : Implements an miniUART device for communication purposes
|
-- Purpose : Implements an miniUART device for communication purposes
|
-- between the CPU68 processor and the Host computer through
|
-- between the CPU68 processor and the Host computer through
|
-- an RS-232 communication protocol.
|
-- an RS-232 communication protocol.
|
--
|
--
|
-- Dependencies : ieee.std_logic_1164
|
-- Dependencies : ieee.std_logic_1164
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
--
|
--
|
--===========================================================================--
|
--===========================================================================--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revision list
|
-- Revision list
|
-- Version Author Date Changes
|
-- Version Author Date Changes
|
--
|
--
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
|
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
|
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
|
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
|
-- the RSBusCtrl did not process all possible situations
|
-- the RSBusCtrl did not process all possible situations
|
--
|
--
|
-- olupas@opencores.org
|
-- olupas@opencores.org
|
--
|
--
|
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
|
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
|
-- Added CTS, RTS, Baud rate control
|
-- Added CTS, RTS, Baud rate control
|
-- & Software Reset
|
-- & Software Reset
|
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
|
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
|
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
|
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
|
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
|
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
|
-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Entity for miniUART Unit - 9600 baudrate --
|
-- Entity for miniUART Unit - 9600 baudrate --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
entity miniUART is
|
entity miniUART is
|
port (
|
port (
|
SysClk : in Std_Logic; -- System Clock
|
SysClk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic;
|
cs : in Std_Logic;
|
rw : in Std_Logic;
|
rw : in Std_Logic;
|
RxD : in Std_Logic;
|
RxD : in Std_Logic;
|
TxD : out Std_Logic;
|
TxD : out Std_Logic;
|
CTS_n : in Std_Logic;
|
CTS_n : in Std_Logic;
|
RTS_n : out Std_Logic;
|
RTS_n : out Std_Logic;
|
Irq : out Std_Logic; -- interrupt
|
Irq : out Std_Logic; -- interrupt
|
Addr : in Std_Logic; -- Register Select
|
Addr : in Std_Logic; -- Register Select
|
DataIn : in Std_Logic_Vector(7 downto 0); --
|
DataIn : in Std_Logic_Vector(7 downto 0); --
|
DataOut : out Std_Logic_Vector(7 downto 0)); --
|
DataOut : out Std_Logic_Vector(7 downto 0)); --
|
end; --================== End of entity ==============================--
|
end; --================== End of entity ==============================--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for miniUART Controller Unit
|
-- Architecture for miniUART Controller Unit
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture uart of miniUART is
|
architecture uart of miniUART is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
signal RxData : Std_Logic_Vector(7 downto 0); --
|
signal RxData : Std_Logic_Vector(7 downto 0); --
|
signal TxData : Std_Logic_Vector(7 downto 0); --
|
signal TxData : Std_Logic_Vector(7 downto 0); --
|
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
|
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
|
-- StatReg detailed
|
-- StatReg detailed
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
|
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
|
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
|
-- CtrlReg detailed
|
-- CtrlReg detailed
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- IrqEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-- IrqEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- IrqEnb
|
-- IrqEnb
|
-- 0 - Rx Interrupt disabled
|
-- 0 - Rx Interrupt disabled
|
-- 1 - Rx Interrupt enabled
|
-- 1 - Rx Interrupt enabled
|
-- TxCtl
|
-- TxCtl
|
-- 0 1 - Tx Interrupt Enable
|
-- 0 1 - Tx Interrupt Enable
|
-- 1 0 - RTS high
|
-- 1 0 - RTS high
|
-- WdFmt
|
-- WdFmt
|
-- 0 0 0 - 7 data, even parity, 2 stop
|
-- 0 0 0 - 7 data, even parity, 2 stop
|
-- 0 0 1 - 7 data, odd parity, 2 stop
|
-- 0 0 1 - 7 data, odd parity, 2 stop
|
-- 0 1 0 - 7 data, even parity, 1 stop
|
-- 0 1 0 - 7 data, even parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- BdCtl
|
-- BdCtl
|
-- 0 0 - Baud Clk divide by 1 (not implemented)
|
-- 0 0 - Baud Clk divide by 1 (not implemented)
|
-- 0 1 - Baud Clk divide by 16
|
-- 0 1 - Baud Clk divide by 16
|
-- 1 0 - Baud Clk divide by 64
|
-- 1 0 - Baud Clk divide by 64
|
-- 1 1 - reset
|
-- 1 1 - reset
|
|
|
signal EnabRx : Std_Logic; -- Enable RX unit
|
signal EnabRx : Std_Logic; -- Enable RX unit
|
signal EnabTx : Std_Logic; -- Enable TX unit
|
signal EnabTx : Std_Logic; -- Enable TX unit
|
signal DRdy : Std_Logic; -- Receive Data ready
|
signal DRdy : Std_Logic; -- Receive Data ready
|
signal TBufE : Std_Logic; -- Transmit buffer empty
|
signal TBufE : Std_Logic; -- Transmit buffer empty
|
signal FErr : Std_Logic; -- Frame error
|
signal FErr : Std_Logic; -- Frame error
|
signal OErr : Std_Logic; -- Output error
|
signal OErr : Std_Logic; -- Output error
|
signal PErr : Std_Logic; -- Parity Error
|
signal PErr : Std_Logic; -- Parity Error
|
signal Read : Std_Logic; -- Read receive buffer
|
signal Read : Std_Logic; -- Read receive buffer
|
signal Load : Std_Logic; -- Load transmit buffer
|
signal Load : Std_Logic; -- Load transmit buffer
|
signal Int : Std_Logic; -- Interrupt bit
|
signal Int : Std_Logic; -- Interrupt bit
|
signal Reset : Std_Logic; -- Reset (Software & Hardware)
|
signal Reset : Std_Logic; -- Reset (Software & Hardware)
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Baud rate Generator
|
-- Baud rate Generator
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
component ClkUnit
|
component ClkUnit
|
port (
|
port (
|
Clk : in Std_Logic; -- System Clock
|
Clk : in Std_Logic; -- System Clock
|
Reset : in Std_Logic; -- Reset input
|
Reset : in Std_Logic; -- Reset input
|
EnableRX : out Std_Logic; -- Control signal
|
EnableRX : out Std_Logic; -- Control signal
|
EnableTX : out Std_Logic; -- Control signal
|
EnableTX : out Std_Logic; -- Control signal
|
BaudRate : in Std_Logic_Vector(1 downto 0));
|
BaudRate : in Std_Logic_Vector(1 downto 0));
|
end component;
|
end component;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Receive Unit
|
-- Receive Unit
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
component RxUnit
|
component RxUnit
|
port (
|
port (
|
Clk : in Std_Logic; -- Clock signal
|
Clk : in Std_Logic; -- Clock signal
|
Reset : in Std_Logic; -- Reset input
|
Reset : in Std_Logic; -- Reset input
|
Enable : in Std_Logic; -- Enable input
|
Enable : in Std_Logic; -- Enable input
|
RxD : in Std_Logic; -- RS-232 data input
|
RxD : in Std_Logic; -- RS-232 data input
|
ReadD : in Std_Logic; -- Read data signal
|
ReadD : in Std_Logic; -- Read data signal
|
Format : in Std_Logic_Vector(2 downto 0); -- word format
|
Format : in Std_Logic_Vector(2 downto 0); -- word format
|
FRErr : out Std_Logic; -- Status signal
|
FRErr : out Std_Logic; -- Status signal
|
ORErr : out Std_Logic; -- Status signal
|
ORErr : out Std_Logic; -- Status signal
|
PAErr : out Std_logic; -- Status signal
|
PAErr : out Std_logic; -- Status signal
|
DARdy : out Std_Logic; -- Status signal
|
DARdy : out Std_Logic; -- Status signal
|
DAOut : out Std_Logic_Vector(7 downto 0));
|
DAOut : out Std_Logic_Vector(7 downto 0));
|
end component;
|
end component;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Transmitter Unit
|
-- Transmitter Unit
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
component TxUnit
|
component TxUnit
|
port (
|
port (
|
Clk : in Std_Logic; -- Clock signal
|
Clk : in Std_Logic; -- Clock signal
|
Reset : in Std_Logic; -- Reset input
|
Reset : in Std_Logic; -- Reset input
|
Enable : in Std_Logic; -- Enable input
|
Enable : in Std_Logic; -- Enable input
|
LoadD : in Std_Logic; -- Load transmit data
|
LoadD : in Std_Logic; -- Load transmit data
|
Format : in Std_Logic_Vector(2 downto 0); -- word format
|
Format : in Std_Logic_Vector(2 downto 0); -- word format
|
TxD : out Std_Logic; -- RS-232 data output
|
TxD : out Std_Logic; -- RS-232 data output
|
TBE : out Std_Logic; -- Tx buffer empty
|
TBE : out Std_Logic; -- Tx buffer empty
|
DataO : in Std_Logic_Vector(7 downto 0));
|
DataO : in Std_Logic_Vector(7 downto 0));
|
end component;
|
end component;
|
begin
|
begin
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
ClkDiv : ClkUnit port map (
|
ClkDiv : ClkUnit port map (
|
Clk => SysClk,
|
Clk => SysClk,
|
EnableRx => EnabRX,
|
EnableRx => EnabRX,
|
EnableTx => EnabTX,
|
EnableTx => EnabTX,
|
BaudRate => CtrlReg(1 downto 0),
|
BaudRate => CtrlReg(1 downto 0),
|
Reset => Reset);
|
Reset => Reset);
|
|
|
TxDev : TxUnit port map (
|
TxDev : TxUnit port map (
|
Clk => SysClk,
|
Clk => SysClk,
|
Reset => Reset,
|
Reset => Reset,
|
Enable => EnabTX,
|
Enable => EnabTX,
|
LoadD => Load,
|
LoadD => Load,
|
Format => CtrlReg(4 downto 2),
|
Format => CtrlReg(4 downto 2),
|
TxD => TxD,
|
TxD => TxD,
|
TBE => TBufE,
|
TBE => TBufE,
|
DataO => TxData);
|
DataO => TxData);
|
|
|
RxDev : RxUnit port map (
|
RxDev : RxUnit port map (
|
Clk => SysClk,
|
Clk => SysClk,
|
Reset => Reset,
|
Reset => Reset,
|
Enable => EnabRX,
|
Enable => EnabRX,
|
RxD => RxD,
|
RxD => RxD,
|
ReadD => Read,
|
ReadD => Read,
|
Format => CtrlReg(4 downto 2),
|
Format => CtrlReg(4 downto 2),
|
FRErr => FErr,
|
FRErr => FErr,
|
ORErr => OErr,
|
ORErr => OErr,
|
PAErr => PErr,
|
PAErr => PErr,
|
DARdy => DRdy,
|
DARdy => DRdy,
|
DAOut => RxData);
|
DAOut => RxData);
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Implements the controller for Rx&Tx units
|
-- Implements the controller for Rx&Tx units
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, CTS_n, PErr, Int, CtrlReg)
|
RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, CTS_n, PErr, Int, CtrlReg)
|
variable StatM : Std_Logic_Vector(7 downto 0);
|
variable StatM : Std_Logic_Vector(7 downto 0);
|
begin
|
begin
|
if SysClk'event and SysClk='0' then
|
if SysClk'event and SysClk='0' then
|
if Reset = '1' then
|
if Reset = '1' then
|
StatM := "00000000";
|
StatM := "00000000";
|
Int <= '0';
|
Int <= '0';
|
else
|
else
|
StatM(0) := DRdy;
|
StatM(0) := DRdy;
|
StatM(1) := TBufE;
|
StatM(1) := TBufE;
|
StatM(2) := '0'; -- DCD
|
StatM(2) := '0'; -- DCD
|
StatM(3) := CTS_n;
|
StatM(3) := CTS_n;
|
StatM(4) := FErr; -- Framing error
|
StatM(4) := FErr; -- Framing error
|
StatM(5) := OErr; -- Overrun error
|
StatM(5) := OErr; -- Overrun error
|
StatM(6) := PErr; -- Parity error
|
StatM(6) := PErr; -- Parity error
|
StatM(7) := Int;
|
StatM(7) := Int;
|
Int <= (CtrlReg(7) and DRdy) or
|
Int <= (CtrlReg(7) and DRdy) or
|
((not CtrlReg(6)) and CtrlReg(5) and TBufE);
|
((not CtrlReg(6)) and CtrlReg(5) and TBufE);
|
end if;
|
end if;
|
|
|
RTS_n <= CtrlReg(6) and not CtrlReg(5);
|
RTS_n <= CtrlReg(6) and not CtrlReg(5);
|
Irq <= Int;
|
Irq <= Int;
|
StatReg <= StatM;
|
StatReg <= StatM;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Combinational section
|
-- Combinational section
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
|
control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
|
begin
|
begin
|
if SysClk'event and SysClk='0' then
|
if SysClk'event and SysClk='0' then
|
if (reset = '1') then
|
if (reset = '1') then
|
CtrlReg <= "00000000";
|
CtrlReg <= "00000000";
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
else
|
else
|
if cs = '1' then
|
if cs = '1' then
|
if Addr = '1' then
|
if Addr = '1' then
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
if rw = '0' then -- write data register
|
if rw = '0' then -- write data register
|
TxData <= DataIn;
|
TxData <= DataIn;
|
Load <= '1';
|
Load <= '1';
|
Read <= '0';
|
Read <= '0';
|
else -- read Data Register
|
else -- read Data Register
|
TxData <= TxData;
|
TxData <= TxData;
|
Load <= '0';
|
Load <= '0';
|
Read <= '1';
|
Read <= '1';
|
end if; -- rw
|
end if; -- rw
|
else -- read Status Register
|
else -- read Status Register
|
TxData <= TxData;
|
TxData <= TxData;
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
if rw = '0' then -- write control register
|
if rw = '0' then -- write control register
|
CtrlReg <= DataIn;
|
CtrlReg <= DataIn;
|
else -- read control Register
|
else -- read control Register
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
end if; -- rw
|
end if; -- rw
|
end if; -- Addr
|
end if; -- Addr
|
else -- not selected
|
else -- not selected
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
end if; -- cs
|
end if; -- cs
|
end if; -- reset
|
end if; -- reset
|
end if; -- SysClk
|
end if; -- SysClk
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- set data output mux
|
-- set data output mux
|
--
|
--
|
--------------------------------------------------------------
|
--------------------------------------------------------------
|
|
|
data_port: process(Addr, StatReg, RxData )
|
data_port: process(Addr, StatReg, RxData )
|
begin
|
begin
|
if Addr = '1' then
|
if Addr = '1' then
|
DataOut <= RxData; -- read data register
|
DataOut <= RxData; -- read data register
|
else
|
else
|
DataOut <= StatReg; -- read status register
|
DataOut <= StatReg; -- read status register
|
end if; -- Addr
|
end if; -- Addr
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- reset may be hardware or software
|
-- reset may be hardware or software
|
--
|
--
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
|
|
uart_reset: process(CtrlReg, rst )
|
uart_reset: process(CtrlReg, rst )
|
begin
|
begin
|
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
|
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
|
end process;
|
end process;
|
|
|
end uart; --===================== End of architecture =======================--
|
end uart; --===================== End of architecture =======================--
|
|
|
|
|
