--===========================================================================----
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--===========================================================================----
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--
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--
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-- S Y N T H E Z I A B L E timer - 9 bit timer
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-- S Y N T H E Z I A B L E timer - 9 bit timer
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--
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--
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-- www.OpenCores.Org - September 2003
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-- www.OpenCores.Org - September 2003
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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--
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--
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-- File name : timer.vhd
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-- File name : timer.vhd
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--
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--
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-- Purpose : 9 bit timer module for System 09
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-- Purpose : 9 bit timer module for System 09
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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--
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--
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-- Uses : None
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-- Uses : None
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- Revision History:
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-- Revision History:
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- Version 0.1 - 6 Sept 2002 - John Kent
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-- Version 0.1 - 6 Sept 2002 - John Kent
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-- converted to a single timer
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-- converted to a single timer
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-- made syncronous with system clock
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-- made syncronous with system clock
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--
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--
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-- Version 1.0 - 6 Sept 2003 - John Kent
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-- Version 1.0 - 6 Sept 2003 - John Kent
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-- Realeased to open Cores
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-- Realeased to open Cores
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-- changed Clock Edge
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-- changed Clock Edge
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--
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--
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--===========================================================================
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--===========================================================================
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--
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--
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-- Register Addressing:
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-- Register Addressing:
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-- addr=0 rw=1 down count
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-- addr=0 rw=1 down count
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-- addr=0 rw=0 preset count
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-- addr=0 rw=0 preset count
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-- addr=1 rw=1 status
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-- addr=1 rw=1 status
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-- addr=0 rw=0 control
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-- addr=0 rw=0 control
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--
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--
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-- Control register
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-- Control register
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-- b0 = counter enable
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-- b0 = counter enable
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-- b1 = mode (0 = counter, 1 = timer)
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-- b1 = mode (0 = counter, 1 = timer)
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-- b7 = interrupt enable
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-- b7 = interrupt enable
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--
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--
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-- Status register
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-- Status register
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-- b6 = timer output
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-- b6 = timer output
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-- b7 = interrupt flag
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-- b7 = interrupt flag
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity timer is
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entity timer is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic;
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addr : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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irq : out std_logic;
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timer_in : in std_logic;
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timer_in : in std_logic;
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timer_out : out std_logic
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timer_out : out std_logic
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);
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);
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end;
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end;
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architecture timer_arch of timer is
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architecture timer_arch of timer is
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signal timer_ctrl : std_logic_vector(7 downto 0);
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signal timer_ctrl : std_logic_vector(7 downto 0);
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signal timer_stat : std_logic_vector(7 downto 0);
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signal timer_stat : std_logic_vector(7 downto 0);
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signal timer_reg : std_logic_vector(7 downto 0);
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signal timer_reg : std_logic_vector(7 downto 0);
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signal timer_count : std_logic_vector(7 downto 0);
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signal timer_count : std_logic_vector(7 downto 0);
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signal timer_int : std_logic; -- Timer interrupt
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signal timer_int : std_logic; -- Timer interrupt
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signal timer_term : std_logic; -- Timer terminal count
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signal timer_term : std_logic; -- Timer terminal count
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signal timer_tog : std_logic; -- Timer output
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signal timer_tog : std_logic; -- Timer output
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--
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--
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-- control/status register bits
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-- control/status register bits
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--
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--
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constant T_enab : integer := 0; -- 0=disable, 1=enabled
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constant T_enab : integer := 0; -- 0=disable, 1=enabled
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constant T_mode : integer := 1; -- 0=counter, 1=timer
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constant T_mode : integer := 1; -- 0=counter, 1=timer
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constant T_out : integer := 6; -- 0=disabled, 1=enabled
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constant T_out : integer := 6; -- 0=disabled, 1=enabled
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constant T_irq : integer := 7; -- 0=disabled, 1-enabled
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constant T_irq : integer := 7; -- 0=disabled, 1-enabled
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begin
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begin
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--------------------------------
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--------------------------------
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--
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--
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-- write control registers
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-- write control registers
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-- doesn't do anything yet
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-- doesn't do anything yet
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--
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--
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--------------------------------
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--------------------------------
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timer_write : process( clk, rst, cs, rw, addr, data_in,
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timer_write : process( clk, rst, cs, rw, addr, data_in,
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timer_reg, timer_ctrl, timer_term, timer_count )
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timer_reg, timer_ctrl, timer_term, timer_count )
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begin
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begin
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if clk'event and clk = '0' then
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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timer_reg <= "00000000";
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timer_reg <= "00000000";
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timer_ctrl <= "00000000";
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timer_ctrl <= "00000000";
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elsif cs = '1' and rw = '0' then
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elsif cs = '1' and rw = '0' then
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if addr='0' then
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if addr='0' then
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timer_reg <= data_in;
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timer_reg <= data_in;
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timer_ctrl <= timer_ctrl;
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timer_ctrl <= timer_ctrl;
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timer_term <= '0';
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timer_term <= '0';
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else
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else
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timer_reg <= timer_reg;
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timer_reg <= timer_reg;
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timer_ctrl <= data_in;
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timer_ctrl <= data_in;
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timer_term <= timer_term;
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timer_term <= timer_term;
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end if;
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end if;
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else
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else
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timer_ctrl <= timer_ctrl;
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timer_ctrl <= timer_ctrl;
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timer_reg <= timer_reg;
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timer_reg <= timer_reg;
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if (timer_ctrl(T_enab) = '1') then
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if (timer_ctrl(T_enab) = '1') then
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if (timer_count = "00000000" ) then
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if (timer_count = "00000000" ) then
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timer_term <= '1';
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timer_term <= '1';
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elsif timer_ctrl(T_mode) = '0' then
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elsif timer_ctrl(T_mode) = '0' then
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timer_term <= '0'; -- counter mode, reset on non zero
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timer_term <= '0'; -- counter mode, reset on non zero
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else
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else
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timer_term <= timer_term; -- timer mode, keep as is
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timer_term <= timer_term; -- timer mode, keep as is
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end if;
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end if;
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else
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else
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timer_term <= timer_term;
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timer_term <= timer_term;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--
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--
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-- timer data output mux
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-- timer data output mux
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--
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--
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timer_read : process( addr, timer_count, timer_stat )
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timer_read : process( addr, timer_count, timer_stat )
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begin
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begin
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if addr='0' then
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if addr='0' then
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data_out <= timer_count;
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data_out <= timer_count;
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else
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else
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data_out <= timer_stat;
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data_out <= timer_stat;
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end if;
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end if;
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end process;
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end process;
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--------------------------------
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--------------------------------
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--
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--
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-- counters
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-- counters
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--
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--
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--------------------------------
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--------------------------------
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my_counter: process( clk, rst, timer_ctrl, timer_count, timer_reg, timer_in )
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my_counter: process( clk, rst, timer_ctrl, timer_count, timer_reg, timer_in )
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variable timer_tmp : std_logic;
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variable timer_tmp : std_logic;
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begin
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begin
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if clk'event and clk = '0' then
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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timer_count <= "00000000";
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timer_count <= "00000000";
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timer_tmp := '0';
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timer_tmp := '0';
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else
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else
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if timer_ctrl( T_enab ) = '1' then
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if timer_ctrl( T_enab ) = '1' then
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if timer_in = '0' and timer_tmp = '1' then
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if timer_in = '0' and timer_tmp = '1' then
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timer_tmp := '0';
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timer_tmp := '0';
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if timer_count = "00000000" then
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if timer_count = "00000000" then
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timer_count <= timer_reg;
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timer_count <= timer_reg;
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else
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else
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timer_count <= timer_count - 1;
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timer_count <= timer_count - 1;
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end if;
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end if;
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elsif timer_in = '1' and timer_tmp = '0' then
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elsif timer_in = '1' and timer_tmp = '0' then
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timer_tmp := '1';
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timer_tmp := '1';
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timer_count <= timer_count;
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timer_count <= timer_count;
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else
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else
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timer_tmp := timer_tmp;
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timer_tmp := timer_tmp;
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timer_count <= timer_count;
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timer_count <= timer_count;
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end if;
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end if;
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else
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else
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timer_tmp := timer_tmp;
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timer_tmp := timer_tmp;
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timer_count <= timer_count;
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timer_count <= timer_count;
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end if; -- timer_ctrl
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end if; -- timer_ctrl
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end if; -- rst
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end if; -- rst
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end if; -- clk
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end if; -- clk
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end process;
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end process;
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--
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--
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-- read timer strobe to reset interrupts
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-- read timer strobe to reset interrupts
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--
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--
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timer_interrupt : process( Clk, rst, cs, rw, addr,
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timer_interrupt : process( Clk, rst, cs, rw, addr,
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timer_term, timer_int, timer_ctrl )
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timer_term, timer_int, timer_ctrl )
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begin
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begin
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if clk'event and clk = '0' then
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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timer_int <= '0';
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timer_int <= '0';
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elsif cs = '1' and rw = '1' then
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elsif cs = '1' and rw = '1' then
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if addr = '0' then
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if addr = '0' then
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timer_int <= '0'; -- reset interrupt on read count
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timer_int <= '0'; -- reset interrupt on read count
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else
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else
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timer_int <= timer_int;
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timer_int <= timer_int;
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end if;
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end if;
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else
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else
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if timer_term = '1' then
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if timer_term = '1' then
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timer_int <= '1';
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timer_int <= '1';
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else
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else
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timer_int <= timer_int;
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timer_int <= timer_int;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if timer_ctrl( T_irq ) = '1' then
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if timer_ctrl( T_irq ) = '1' then
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irq <= timer_int;
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irq <= timer_int;
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else
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else
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irq <= '0';
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irq <= '0';
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end if;
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end if;
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end process;
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end process;
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--
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--
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-- timer status register
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-- timer status register
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--
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--
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timer_status : process( timer_ctrl, timer_int, timer_tog )
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timer_status : process( timer_ctrl, timer_int, timer_tog )
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begin
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begin
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timer_stat(5 downto 0) <= timer_ctrl(5 downto 0);
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timer_stat(5 downto 0) <= timer_ctrl(5 downto 0);
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timer_stat(T_out) <= timer_tog;
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timer_stat(T_out) <= timer_tog;
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timer_stat(T_irq) <= timer_int;
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timer_stat(T_irq) <= timer_int;
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end process;
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end process;
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--
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--
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-- timer output
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-- timer output
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--
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--
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timer_output : process( Clk, rst, timer_term, timer_ctrl, timer_tog )
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timer_output : process( Clk, rst, timer_term, timer_ctrl, timer_tog )
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variable timer_tmp : std_logic; -- tracks change in terminal count
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variable timer_tmp : std_logic; -- tracks change in terminal count
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begin
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begin
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if clk'event and clk = '0' then
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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timer_tog <= '0';
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timer_tog <= '0';
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timer_tmp := '0';
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timer_tmp := '0';
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elsif timer_ctrl(T_mode) = '0' then -- free running ?
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elsif timer_ctrl(T_mode) = '0' then -- free running ?
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if (timer_term = '1') and (timer_tmp = '0') then
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if (timer_term = '1') and (timer_tmp = '0') then
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timer_tmp := '1';
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timer_tmp := '1';
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timer_tog <= not timer_tog;
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timer_tog <= not timer_tog;
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elsif (timer_term = '0') and (timer_tmp = '1') then
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elsif (timer_term = '0') and (timer_tmp = '1') then
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timer_tmp := '0';
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timer_tmp := '0';
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timer_tog <= timer_tog;
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timer_tog <= timer_tog;
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else
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else
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timer_tmp := timer_tmp;
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timer_tmp := timer_tmp;
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timer_tog <= timer_tog;
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timer_tog <= timer_tog;
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end if;
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end if;
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else -- one shot timer mode, follow terminal count
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else -- one shot timer mode, follow terminal count
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if (timer_term = '1') and (timer_tmp = '0') then
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if (timer_term = '1') and (timer_tmp = '0') then
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timer_tmp := '1';
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timer_tmp := '1';
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timer_tog <= '1';
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timer_tog <= '1';
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elsif (timer_term = '0') and (timer_tmp = '1') then
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elsif (timer_term = '0') and (timer_tmp = '1') then
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timer_tmp := '0';
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timer_tmp := '0';
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timer_tog <= '0';
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timer_tog <= '0';
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else
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else
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timer_tmp := timer_tmp;
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timer_tmp := timer_tmp;
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timer_tog <= timer_tog;
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timer_tog <= timer_tog;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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timer_out <= timer_tog and timer_ctrl(T_out);
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timer_out <= timer_tog and timer_ctrl(T_out);
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end process;
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end process;
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end timer_arch;
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end timer_arch;
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