---------------------------------------------------------
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---------------------------------------------------------
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--
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--
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-- PS2 Keycode look up table
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-- PS2 Keycode look up table
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-- converts 7 bit key code to ASCII
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-- converts 7 bit key code to ASCII
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-- Address bit 7 = CAPS Lock
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-- Address bit 7 = CAPS Lock
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-- Address bit 8 = Shift
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-- Address bit 8 = Shift
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--
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--
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-- J.E.Kent
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-- J.E.Kent
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-- 18th Oct 2004
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-- 18th Oct 2004
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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library unisim;
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use unisim.all;
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use unisim.all;
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entity key_b4 is
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entity key_b4 is
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (8 downto 0);
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addr : in std_logic_vector (8 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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wdata : in std_logic_vector (7 downto 0)
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wdata : in std_logic_vector (7 downto 0)
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);
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);
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end key_b4;
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end key_b4;
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architecture rtl of key_b4 is
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architecture rtl of key_b4 is
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component RAMB4_S8
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component RAMB4_S8
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generic (
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generic (
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INIT_00, INIT_01, INIT_02, INIT_03,
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INIT_00, INIT_01, INIT_02, INIT_03,
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INIT_04, INIT_05, INIT_06, INIT_07,
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INIT_04, INIT_05, INIT_06, INIT_07,
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INIT_08, INIT_09, INIT_0A, INIT_0B,
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INIT_08, INIT_09, INIT_0A, INIT_0B,
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INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
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INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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en : in std_logic;
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en : in std_logic;
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we : in std_logic;
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we : in std_logic;
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addr : in std_logic_vector(8 downto 0);
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addr : in std_logic_vector(8 downto 0);
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di : in std_logic_vector(7 downto 0);
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di : in std_logic_vector(7 downto 0);
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do : out std_logic_vector(7 downto 0)
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do : out std_logic_vector(7 downto 0)
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);
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);
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end component RAMB4_S8;
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end component RAMB4_S8;
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signal we : std_logic;
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signal we : std_logic;
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begin
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begin
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ROM : RAMB4_S8
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ROM : RAMB4_S8
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generic map (
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generic map (
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INIT_00 => x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
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INIT_00 => x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
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INIT_01 => x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
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INIT_01 => x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
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INIT_02 => x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
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INIT_02 => x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
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INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
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INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
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INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
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INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
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INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
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INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
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INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
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INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
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INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
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INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
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INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
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INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
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INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
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INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
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INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
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INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
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INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
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INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
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INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
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INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
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INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
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INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
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INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
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INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
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INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
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INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
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)
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)
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port map ( clk => clk,
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port map ( clk => clk,
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en => cs,
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en => cs,
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we => we,
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we => we,
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rst => rst,
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rst => rst,
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addr => addr,
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addr => addr,
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di => wdata,
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di => wdata,
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do => rdata
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do => rdata
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);
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);
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my_ram_512 : process ( rw )
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my_ram_512 : process ( rw )
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begin
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begin
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we <= not rw;
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we <= not rw;
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end process;
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end process;
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end architecture rtl;
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end architecture rtl;
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