-- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
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-- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- S Y N T H E Z I A B L E System09 - SOC.
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-- S Y N T H E Z I A B L E System09 - SOC.
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--
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--
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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--
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--
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-- File name : System09.vhd
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-- File name : System09.vhd
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--
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--
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-- Purpose : Top level file for 6809 compatible system on a chip
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-- Purpose : Top level file for 6809 compatible system on a chip
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-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
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-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
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-- Implemented With Digilent Xilinx Starter FPGA board,
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-- Implemented With Digilent Xilinx Starter FPGA board,
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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-- ieee.numeric_std
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--
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--
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-- Uses : mon_rom (kbug_rom2k.vhd) Monitor ROM
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-- Uses : mon_rom (kbug_rom2k.vhd) Monitor ROM
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-- cpu09 (cpu09.vhd) CPU core
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-- cpu09 (cpu09.vhd) CPU core
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-- miniuart (minitUART3.vhd) ACIA / MiniUART
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-- miniuart (minitUART3.vhd) ACIA / MiniUART
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-- (rxunit3.vhd)
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-- (rxunit3.vhd)
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-- (tx_unit3.vhd)
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-- (tx_unit3.vhd)
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- Revision History:
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-- Revision History:
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--===========================================================================--
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--===========================================================================--
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-- Version 0.1 - 20 March 2003
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-- Version 0.1 - 20 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.4 - 29 June 2003
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-- Version 0.4 - 29 June 2003
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--
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--
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-- Version 0.5 - 19 July 2003
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-- Version 0.5 - 19 July 2003
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-- prints out "Hello World"
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-- prints out "Hello World"
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--
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--
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-- Version 0.6 - 5 September 2003
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-- Version 0.6 - 5 September 2003
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-- Runs SBUG
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-- Runs SBUG
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--
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--
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-- Version 1.0- 6 Sep 2003 - John Kent
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-- Version 1.0- 6 Sep 2003 - John Kent
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-- Inverted CLK_50MHZ
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-- Inverted CLK_50MHZ
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-- Initial release to Open Cores
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-- Initial release to Open Cores
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--
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--
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-- Version 1.1 - 17 Jan 2004 - John Kent
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-- Version 1.1 - 17 Jan 2004 - John Kent
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-- Updated miniUart.
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-- Updated miniUart.
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--
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--
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-- Version 1.2 - 25 Jan 2004 - John Kent
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-- Version 1.2 - 25 Jan 2004 - John Kent
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-- removed signals "test_alu" and "test_cc"
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-- removed signals "test_alu" and "test_cc"
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-- Trap hardware re-instated.
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-- Trap hardware re-instated.
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--
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--
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-- Version 1.3 - 11 Feb 2004 - John Kent
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-- Version 1.3 - 11 Feb 2004 - John Kent
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-- Designed forked off to produce System09_VDU
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-- Designed forked off to produce System09_VDU
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-- Added VDU component
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-- Added VDU component
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-- VDU runs at 25MHz and divides the clock by 2 for the CPU
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-- VDU runs at 25MHz and divides the clock by 2 for the CPU
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-- UART Runs at 57.6 Kbps
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-- UART Runs at 57.6 Kbps
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--
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--
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-- Version 2.0 - 2 September 2004 - John Kent
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-- Version 2.0 - 2 September 2004 - John Kent
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-- ported to Digilent Xilinx Spartan3 starter board
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-- ported to Digilent Xilinx Spartan3 starter board
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-- removed Compaact Flash and Trap Logic.
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-- removed Compaact Flash and Trap Logic.
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-- Replaced SBUG with KBug9s
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-- Replaced SBUG with KBug9s
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--
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--
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-- Version 3.0 - 22 April 2006 - John Kent
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-- Version 3.0 - 22 April 2006 - John Kent
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-- Port to Digilent Spartan 3E Starter board
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-- Port to Digilent Spartan 3E Starter board
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-- Removed keyboard, vdu, timer, and trap logic
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-- Removed keyboard, vdu, timer, and trap logic
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-- added PIA with counters attached.
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-- added PIA with counters attached.
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-- Uses 32Kbytes of internal Block RAM
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-- Uses 32Kbytes of internal Block RAM
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--
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--
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-- Version 4.0 - 8th April 2007 - John kent
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-- Version 4.0 - 8th April 2007 - John kent
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-- Added VDU and PS/2 keyboard
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-- Added VDU and PS/2 keyboard
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-- Updated miniUART to ACIA6850
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-- Updated miniUART to ACIA6850
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-- Reduce monitor ROM to 2KB
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-- Reduce monitor ROM to 2KB
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-- Re-assigned I/O port assignments so it is possible to run KBUG9
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-- Re-assigned I/O port assignments so it is possible to run KBUG9
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-- $E000 - ACIA
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-- $E000 - ACIA
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-- $E020 - Keyboard
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-- $E020 - Keyboard
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-- $E030 - VDU
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-- $E030 - VDU
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-- $E040 - Compact Flash (not implemented)
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-- $E040 - Compact Flash (not implemented)
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-- $E050 - Timer
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-- $E050 - Timer
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-- $E060 - Bus trap
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-- $E060 - Bus trap
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-- $E070 - Parallel I/O
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-- $E070 - Parallel I/O
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--
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--
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--===========================================================================--
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--===========================================================================--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity my_system09 is
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entity my_system09 is
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port(
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port(
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CLK_50MHZ : in Std_Logic; -- System Clock input
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CLK_50MHZ : in Std_Logic; -- System Clock input
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BTN_SOUTH : in Std_Logic;
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BTN_SOUTH : in Std_Logic;
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|
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-- PS/2 Keyboard
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-- PS/2 Keyboard
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PS2_CLK : inout Std_logic;
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PS2_CLK : inout Std_logic;
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PS2_DATA : inout Std_Logic;
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PS2_DATA : inout Std_Logic;
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|
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-- CRTC output signals
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-- CRTC output signals
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VGA_VSYNC : out Std_Logic;
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VGA_VSYNC : out Std_Logic;
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VGA_HSYNC : out Std_Logic;
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VGA_HSYNC : out Std_Logic;
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VGA_BLUE : out std_logic;
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VGA_BLUE : out std_logic;
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VGA_GREEN : out std_logic;
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VGA_GREEN : out std_logic;
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VGA_RED : out std_logic;
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VGA_RED : out std_logic;
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|
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-- Uart Interface
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-- Uart Interface
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RS232_DCE_RXD : in std_logic;
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RS232_DCE_RXD : in std_logic;
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RS232_DCE_TXD : out std_logic;
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RS232_DCE_TXD : out std_logic;
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|
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-- LEDS & Switches
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-- LEDS & Switches
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LED : out std_logic_vector(7 downto 0)
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LED : out std_logic_vector(7 downto 0)
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);
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);
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end my_system09;
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end my_system09;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture my_computer of my_system09 is
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architecture my_computer of my_system09 is
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
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constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
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constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
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constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
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constant BAUD_Rate : integer := 57600; -- Baud Rate
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constant BAUD_Rate : integer := 57600; -- Baud Rate
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constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
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constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
|
|
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
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-- BOOT ROM
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-- BOOT ROM
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signal rom_cs : Std_logic;
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signal rom_cs : Std_logic;
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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|
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-- UART Interface signals
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-- UART Interface signals
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signal uart_data_out : Std_Logic_Vector(7 downto 0);
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signal uart_data_out : Std_Logic_Vector(7 downto 0);
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signal uart_cs : Std_Logic;
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signal uart_cs : Std_Logic;
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signal uart_irq : Std_Logic;
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signal uart_irq : Std_Logic;
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signal uart_clk : Std_Logic;
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signal uart_clk : Std_Logic;
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signal rxbit : Std_Logic;
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signal rxbit : Std_Logic;
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signal txbit : Std_Logic;
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signal txbit : Std_Logic;
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signal DCD_n : Std_Logic;
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signal DCD_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal CTS_n : Std_Logic;
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signal CTS_n : Std_Logic;
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|
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-- timer
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-- timer
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signal timer_data_out : std_logic_vector(7 downto 0);
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signal timer_data_out : std_logic_vector(7 downto 0);
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signal timer_cs : std_logic;
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signal timer_cs : std_logic;
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signal timer_irq : std_logic;
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signal timer_irq : std_logic;
|
|
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-- trap
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-- trap
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signal trap_cs : std_logic;
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signal trap_cs : std_logic;
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signal trap_data_out : std_logic_vector(7 downto 0);
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signal trap_data_out : std_logic_vector(7 downto 0);
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signal trap_irq : std_logic;
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signal trap_irq : std_logic;
|
|
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-- PIA Interface signals
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-- PIA Interface signals
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signal pia_data_out : Std_Logic_Vector(7 downto 0);
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signal pia_data_out : Std_Logic_Vector(7 downto 0);
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signal pia_cs : Std_Logic;
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signal pia_cs : Std_Logic;
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signal pia_irq_a : Std_Logic;
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signal pia_irq_a : Std_Logic;
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signal pia_irq_b : Std_Logic;
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signal pia_irq_b : Std_Logic;
|
|
|
-- keyboard port
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-- keyboard port
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signal keyboard_data_out : std_logic_vector(7 downto 0);
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signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_cs : std_logic;
|
signal keyboard_cs : std_logic;
|
signal keyboard_irq : std_logic;
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signal keyboard_irq : std_logic;
|
|
|
-- Video Display Unit
|
-- Video Display Unit
|
signal pix_clk : std_logic;
|
signal pix_clk : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_reset : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- CLK_50MHZ clock divide by 2
|
-- CLK_50MHZ clock divide by 2
|
signal clock_div : std_logic_vector(1 downto 0);
|
signal clock_div : std_logic_vector(1 downto 0);
|
signal SysClk : std_logic;
|
signal SysClk : std_logic;
|
signal Reset_n : std_logic;
|
signal Reset_n : std_logic;
|
signal CountL : std_logic_vector(23 downto 0);
|
signal CountL : std_logic_vector(23 downto 0);
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
rw: out std_logic; -- Asynchronous memory interface
|
rw: out std_logic; -- Asynchronous memory interface
|
vma: out std_logic;
|
vma: out std_logic;
|
address: out std_logic_vector(15 downto 0);
|
address: out std_logic_vector(15 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
halt: in std_logic;
|
halt: in std_logic;
|
hold: in std_logic;
|
hold: in std_logic;
|
irq: in std_logic;
|
irq: in std_logic;
|
nmi: in std_logic;
|
nmi: in std_logic;
|
firq: in std_logic
|
firq: in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Block RAM Monitor ROM
|
-- Block RAM Monitor ROM
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component mon_rom
|
component mon_rom
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
wdata : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Block RAM Monitor
|
-- Block RAM Monitor
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component ram_32k
|
component ram_32k
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (14 downto 0);
|
addr : in std_logic_vector (14 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
wdata : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- 6822 compatible PIA with counters
|
-- 6822 compatible PIA with counters
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component pia_timer
|
component pia_timer
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector(1 downto 0);
|
addr : in std_logic_vector(1 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irqa : out std_logic;
|
irqa : out std_logic;
|
irqb : out std_logic
|
irqb : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- 6850 ACIA/UART
|
-- 6850 ACIA/UART
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_6850
|
component ACIA_6850
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- miniUART Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
Addr : in Std_Logic; -- Register Select
|
Addr : in Std_Logic; -- Register Select
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
RxC : in Std_Logic; -- Receive Baud Clock
|
RxC : in Std_Logic; -- Receive Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
RxD : in Std_Logic; -- Receive Data
|
RxD : in Std_Logic; -- Receive Data
|
TxD : out Std_Logic; -- Transmit Data
|
TxD : out Std_Logic; -- Transmit Data
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
CTS_n : in Std_Logic; -- Clear To Send
|
CTS_n : in Std_Logic; -- Clear To Send
|
RTS_n : out Std_Logic ); -- Request To send
|
RTS_n : out Std_Logic ); -- Request To send
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- ACIA Clock divider
|
-- ACIA Clock divider
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_Clock
|
component ACIA_Clock
|
generic (
|
generic (
|
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
|
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
|
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
|
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
|
);
|
);
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer module
|
-- Timer module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component timer
|
component timer
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic;
|
addr : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
-- ;
|
-- ;
|
-- timer_in : in std_logic;
|
-- timer_in : in std_logic;
|
-- timer_out : out std_logic
|
-- timer_out : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------------------------------------
|
------------------------------------------------------------
|
--
|
--
|
-- Bus Trap logic
|
-- Bus Trap logic
|
--
|
--
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
|
component trap
|
component trap
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
vma : in std_logic;
|
vma : in std_logic;
|
addr : in std_logic_vector(15 downto 0);
|
addr : in std_logic_vector(15 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- PS/2 Keyboard
|
-- PS/2 Keyboard
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component keyboard
|
component keyboard
|
generic(
|
generic(
|
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
|
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic;
|
addr : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic;
|
irq : out std_logic;
|
kbd_clk : inout std_logic;
|
kbd_clk : inout std_logic;
|
kbd_data : inout std_logic
|
kbd_data : inout std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Video Display Unit.
|
-- Video Display Unit.
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component vdu8
|
component vdu8
|
generic(
|
generic(
|
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
|
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
|
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
|
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
|
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
|
VGA_LINES_PER_CHAR : integer := 16; -- LINES
|
VGA_LINES_PER_CHAR : integer := 16; -- LINES
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_SYNC : integer := 1; -- LINES
|
VGA_VER_SYNC : integer := 1; -- LINES
|
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
|
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
|
);
|
);
|
port(
|
port(
|
-- control register interface
|
-- control register interface
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_rst : in std_logic;
|
vdu_rst : in std_logic;
|
vdu_cs : in std_logic;
|
vdu_cs : in std_logic;
|
vdu_rw : in std_logic;
|
vdu_rw : in std_logic;
|
vdu_addr : in std_logic_vector(2 downto 0);
|
vdu_addr : in std_logic_vector(2 downto 0);
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_red_o : out std_logic;
|
vga_red_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_hsync_o : out std_logic;
|
vga_hsync_o : out std_logic;
|
vga_vsync_o : out std_logic
|
vga_vsync_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
component BUFG
|
component BUFG
|
port (
|
port (
|
i: in std_logic;
|
i: in std_logic;
|
o: out std_logic
|
o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
address => cpu_addr(15 downto 0),
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
halt => cpu_halt,
|
halt => cpu_halt,
|
hold => cpu_hold,
|
hold => cpu_hold,
|
irq => cpu_irq,
|
irq => cpu_irq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
firq => cpu_firq
|
firq => cpu_firq
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
my_rom : mon_rom port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => rom_cs,
|
cs => rom_cs,
|
rw => '1',
|
rw => '1',
|
addr => cpu_addr(10 downto 0),
|
addr => cpu_addr(10 downto 0),
|
rdata => rom_data_out,
|
rdata => rom_data_out,
|
wdata => cpu_data_out
|
wdata => cpu_data_out
|
);
|
);
|
|
|
my_ram : ram_32k port map (
|
my_ram : ram_32k port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => ram_cs,
|
cs => ram_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(14 downto 0),
|
addr => cpu_addr(14 downto 0),
|
rdata => ram_data_out,
|
rdata => ram_data_out,
|
wdata => cpu_data_out
|
wdata => cpu_data_out
|
);
|
);
|
|
|
my_pia : pia_timer port map (
|
my_pia : pia_timer port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => pia_cs,
|
cs => pia_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(1 downto 0),
|
addr => cpu_addr(1 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => pia_data_out,
|
data_out => pia_data_out,
|
irqa => pia_irq_a,
|
irqa => pia_irq_a,
|
irqb => pia_irq_b
|
irqb => pia_irq_b
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- ACIA/UART Serial interface
|
-- ACIA/UART Serial interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_ACIA : ACIA_6850 port map (
|
my_ACIA : ACIA_6850 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => uart_cs,
|
cs => uart_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
irq => uart_irq,
|
irq => uart_irq,
|
Addr => cpu_addr(0),
|
Addr => cpu_addr(0),
|
Datain => cpu_data_out,
|
Datain => cpu_data_out,
|
DataOut => uart_data_out,
|
DataOut => uart_data_out,
|
RxC => uart_clk,
|
RxC => uart_clk,
|
TxC => uart_clk,
|
TxC => uart_clk,
|
RxD => rxbit,
|
RxD => rxbit,
|
TxD => txbit,
|
TxD => txbit,
|
DCD_n => dcd_n,
|
DCD_n => dcd_n,
|
CTS_n => cts_n,
|
CTS_n => cts_n,
|
RTS_n => rts_n
|
RTS_n => rts_n
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- ACIA Clock
|
-- ACIA Clock
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
)
|
)
|
port map(
|
port map(
|
clk => SysClk,
|
clk => SysClk,
|
acia_clk => uart_clk
|
acia_clk => uart_clk
|
);
|
);
|
|
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- PS/2 Keyboard Interface
|
-- PS/2 Keyboard Interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_keyboard : keyboard
|
my_keyboard : keyboard
|
generic map (
|
generic map (
|
KBD_Clock_Frequency => CPU_Clock_frequency
|
KBD_Clock_Frequency => CPU_Clock_frequency
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => keyboard_cs,
|
cs => keyboard_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out(7 downto 0),
|
data_in => cpu_data_out(7 downto 0),
|
data_out => keyboard_data_out(7 downto 0),
|
data_out => keyboard_data_out(7 downto 0),
|
irq => keyboard_irq,
|
irq => keyboard_irq,
|
kbd_clk => PS2_CLK,
|
kbd_clk => PS2_CLK,
|
kbd_data => PS2_DATA
|
kbd_data => PS2_DATA
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Video Display Unit instantiation
|
-- Video Display Unit instantiation
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_vdu : vdu8
|
my_vdu : vdu8
|
generic map(
|
generic map(
|
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
|
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
|
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
|
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
|
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
|
VGA_LINES_PER_CHAR => 16, -- LINES
|
VGA_LINES_PER_CHAR => 16, -- LINES
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_SYNC => 1, -- LINES
|
VGA_VER_SYNC => 1, -- LINES
|
VGA_VER_FRONT_PORCH => 36 -- LINES
|
VGA_VER_FRONT_PORCH => 36 -- LINES
|
)
|
)
|
port map(
|
port map(
|
|
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
vdu_rst => cpu_reset,
|
vdu_rst => cpu_reset,
|
vdu_cs => vdu_cs,
|
vdu_cs => vdu_cs,
|
vdu_rw => cpu_rw,
|
vdu_rw => cpu_rw,
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
|
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
|
vga_red_o => vga_red,
|
vga_red_o => vga_red,
|
vga_green_o => vga_green,
|
vga_green_o => vga_green,
|
vga_blue_o => vga_blue,
|
vga_blue_o => vga_blue,
|
vga_hsync_o => vga_hsync,
|
vga_hsync_o => vga_hsync,
|
vga_vsync_o => vga_vsync
|
vga_vsync_o => vga_vsync
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_timer : timer port map (
|
my_timer : timer port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => timer_cs,
|
cs => timer_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => timer_data_out,
|
data_out => timer_data_out,
|
irq => timer_irq
|
irq => timer_irq
|
-- ,
|
-- ,
|
-- timer_in => CountL(5)
|
-- timer_in => CountL(5)
|
-- timer_out => timer_out
|
-- timer_out => timer_out
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Bus Trap Interrupt logic
|
-- Bus Trap Interrupt logic
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_trap : trap port map (
|
my_trap : trap port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => trap_cs,
|
cs => trap_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
addr => cpu_addr,
|
addr => cpu_addr,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => trap_data_out,
|
data_out => trap_data_out,
|
irq => trap_irq
|
irq => trap_irq
|
);
|
);
|
|
|
--
|
--
|
-- 25 MHz CPU clock
|
-- 25 MHz CPU clock
|
--
|
--
|
cpu_clk_buffer : BUFG port map(
|
cpu_clk_buffer : BUFG port map(
|
i => clock_div(0),
|
i => clock_div(0),
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
|
--
|
--
|
-- 25 MHz VGA Pixel clock
|
-- 25 MHz VGA Pixel clock
|
--
|
--
|
vga_clk_buffer : BUFG port map(
|
vga_clk_buffer : BUFG port map(
|
i => clock_div(0),
|
i => clock_div(0),
|
o => pix_clk
|
o => pix_clk
|
);
|
);
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( cpu_clk, Reset_n,
|
mem_decode: process( cpu_clk, Reset_n,
|
cpu_addr, cpu_rw, cpu_vma,
|
cpu_addr, cpu_rw, cpu_vma,
|
rom_data_out,
|
rom_data_out,
|
ram_data_out,
|
ram_data_out,
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
pia_data_out,
|
pia_data_out,
|
uart_data_out,
|
uart_data_out,
|
keyboard_data_out,
|
keyboard_data_out,
|
vdu_data_out )
|
vdu_data_out )
|
variable decode_addr : std_logic_vector(3 downto 0);
|
variable decode_addr : std_logic_vector(3 downto 0);
|
begin
|
begin
|
-- decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
|
-- decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
|
decode_addr := cpu_addr(15 downto 12);
|
decode_addr := cpu_addr(15 downto 12);
|
|
|
case decode_addr is
|
case decode_addr is
|
--
|
--
|
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
|
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
|
--
|
--
|
when "1111" => -- $F000 - $FFFF
|
when "1111" => -- $F000 - $FFFF
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
ram_cs <= '0';
|
ram_cs <= '0';
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- IO Devices $E000 - $EFFF
|
-- IO Devices $E000 - $EFFF
|
--
|
--
|
when "1110" => -- $E000 - $E7FF
|
when "1110" => -- $E000 - $E7FF
|
rom_cs <= '0';
|
rom_cs <= '0';
|
ram_cs <= '0';
|
ram_cs <= '0';
|
case cpu_addr(7 downto 4) is
|
case cpu_addr(7 downto 4) is
|
--
|
--
|
-- UART / ACIA $E000
|
-- UART / ACIA $E000
|
--
|
--
|
when "0000" => -- $E000
|
when "0000" => -- $E000
|
cpu_data_in <= uart_data_out;
|
cpu_data_in <= uart_data_out;
|
uart_cs <= cpu_vma;
|
uart_cs <= cpu_vma;
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- WD1771 FDC sites at $E010-$E01F
|
-- WD1771 FDC sites at $E010-$E01F
|
--
|
--
|
when "0001" => -- $E010
|
when "0001" => -- $E010
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- Keyboard port $E020 - $E02F
|
-- Keyboard port $E020 - $E02F
|
--
|
--
|
when "0010" => -- $E020
|
when "0010" => -- $E020
|
cpu_data_in <= keyboard_data_out;
|
cpu_data_in <= keyboard_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= cpu_vma;
|
keyboard_cs <= cpu_vma;
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- VDU port $E030 - $E03F
|
-- VDU port $E030 - $E03F
|
--
|
--
|
when "0011" => -- $E030
|
when "0011" => -- $E030
|
cpu_data_in <= vdu_data_out;
|
cpu_data_in <= vdu_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= cpu_vma;
|
vdu_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Compact Flash $E040 - $E04F
|
-- Compact Flash $E040 - $E04F
|
--
|
--
|
when "0100" => -- $E040
|
when "0100" => -- $E040
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- Timer $E050 - $E05F
|
-- Timer $E050 - $E05F
|
--
|
--
|
when "0101" => -- $E050
|
when "0101" => -- $E050
|
cpu_data_in <= timer_data_out;
|
cpu_data_in <= timer_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= cpu_vma;
|
timer_cs <= cpu_vma;
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- Bus Trap Logic $E060 - $E06F
|
-- Bus Trap Logic $E060 - $E06F
|
--
|
--
|
when "0110" => -- $E060
|
when "0110" => -- $E060
|
cpu_data_in <= trap_data_out;
|
cpu_data_in <= trap_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= cpu_vma;
|
trap_cs <= cpu_vma;
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
--
|
--
|
-- I/O port $E070 - $E07F
|
-- I/O port $E070 - $E07F
|
--
|
--
|
when "0111" => -- $E070
|
when "0111" => -- $E070
|
cpu_data_in <= pia_data_out;
|
cpu_data_in <= pia_data_out;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= cpu_vma;
|
pia_cs <= cpu_vma;
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
when others => -- $E080 to $E7FF
|
when others => -- $E080 to $E7FF
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
end case;
|
end case;
|
|
|
--
|
--
|
-- $8000 to $DFFF = null
|
-- $8000 to $DFFF = null
|
--
|
--
|
when "1101" | "1100" | "1011" | "1010" |
|
when "1101" | "1100" | "1011" | "1010" |
|
"1001" | "1000" =>
|
"1001" | "1000" =>
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
rom_cs <= '0';
|
rom_cs <= '0';
|
ram_cs <= '0';
|
ram_cs <= '0';
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
when others =>
|
when others =>
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
rom_cs <= '0';
|
rom_cs <= '0';
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( Reset_n,
|
interrupts : process( Reset_n,
|
pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
|
pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
|
)
|
)
|
begin
|
begin
|
cpu_reset <= not Reset_n; -- CPU reset is active high
|
cpu_reset <= not Reset_n; -- CPU reset is active high
|
cpu_irq <= uart_irq or keyboard_irq;
|
cpu_irq <= uart_irq or keyboard_irq;
|
cpu_nmi <= pia_irq_a or trap_irq;
|
cpu_nmi <= pia_irq_a or trap_irq;
|
cpu_firq <= pia_irq_b or timer_irq;
|
cpu_firq <= pia_irq_b or timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0';
|
cpu_hold <= '0';
|
end process;
|
end process;
|
|
|
--
|
--
|
--
|
--
|
my_led_flasher: process( SysClk, Reset_n, CountL )
|
my_led_flasher: process( SysClk, Reset_n, CountL )
|
begin
|
begin
|
if Reset_n = '0' then
|
if Reset_n = '0' then
|
CountL <= "000000000000000000000000";
|
CountL <= "000000000000000000000000";
|
elsif(SysClk'event and SysClk = '0') then
|
elsif(SysClk'event and SysClk = '0') then
|
CountL <= CountL + 1;
|
CountL <= CountL + 1;
|
end if;
|
end if;
|
LED(7 downto 0) <= CountL(23 downto 16);
|
LED(7 downto 0) <= CountL(23 downto 16);
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Clock divider
|
-- Clock divider
|
--
|
--
|
my_clock_divider: process( SysClk )
|
my_clock_divider: process( SysClk )
|
begin
|
begin
|
if SysClk'event and SysClk='0' then
|
if SysClk'event and SysClk='0' then
|
clock_div <= clock_div + "01";
|
clock_div <= clock_div + "01";
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
DCD_n <= '0';
|
DCD_n <= '0';
|
CTS_n <= '0';
|
CTS_n <= '0';
|
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
|
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
|
SysClk <= CLK_50MHZ;
|
SysClk <= CLK_50MHZ;
|
rxbit <= RS232_DCE_RXD;
|
rxbit <= RS232_DCE_RXD;
|
RS232_DCE_TXD <= txbit;
|
RS232_DCE_TXD <= txbit;
|
|
|
end my_computer; --===================== End of architecture =======================--
|
end my_computer; --===================== End of architecture =======================--
|
|
|
|
|
