PK
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PK
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__OBJSTORE__/PK
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__OBJSTORE__/PK
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__OBJSTORE__/common/PK
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__OBJSTORE__/common/PK
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' __OBJSTORE__/common/HierarchicalDesign/PK
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' __OBJSTORE__/common/HierarchicalDesign/PK
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7L L 0 __OBJSTORE__/common/HierarchicalDesign/HDProject PK
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7L L 0 __OBJSTORE__/common/HierarchicalDesign/HDProject PK
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#W o( ( 7 __OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl 1 4 /my_system09 my_system09 PK
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#W o( ( 7 __OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl 1 4 /my_system09 my_system09 PK
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";< < + __OBJSTORE__/common/__stored_object_table__ ( : PK
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";< < + __OBJSTORE__/common/__stored_object_table__ ( : PK
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__OBJSTORE__/HierarchicalDesign/PK
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__OBJSTORE__/HierarchicalDesign/PK
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__OBJSTORE__/PnAutoRun/PK
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__OBJSTORE__/PnAutoRun/PK
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__OBJSTORE__/PnAutoRun/Scripts/PK
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__OBJSTORE__/PnAutoRun/Scripts/PK
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> * __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl PK
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> * __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl PK
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髭 1 __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl namespace eval xilinx {
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髭 1 __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl namespace eval xilinx {
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namespace eval Dpm {
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namespace eval Dpm {
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proc GetIseVersion {} {
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proc GetIseVersion {} {
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set fsetName "fileset.txt"
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set fsetName "fileset.txt"
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set fsetPath ""
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set fsetPath ""
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# Find the file in the Xilinx environment.
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# Find the file in the Xilinx environment.
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# First, construct the environment path.
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# First, construct the environment path.
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set sep ":"; # Default to UNIX style seperator.
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set sep ":"; # Default to UNIX style seperator.
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if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
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if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
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set sep ";"; # Platform is a Windows variant, so use semi-colon.
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set sep ";"; # Platform is a Windows variant, so use semi-colon.
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}
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}
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set xilinxPath $::env(XILINX)
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set xilinxPath $::env(XILINX)
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if [info exists ::env(MYXILINX)] then {
|
if [info exists ::env(MYXILINX)] then {
|
set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
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set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
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}
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}
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# Now look in each path of the path until we find a match.
|
# Now look in each path of the path until we find a match.
|
foreach xilElem [split $xilinxPath $sep] {
|
foreach xilElem [split $xilinxPath $sep] {
|
set checkPath ${xilElem}/$fsetName
|
set checkPath ${xilElem}/$fsetName
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set checkPath [ string map { \\ / } $checkPath ]
|
set checkPath [ string map { \\ / } $checkPath ]
|
if { [file exists $checkPath] } {
|
if { [file exists $checkPath] } {
|
set fsetPath $checkPath
|
set fsetPath $checkPath
|
break
|
break
|
}
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}
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}
|
}
|
if { [string equal $fsetPath ""] } {
|
if { [string equal $fsetPath ""] } {
|
puts "ERROR: Can not determine the ISE software version."
|
puts "ERROR: Can not determine the ISE software version."
|
return ""
|
return ""
|
}
|
}
|
if { [catch { open $fsetPath r } fset] } {
|
if { [catch { open $fsetPath r } fset] } {
|
puts "ERROR: Could not open $fsetPath: $fset"
|
puts "ERROR: Could not open $fsetPath: $fset"
|
return ""
|
return ""
|
}
|
}
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# have the file open, scan for the version entry.
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# have the file open, scan for the version entry.
|
set sVersion ""
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set sVersion ""
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while { ![eof $fset] } {
|
while { ![eof $fset] } {
|
set line [gets $fset]
|
set line [gets $fset]
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regexp {version=(.*)} $line match sVersion
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regexp {version=(.*)} $line match sVersion
|
# The above doesn't stop looking in the file. This assumes that if
|
# The above doesn't stop looking in the file. This assumes that if
|
# there are multiple version entries, the last one is the one we want.
|
# there are multiple version entries, the last one is the one we want.
|
}
|
}
|
close $fset
|
close $fset
|
return $sVersion
|
return $sVersion
|
}
|
}
|
proc CheckForIron {project_name} {
|
proc CheckForIron {project_name} {
|
|
|
# Determine if the currently running version of ProjNav is earlier than Jade.
|
# Determine if the currently running version of ProjNav is earlier than Jade.
|
set version [GetIseVersion]
|
set version [GetIseVersion]
|
set dotLocation [string first "." $version]
|
set dotLocation [string first "." $version]
|
set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
|
set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
|
if {$versionBase < 9} {
|
if {$versionBase < 9} {
|
|
|
# The project file is newer than Iron, so take action to prevent the
|
# The project file is newer than Iron, so take action to prevent the
|
# file from being corrupted.
|
# file from being corrupted.
|
# Make the file read-only.
|
# Make the file read-only.
|
if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
|
if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
|
# The above will return 0 for a match to "windows" or "windows64".
|
# The above will return 0 for a match to "windows" or "windows64".
|
# This is the non-zero part of the if, for lin and sol.
|
# This is the non-zero part of the if, for lin and sol.
|
# Change the permissions to turn off writability.
|
# Change the permissions to turn off writability.
|
file attributes $project_name -permissions a-w
|
file attributes $project_name -permissions a-w
|
} else {
|
} else {
|
# On Windows, set file to read-only.
|
# On Windows, set file to read-only.
|
file attributes $project_name -readonly 1
|
file attributes $project_name -readonly 1
|
}
|
}
|
|
|
# And tell the user about it.
|
# And tell the user about it.
|
set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
|
set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
|
# In the console window
|
# In the console window
|
puts $messageText
|
puts $messageText
|
# And with a GUI message box if possible.
|
# And with a GUI message box if possible.
|
::xilinx::Dpm::TOE::loadGuiLibraries
|
::xilinx::Dpm::TOE::loadGuiLibraries
|
set iInterface 0
|
set iInterface 0
|
set messageDisplay 0
|
set messageDisplay 0
|
if {[catch {
|
if {[catch {
|
set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
|
set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
|
set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
|
set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
|
if {$messageDisplay != 0} {
|
if {$messageDisplay != 0} {
|
# Managed to get a component to display a dialog, so use it
|
# Managed to get a component to display a dialog, so use it
|
set messageTitle "Incompatible Project Version (Newer)"
|
set messageTitle "Incompatible Project Version (Newer)"
|
set messageType 2
|
set messageType 2
|
# 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
|
# 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
|
set messageTimeout 300000
|
set messageTimeout 300000
|
# in milliseconds, 5 minutes
|
# in milliseconds, 5 minutes
|
set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
|
set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
|
}
|
}
|
} catchResult]} {
|
} catchResult]} {
|
# There was an error, probably because we aren't in a GUI enviroment.
|
# There was an error, probably because we aren't in a GUI enviroment.
|
} else {
|
} else {
|
# All is well.
|
# All is well.
|
}
|
}
|
set messageDisplay 0
|
set messageDisplay 0
|
set iInterface 0
|
set iInterface 0
|
}
|
}
|
|
|
return 1
|
return 1
|
}
|
}
|
}
|
}
|
}
|
}
|
::xilinx::Dpm::CheckForIron PK
|
::xilinx::Dpm::CheckForIron PK
|
__OBJSTORE__/ProjectNavigator/PK
|
__OBJSTORE__/ProjectNavigator/PK
|
/ __OBJSTORE__/ProjectNavigator/dpm_project_main/PK
|
/ __OBJSTORE__/ProjectNavigator/dpm_project_main/PK
|
XK4P P ? __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main F y PK
|
XK4P P ? __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main F y PK
|
ɀ* * F __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl System09 acr2 spartan3 virtex5 PK
|
ɀ* * F __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl System09 acr2 spartan3 virtex5 PK
|
\&; &; 0 __OBJSTORE__/ProjectNavigator/__stored_objects__
|
\&; &; 0 __OBJSTORE__/ProjectNavigator/__stored_objects__
|
q ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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Gomy_system09.ngc
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Gmy_system09_vhdl.prj
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|
G
|
|
|
P x
|
P x
|
|
|
|
|
|
|
G
|
G
|
|
|
P x
|
P x
|
GU 0
|
GU 0
|
|
|
|
|
|
|
|
|
y G
|
y G
|
|
|
P
|
P
|
|
|
G
|
G
|
|
|
P
|
P
|
G
|
G
|
|
|
P
|
P
|
|
|
|
|
|
|
|
|
G
|
G
|
|
|
P
|
P
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
GU 0
|
GU 0
|
|
|
Q
|
Q
|
|
|
|
|
|
|
z GU 0
|
z GU 0
|
|
|
F
|
F
|
|
|
|
|
{ GU ܰ
|
{ GU ܰ
|
C
|
C
|
GU ܰ
|
GU ܰ
|
B G
|
B G
|
|
|
P
|
P
|
A
|
A
|
|
|
G
|
G
|
|
|
P
|
P
|
@
|
@
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
? GU 0
|
? GU 0
|
|
|
|
|
|
|
|
|
|
|
| GU 0
|
| GU 0
|
|
|
|
|
|
|
|
|
} GU ܰ
|
} GU ܰ
|
|
|
GU ܰ
|
GU ܰ
|
GU ܰ
|
GU ܰ
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
GU 0
|
GU 0
|
|
|
}
|
}
|
|
|
|
|
|
|
~ GU 0
|
~ GU 0
|
|
|
r
|
r
|
|
|
|
|
GU ܰ
|
GU ܰ
|
o
|
o
|
GU ܰ
|
GU ܰ
|
n GU ܰ
|
n GU ܰ
|
m
|
m
|
|
|
GU ܰ
|
GU ܰ
|
l
|
l
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
k GU 0
|
k GU 0
|
|
|
|
|
|
|
|
|
GU 0
|
GU 0
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
GU ܰ
|
GU ܰ
|
GU ܰ
|
GU ܰ
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
|
|
|
|
GU ܰ
|
GU ܰ
|
|
|
GC:/sb/opencores/System09/src/sys09bug/sys09xes.vhd
|
GC:/sb/opencores/System09/src/sys09bug/sys09xes.vhd
|
t
|
t
|
876543 d g< 7
|
876543 d g< 7
|
5 3
8 6 4
|
5 3
8 6 4
|
|
|
|
|
|
|
|
|
|
|
GU c
|
GU c
|
|
|
|
|
|
|
|
|
3 & ' GU c 3
GU c 3 GU c
|
3 & ' GU c 3
GU c 3 GU c
|
|
|
|
|
|
|
4 & ' GU c
|
4 & ' GU c
|
|
|
GU c
|
GU c
|
GU c
|
GU c
|
|
|
|
|
|
|
|
|
GU c
|
GU c
|
|
|
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|
GU c
|
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|
|
|
GU c
|
GU c
|
|
|
}
|
}
|
|
|
|
|
5 & ' GU c r
|
5 & ' GU c r
|
|
|
6 & ' GU c
|
6 & ' GU c
|
o
|
o
|
GU c
|
GU c
|
n GU c
|
n GU c
|
m
|
m
|
|
|
GU c
|
GU c
|
l
|
l
|
|
|
|
|
GU c
|
GU c
|
|
|
k GU c
|
k GU c
|
|
|
|
|
|
|
7 & ' GU c
|
7 & ' GU c
|
|
|
8 & ' GU c
|
8 & ' GU c
|
|
|
GU c
|
GU c
|
GU c
|
GU c
|
|
|
|
|
GU c
|
GU c
|
|
|
|
|
|
|
GU c
|
GU c
|
|
|
e g<
|
e g<
|
|
|
|
|
|
|
|
|
|
|
|
|
GU c
|
GU c
|
|
|
|
|
|
|
|
|
G~
G~ GU c
|
G~
G~ GU c
|
|
|
|
|
|
|
G~
|
G~
|
|
|
G~
|
G~
|
G~
|
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|
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|
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|
G~
|
G~
|
|
|
|
|
GU c
|
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|
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|
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|
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|
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|
}
|
}
|
|
|
|
|
GU c r
|
GU c r
|
|
|
GU c
|
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|
o
|
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|
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|
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|
n G~
|
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|
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|
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|
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|
G~
|
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|
l
|
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|
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|
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|
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k GU c
|
k GU c
|
|
|
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|
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|
GU c
|
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|
|
|
GU c
|
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|
|
|
GU c
|
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|
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|
GU c
|
|
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|
GU c
|
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|
|
|
|
|
|
|
GU c
|
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|
|
|
^ g<
|
^ g<
|
|
|
|
|
|
|
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|
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|
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|
GU c
|
GU c
|
|
|
|
|
|
|
|
|
G~
G~ GU c
|
G~
G~ GU c
|
|
|
|
|
|
|
G~
|
G~
|
|
|
G~
|
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|
G~
|
G~
|
|
|
|
|
|
|
|
|
G~
|
G~
|
|
|
|
|
GU %
|
GU %
|
|
|
GU c
|
GU c
|
|
|
}
|
}
|
|
|
|
|
GU c r
|
GU c r
|
|
|
GU %
|
GU %
|
o
|
o
|
GU %
|
GU %
|
n G~
|
n G~
|
m
|
m
|
|
|
G~
|
G~
|
l
|
l
|
|
|
|
|
GU %
|
GU %
|
|
|
k GU c
|
k GU c
|
|
|
|
|
|
|
GU c
|
GU c
|
|
|
GU %
|
GU %
|
|
|
GU %
|
GU %
|
GU %
|
GU %
|
|
|
|
|
GU %
|
GU %
|
|
|
|
|
|
|
GU %
|
GU %
|
|
|
G\ {C:/sb/opencores/System09/rtl/VHDL/trap.vhd
|
G\ {C:/sb/opencores/System09/rtl/VHDL/trap.vhd
|
t
|
t
|
/. d g< . /
|
/. d g< . /
|
|
|
|
|
GU % D
|
GU % D
|
|
|
. & ' GU % 7
|
. & ' GU % 7
|
|
|
/ & ' GU
|
/ & ' GU
|
|
|
4
|
4
|
|
|
|
|
GU
|
GU
|
|
|
3
|
3
|
|
|
|
|
GU
|
GU
|
|
|
2
|
2
|
wv ^ g< v w
|
wv ^ g< v w
|
|
|
|
|
|
|
GU % D
|
GU % D
|
|
|
v
GU % 7
|
v
GU % 7
|
|
|
w Gx
|
w Gx
|
|
|
4
|
4
|
|
|
|
|
Gx
|
Gx
|
|
|
3
|
3
|
|
|
|
|
Gx
|
Gx
|
|
|
2 e g<
|
2 e g<
|
|
|
|
|
GU % D
|
GU % D
|
|
|
GU % 7
|
GU % 7
|
|
|
Gx
|
Gx
|
|
|
4
|
4
|
|
|
|
|
Gx
|
Gx
|
|
|
3
|
3
|
|
|
|
|
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|
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|
|
|
2 G\ {C:/sb/opencores/System09/rtl/VHDL/vdu8.vhd
|
2 G\ {C:/sb/opencores/System09/rtl/VHDL/vdu8.vhd
|
t
|
t
|
!10 d g< 0 " # $ 1
|
!10 d g< 0 " # $ 1
|
|
|
|
|
! GU
$#" ! > % !
|
! GU
$#" ! > % !
|
|
|
|
|
0 & ' & GU
0 " " # GU
0 $ $ # GU
0 % % & GU
|
0 & ' & GU
0 " " # GU
0 $ $ # GU
0 % % & GU
|
'
|
'
|
|
|
|
|
1 & ' ( GU
|
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|
|
|
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|
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|
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|
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|
|
|
|
|
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|
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|
|
|
|
|
|
|
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|
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|
|
|
)*+,-sr ^ g< r . / 0 s
|
)*+,-sr ^ g< r . / 0 s
|
, +
|
, +
|
*
|
*
|
- GU
0/. ! > 1 !
|
- GU
0/. ! > 1 !
|
|
|
|
|
r 2 Gx W0 r " " # Gx W0 r $ $ # Gx W0 r % % & GU
|
r 2 Gx W0 r " " # Gx W0 r $ $ # Gx W0 r % % & GU
|
3
|
3
|
|
|
|
|
s 4 Gx
|
s 4 Gx
|
|
|
Gx
|
Gx
|
Gx '
|
Gx '
|
|
|
|
|
Gx
|
Gx
|
|
|
|
|
|
|
GU
|
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|
|
|
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|
56789 e g< : ; <
|
8 7
|
8 7
|
6
|
6
|
9 GU
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|
9 GU
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|
|
|
|
|
> ? Gx " " # Gx $ $ # Gx % % & GU
|
> ? Gx " " # Gx $ $ # Gx % % & GU
|
@
|
@
|
|
|
|
|
A B Gx
|
A B Gx
|
|
|
Gx
|
Gx
|
Gx '
|
Gx '
|
|
|
|
|
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|
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|
|
|
|
|
|
|
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|
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|
|
|
CDE ( GڟKC:/sb/opencores/System09/rtl/Spartan3/char_rom2k_b16.vhd
|
CDE ( GڟKC:/sb/opencores/System09/rtl/Spartan3/char_rom2k_b16.vhd
|
tF
|
tF
|
GHIJK $ d g< )$ *
|
GHIJK $ d g< )$ *
|
J
|
J
|
H
|
H
|
I
|
I
|
K GU
m E
|
K GU
m E
|
) L
|
) L
|
&
|
&
|
|
|
$ & ' M GU
m E & * N &
|
$ & ' M GU
m E & * N &
|
|
|
& ' O GU
m E
|
& ' O GU
m E
|
|
|
GU
m E
|
GU
m E
|
GU
m E
|
GU
m E
|
|
|
|
|
|
|
|
|
GU
m E
|
GU
m E
|
|
|
|
|
GU
m E
|
GU
m E
|
|
|
PQRSTut ^ g< )t *u
|
PQRSTut ^ g< )t *u
|
S
|
S
|
Q
|
Q
|
R
|
R
|
T GU
m D
|
T GU
m D
|
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|
) U
|
&
|
&
|
|
|
t V GU
m D & * W &
|
t V GU
m D & * W &
|
|
|
u X Gx D
|
u X Gx D
|
|
|
Gx D
|
Gx D
|
Gx D
|
Gx D
|
|
|
|
|
|
|
|
|
Gx D
|
Gx D
|
|
|
|
|
GU
m D
|
GU
m D
|
|
|
YZ[\] e g< ) *
|
YZ[\] e g< ) *
|
\
|
\
|
Z
|
Z
|
[
|
[
|
] GU
m C
|
] GU
m C
|
) ^
|
) ^
|
&
|
&
|
|
|
_ ` GU
m C & * a &
|
_ ` GU
m C & * a &
|
|
|
b c Gx C
|
b c Gx C
|
|
|
Gx C
|
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|
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|
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|
|
|
|
|
|
|
|
|
Gx C
|
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|
|
|
|
|
GU
m C
|
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|
|
|
def + G\ {C:/sb/opencores/System09/rtl/VHDL/ps2_keyboard.vhd
|
def + G\ {C:/sb/opencores/System09/rtl/VHDL/ps2_keyboard.vhd
|
tg
|
tg
|
hijkl*) d g< ,) -m .*
|
hijkl*) d g< ,) -m .*
|
h
|
h
|
j
|
j
|
k
|
k
|
l
|
l
|
i GU
2 f m
|
i GU
2 f m
|
, n
|
, n
|
/
|
/
|
|
|
) & ' o GU
2 ) 0 - 0 1 GU
2 f / . p /
|
) & ' o GU
2 ) 0 - 0 1 GU
2 f / . p /
|
|
|
* & ' q GU
2 f
|
* & ' q GU
2 f
|
|
|
|
|
|
|
|
|
|
|
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2 f
|
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2 f
|
|
|
{
|
{
|
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|
|
|
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2 f
|
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2 f
|
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|
z
|
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|
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|
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2 f
|
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|
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|
y
|
y
|
|
|
|
|
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|
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|
|
|
x rstuv_b ^ g< ,b -w ._
|
x rstuv_b ^ g< ,b -w ._
|
r
|
r
|
t
|
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|
u
|
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|
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|
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|
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|
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|
, x
|
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|
/
|
/
|
|
|
b y Gx a b 0 - 0 1 GU
2 e / . z /
|
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|
|
|
_ { Gx a e
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
|
x |}~ e g< , - .
|
x |}~ e g< , - .
|
|
|
|
|
~
|
~
|
|
|
|
|
} GU
2 d
|
} GU
2 d
|
,
|
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|
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|
/
|
|
|
Gx a 0 - 0 1 GU
2 d / . /
|
Gx a 0 - 0 1 GU
2 d / . /
|
|
|
Gx a d
|
Gx a d
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
{
|
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|
|
|
|
|
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|
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|
|
|
z
|
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|
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|
|
Gx a d
|
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|
|
|
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|
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|
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|
|
|
Gx a d
|
Gx a d
|
|
|
x 2 GkXSA-3S1000.ucf 3 4
+ d g< 5+ GU h 6 5 6 7
|
x 2 GkXSA-3S1000.ucf 3 4
+ d g< 5+ GU h 6 5 6 7
|
+ & '
^ g< 5 GU h 6 5 6 7
|
+ & '
^ g< 5 GU h 6 5 6 7
|
e g< 5 GU h 6 5 6 7
|
e g< 5 GU h 6 5 6 7
|
( 8 G\ wC:/sb/opencores/System09/rtl/Spartan3/ram2k_b16.vhd
|
( 8 G\ wC:/sb/opencores/System09/rtl/Spartan3/ram2k_b16.vhd
|
t
|
t
|
-, d g< 9, :-
|
-, d g< 9, :-
|
|
|
|
|
|
|
GU
|
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|
9
|
9
|
#
|
#
|
|
|
, & ' GU # : #
|
, & ' GU # : #
|
|
|
- & ' GU
|
- & ' GU
|
|
|
GU
|
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|
GU
|
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|
|
|
|
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|
|
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|
GU
|
GU
|
|
|
|
|
GU
|
GU
|
|
|
kj ^ g< 9j :k
|
kj ^ g< 9j :k
|
|
|
|
|
|
|
GU
|
GU
|
9
|
9
|
#
|
#
|
|
|
j GU # : #
|
j GU # : #
|
|
|
k Gx x
|
k Gx x
|
|
|
Gx x
|
Gx x
|
Gx x
|
Gx x
|
|
|
|
|
|
|
|
|
Gx x
|
Gx x
|
|
|
|
|
GU
|
GU
|
|
|
e g< 9 :
|
e g< 9 :
|
|
|
|
|
|
|
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|
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|
9
|
9
|
#
|
#
|
|
|
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|
GU # : #
|
|
|
Gx x
|
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|
|
|
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|
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|
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|
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|
|
|
|
|
|
|
|
Gx x
|
Gx x
|
|
|
|
|
GU
|
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|
|
|
; G\ wC:/sb/opencores/System09/rtl/Spartan3/keymap_rom_slice.vhd
|
; G\ wC:/sb/opencores/System09/rtl/Spartan3/keymap_rom_slice.vhd
|
t
|
t
|
#" d g< <" =#
|
#" d g< <" =#
|
|
|
>
|
>
|
GU {P
|
GU {P
|
<
|
<
|
1
|
1
|
|
|
" & ' GU {P 1 = 1
|
" & ' GU {P 1 = 1
|
|
|
# & ' GU {P
|
# & ' GU {P
|
|
|
|
|
|
|
|
|
GU {P ? >
|
GU {P ? >
|
|
|
GU {P
|
GU {P
|
|
|
|
|
|
|
|
|
GU {P
|
GU {P
|
|
|
qp ^ g< <p =q
|
qp ^ g< <p =q
|
|
|
>
|
>
|
GU {P
|
GU {P
|
<
|
<
|
1
|
1
|
|
|
p GU {P 1 = 1
|
p GU {P 1 = 1
|
|
|
q Gx >8
|
q Gx >8
|
|
|
|
|
|
|
|
|
Gx >8 ? >
|
Gx >8 ? >
|
|
|
Gx >8
|
Gx >8
|
|
|
|
|
|
|
|
|
Gx >8
|
Gx >8
|
|
|
e g< < =
|
e g< < =
|
|
|
>
|
>
|
GU {P
|
GU {P
|
<
|
<
|
1
|
1
|
|
|
GU {P 1 = 1
|
GU {P 1 = 1
|
|
|
Gx >8
|
Gx >8
|
|
|
|
|
|
|
|
|
Gx >8 ? >
|
Gx >8 ? >
|
|
|
Gx >8
|
Gx >8
|
|
|
|
|
|
|
|
|
Gx >8
|
Gx >8
|
|
|
@ G\ {C:/sb/opencores/System09/rtl/VHDL/keyboard.vhd
|
@ G\ {C:/sb/opencores/System09/rtl/VHDL/keyboard.vhd
|
t
|
t
|
&% d g< A% B C&
|
&% d g< A% B C&
|
|
|
|
|
|
|
|
|
GU {P
|
GU {P
|
A '
|
A '
|
|
|
|
|
|
|
% & ' GU < % D B N D / GU {P
|
% & ' GU < % D B N D / GU {P
|
C
|
C
|
|
|
|
|
& & ' GU <
|
& & ' GU <
|
|
|
|
|
|
|
|
|
GU <
|
GU <
|
|
|
|
|
|
|
|
|
GU <
|
GU <
|
|
|
|
|
|
|
|
|
GU <
|
GU <
|
|
|
|
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|
|
|
|
GU <
|
GU <
|
|
|
ml ^ g< Al B Cm
|
ml ^ g< Al B Cm
|
|
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|
|
|
|
|
|
GU <
|
GU <
|
A '
|
A '
|
|
|
|
|
|
|
l Gx l D B N D / GU <
|
l Gx l D B N D / GU <
|
C
|
C
|
|
|
|
|
m Gx
|
m Gx
|
|
|
|
|
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|
Gx
|
Gx
|
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|
|
|
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|
|
|
Gx
|
Gx
|
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|
|
|
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|
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|
Gx
|
Gx
|
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|
|
|
|
|
Gx
|
Gx
|
|
|
e g< A B C
|
e g< A B C
|
|
|
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|
GU <
|
GU <
|
A '
|
A '
|
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|
Gx D B N D / GU <
|
Gx D B N D / GU <
|
C
|
C
|
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|
Gx
|
Gx
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Gx
|
Gx
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|
Gx
|
Gx
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|
Gx
|
Gx
|
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|
|
Gx
|
Gx
|
|
|
E G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_TX.vhd
|
E G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_TX.vhd
|
t
|
t
|
(' d g< F' G(
|
(' d g< F' G(
|
|
|
|
|
|
|
GU <
|
GU <
|
F A
|
F A
|
H
|
H
|
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|
' & ' GU < H G 1 H
|
' & ' GU < H G 1 H
|
|
|
( & ' GU P
|
( & ' GU P
|
|
|
+
|
+
|
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|
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|
GU P
|
GU P
|
|
|
*
|
*
|
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|
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|
GU P
|
GU P
|
|
|
)
|
)
|
|
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|
GU P
|
GU P
|
|
|
( on ^ g< Fn Go
|
( on ^ g< Fn Go
|
|
|
|
|
|
|
GU <
|
GU <
|
F A
|
F A
|
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|
H
|
H
|
|
|
n GU < H G 1 H
|
n GU < H G 1 H
|
|
|
o
Gx
|
o
Gx
|
|
|
+
|
+
|
|
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|
Gx
|
Gx
|
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|
*
|
*
|
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|
Gx
|
Gx
|
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|
)
|
)
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|
Gx
|
Gx
|
|
|
( e g< F G
|
( e g< F G
|
|
|
|
|
|
|
GU P
|
GU P
|
F A
|
F A
|
H
|
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|
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|
GU P H G 1 H
|
GU P H G 1 H
|
|
|
Gx
|
Gx
|
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+
|
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|
Gx
|
Gx
|
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|
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|
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|
Gx
|
Gx
|
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|
)
|
)
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|
Gx
|
Gx
|
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|
( I G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_Clock.vhd
|
( I G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_Clock.vhd
|
t
|
t
|
! !"# $%&'()*+, d g< J K
|
! !"# $%&'()*+, d g< J K
|
+ L M!
|
+ L M!
|
&
|
&
|
'
|
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|
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|
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|
" N#
|
" N#
|
(
|
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|
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|
%
|
* O, GU ø
|
* O, GU ø
|
J = -
|
J = -
|
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|
& ' . GU ø
|
& ' . GU ø
|
K 0 /
|
K 0 /
|
|
|
|
|
& ' 0 GU ø P O - Q
|
& ' 0 GU ø P O - Q
|
GU ø
|
GU ø
|
, GU ø
|
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|
+
|
+
|
GU ø
|
GU ø
|
* GU ø
|
* GU ø
|
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|
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|
)
|
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|
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|
GU ø
|
GU ø
|
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|
(
|
(
|
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|
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|
GU ø
|
GU ø
|
|
|
'
|
'
|
|
|
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|
GU ø
|
GU ø
|
|
|
&
|
&
|
|
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|
GU ø
|
GU ø
|
|
|
% GU ø Q L 1 2 Q 3 R
|
% GU ø Q L 1 2 Q 3 R
|
& ' 4 GU ø S N
|
& ' 4 GU ø S N
|
|
|
|
|
GU ø
|
GU ø
|
|
|
|
|
GU ø
|
GU ø
|
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|
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|
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|
GU ø
|
GU ø
|
|
|
GU ø @ Q M 5 6 Q 7 T
|
GU ø @ Q M 5 6 Q 7 T
|
! & ' 8 GU ø S N
|
! & ' 8 GU ø S N
|
|
|
|
|
|
|
GU ø
|
GU ø
|
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|
GU ø
|
GU ø
|
|
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|
|
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|
GU ø
|
GU ø
|
|
|
9:;<]=>?@^ABCDEFGHI`a ^ g< Ja K`
|
9:;<]=>?@^ABCDEFGHI`a ^ g< Ja K`
|
H L^ M]
|
H L^ M]
|
C
|
C
|
D
|
D
|
>
|
>
|
? N@
|
? N@
|
E
|
E
|
B
|
B
|
G OI GU ø
|
G OI GU ø
|
J = J
|
J = J
|
|
|
|
|
|
|
a K GU ø
|
a K GU ø
|
K 0 L
|
K 0 L
|
|
|
|
|
` M Gx
P O - Q
|
` M Gx
P O - Q
|
Gx
|
Gx
|
, Gx
|
, Gx
|
+
|
+
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GU ø
|
GU ø
|
* Gx
|
* Gx
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|
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|
|
Gx
|
Gx
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|
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|
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|
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|
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Gx
|
Gx
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|
&
|
&
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|
|
|
|
GU ø
|
GU ø
|
|
|
% GU ø Q L 1 N Q 3 R
|
% GU ø Q L 1 N Q 3 R
|
^ O Gx
S N
|
^ O Gx
S N
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|
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|
|
Gx
|
Gx
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|
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|
|
Gx
|
Gx
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|
GU ø
|
GU ø
|
|
|
GU ø @ Q M 5 P Q 7 T
|
GU ø @ Q M 5 P Q 7 T
|
] Q GU ø S N
|
] Q GU ø S N
|
|
|
|
|
|
|
GU ø
|
GU ø
|
|
|
|
|
GU ø
|
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|
|
|
|
|
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|
GU ø
|
GU ø
|
|
|
RSTUVWXYZ[\]^_`ab e g< J K
|
RSTUVWXYZ[\]^_`ab e g< J K
|
a L M
|
a L M
|
\
|
\
|
]
|
]
|
W
|
W
|
X NY
|
X NY
|
^
|
^
|
[
|
[
|
` Ob GU ø
|
` Ob GU ø
|
J = c
|
J = c
|
|
|
|
|
|
|
d e GU ø
|
d e GU ø
|
K 0 f
|
K 0 f
|
|
|
|
|
g h Gx
P O - Q
|
g h Gx
P O - Q
|
Gx
|
Gx
|
, Gx
|
, Gx
|
+
|
+
|
GU ø
|
GU ø
|
* Gx
|
* Gx
|
|
|
)
|
)
|
|
|
|
|
Gx
|
Gx
|
|
|
(
|
(
|
|
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|
|
Gx
|
Gx
|
|
|
'
|
'
|
|
|
|
|
Gx
|
Gx
|
|
|
&
|
&
|
|
|
|
|
GU ø
|
GU ø
|
|
|
% GU ø Q L 1 i Q 3 R
|
% GU ø Q L 1 i Q 3 R
|
j k Gx
S N
|
j k Gx
S N
|
|
|
|
|
Gx
|
Gx
|
|
|
|
|
Gx
|
Gx
|
|
|
|
|
|
|
GU ø
|
GU ø
|
|
|
GU ø @ Q M 5 l Q 7 T
|
GU ø @ Q M 5 l Q 7 T
|
m n GU ø S N
|
m n GU ø S N
|
|
|
|
|
|
|
GU ø
|
GU ø
|
|
|
|
|
GU ø
|
GU ø
|
|
|
|
|
|
|
GU ø
|
GU ø
|
|
|
opq U G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_6850.vhd
|
opq U G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_6850.vhd
|
tr
|
tr
|
stuF d g< V Wv Xw YF
|
stuF d g< V Wv Xw YF
|
s
|
s
|
u
|
u
|
t GU 8 q vw
|
t GU 8 q vw
|
V Y x
|
V Y x
|
|
|
|
|
|
|
& ' y GU 8 Z X Z H GU 8 [ W [ \ GU 8 q
|
& ' y GU 8 Z X Z H GU 8 [ W [ \ GU 8 q
|
Y = z
|
Y = z
|
|
|
|
|
F & ' { GU 8 q
|
F & ' { GU 8 q
|
|
|
4
|
4
|
|
|
|
|
GU 8 q
|
GU 8 q
|
|
|
3
|
3
|
|
|
|
|
GU 8 q
|
GU 8 q
|
|
|
2 |}~ed ^ g< Vd W X Ye
|
2 |}~ed ^ g< Vd W X Ye
|
|
|
|
|
~
|
~
|
} GU 8 p
|
} GU 8 p
|
V Y
|
V Y
|
|
|
|
|
|
|
d Gx d Z X Z H Gx d [ W [ \ GU 8 p
|
d Gx d Z X Z H Gx d [ W [ \ GU 8 p
|
Y =
|
Y =
|
|
|
|
|
e Gx p
|
e Gx p
|
|
|
4
|
4
|
|
|
|
|
Gx p
|
Gx p
|
|
|
3
|
3
|
|
|
|
|
Gx p
|
Gx p
|
|
|
2 e g< V W X Y
|
2 e g< V W X Y
|
|
|
|
|
GU 8 o
|
GU 8 o
|
V Y
|
V Y
|
|
|
|
|
|
|
Gx Z X Z H Gx [ W [ \ GU 8 o
|
Gx Z X Z H Gx [ W [ \ GU 8 o
|
Y =
|
Y =
|
|
|
|
|
Gx o
|
Gx o
|
|
|
4
|
4
|
|
|
|
|
Gx o
|
Gx o
|
|
|
3
|
3
|
|
|
|
|
Gx o
|
Gx o
|
|
|
2 ] G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_RX.vhd
|
2 ] G\ {C:/sb/opencores/System09/rtl/VHDL/ACIA_RX.vhd
|
t
|
t
|
|
|
|
|
d g< ^ _
|
d g< ^ _
|
|
|
|
|
|
|
GU J
|
GU J
|
^ L
|
^ L
|
\
|
\
|
|
|
& ' GU J \ _ 8 \
|
& ' GU J \ _ 8 \
|
|
|
& ' GU
|
& ' GU
|
|
|
0
|
0
|
|
|
|
|
GU
|
GU
|
|
|
/
|
/
|
|
|
|
|
GU
|
GU
|
|
|
.
|
.
|
|
|
|
|
GU
|
GU
|
|
|
-
|
-
|
gf ^ g< ^f _g
|
gf ^ g< ^f _g
|
|
|
|
|
|
|
GU J
|
GU J
|
^ L
|
^ L
|
\
|
\
|
|
|
f GU J \ _ 8 \
|
f GU J \ _ 8 \
|
|
|
g Gx )
|
g Gx )
|
|
|
0
|
0
|
|
|
|
|
Gx )
|
Gx )
|
|
|
/
|
/
|
|
|
|
|
Gx )
|
Gx )
|
|
|
.
|
.
|
|
|
|
|
Gx )
|
Gx )
|
|
|
-
|
-
|
e g< ^ _
|
e g< ^ _
|
|
|
|
|
|
|
GU J
|
GU J
|
^ L
|
^ L
|
\
|
\
|
|
|
GU J \ _ 8 \
|
GU J \ _ 8 \
|
|
|
Gx
|
Gx
|
|
|
0
|
0
|
|
|
|
|
Gx
|
Gx
|
|
|
/
|
/
|
|
|
|
|
Gx
|
Gx
|
|
|
.
|
.
|
|
|
|
|
Gx
|
Gx
|
|
|
- ` GڟNC:/sb/opencores/System09/rtl/VHDL/timer.vhd
|
- ` GڟNC:/sb/opencores/System09/rtl/VHDL/timer.vhd
|
t
|
t
|
GH d g< aH bG
|
GH d g< aH bG
|
|
|
|
|
GU
|
GU
|
a O
|
a O
|
c
|
c
|
|
|
H & ' GU c b C c
|
H & ' GU c b C c
|
|
|
G & ' GU
|
G & ' GU
|
|
|
@
|
@
|
|
|
|
|
GU
|
GU
|
|
|
?
|
?
|
|
|
|
|
GU
|
GU
|
|
|
> ih ^ g< ah bi
|
> ih ^ g< ah bi
|
|
|
|
|
GU
|
GU
|
a O
|
a O
|
c
|
c
|
|
|
h GU c b C c
|
h GU c b C c
|
|
|
i Gx @
|
i Gx @
|
|
|
@
|
@
|
|
|
|
|
Gx @
|
Gx @
|
|
|
?
|
?
|
|
|
|
|
Gx @
|
Gx @
|
|
|
> e g< a b
|
> e g< a b
|
|
|
|
|
GU
|
GU
|
a O
|
a O
|
c
|
c
|
|
|
GU c b C c
|
GU c b C c
|
|
|
Gx @
|
Gx @
|
|
|
@
|
@
|
|
|
|
|
Gx @
|
Gx @
|
|
|
?
|
?
|
|
|
|
|
Gx @
|
Gx @
|
|
|
> d GڟNC:/sb/opencores/System09/rtl/VHDL/cpu09.vhd
|
> d GڟNC:/sb/opencores/System09/rtl/VHDL/cpu09.vhd
|
t
|
t
|
d g< e f
|
d g< e f
|
|
|
|
|
GU
|
GU
|
͠
|
͠
|
e
|
e
|
|
|
|
|
|
|
& ' GU
|
& ' GU
|
͠
|
͠
|
f
|
f
|
|
|
|
|
& ' GU
|
& ' GU
|
|
|
|
|
|
|
|
|
GU
|
GU
|
|
|
|
|
|
|
|
|
GU
|
GU
|
|
|
c ^ g< ec f
|
c ^ g< ec f
|
|
|
|
|
GU
|
GU
|
͠
|
͠
|
e
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7 __OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl work verilog System09 simprim vcomponents unisim AND2B1|unisim|vcomponents AND2B2|unisim|vcomponents AND2|unisim|vcomponents AND3B1|unisim|vcomponents AND3B2|unisim|vcomponents AND3B3|unisim|vcomponents AND3|unisim|vcomponents AND4B1|unisim|vcomponents AND4B2|unisim|vcomponents AND4B3|unisim|vcomponents AND4B4|unisim|vcomponents AND4|unisim|vcomponents AND5B1|unisim|vcomponents AND5B2|unisim|vcomponents AND5B3|unisim|vcomponents AND5B4|unisim|vcomponents AND5B5|unisim|vcomponents AND5|unisim|vcomponents AND6|unisim|vcomponents AND7|unisim|vcomponents AND8|unisim|vcomponents BSCAN_FPGACORE|unisim|vcomponents BSCAN_SPARTAN2|unisim|vcomponents BSCAN_SPARTAN3A|unisim|vcomponents BSCAN_SPARTAN3|unisim|vcomponents BSCAN_VIRTEX2|unisim|vcomponents BSCAN_VIRTEX4|unisim|vcomponents BSCAN_VIRTEX5|unisim|vcomponents BSCAN_VIRTEX|unisim|vcomponents BUFCF|unisim|vcomponents BUFE|unisim|vcomponents BUFFOE|unisim|vcomponents BUFGCE_1|unisim|vcomponents BUFGCE|unisim|vcomponents BUFGCTRL|unisim|vcomponents BUFGDLL|unisim|vcomponents BUFGMUX_1|unisim|vcomponents BUFGMUX_CTRL|unisim|vcomponents BUFGMUX_VIRTEX4|unisim|vcomponents BUFGMUX|unisim|vcomponents BUFGP|unisim|vcomponents BUFGSR|unisim|vcomponents BUFGTS|unisim|vcomponents BUFG|unisim|vcomponents BUFIO|unisim|vcomponents BUFR|unisim|vcomponents BUFT|unisim|vcomponents BUF|unisim|vcomponents CAPTURE_FPGACORE|unisim|vcomponents CAPTURE_SPARTAN2|unisim|vcomponents CAPTURE_SPARTAN3A|unisim|vcomponents CAPTURE_SPARTAN3|unisim|vcomponents CAPTURE_VIRTEX2|unisim|vcomponents CAPTURE_VIRTEX4|unisim|vcomponents CAPTURE_VIRTEX5|unisim|vcomponents CAPTURE_VIRTEX|unisim|vcomponents CARRY4|unisim|vcomponents CFGLUT5|unisim|vcomponents CLKDLLE|unisim|vcomponents CLKDLLHF|unisim|vcomponents CLKDLL|unisim|vcomponents CLK_DIV10RSD|unisim|vcomponents CLK_DIV10R|unisim|vcomponents CLK_DIV10SD|unisim|vcomponents CLK_DIV10|unisim|vcomponents CLK_DIV12RSD|unisim|vcomponents CLK_DIV12R|unisim|vcomponents CLK_DIV12SD|unisim|vcomponents CLK_DIV12|unisim|vcomponents CLK_DIV14RSD|unisim|vcomponents CLK_DIV14R|unisim|vcomponents CLK_DIV14SD|unisim|vcomponents CLK_DIV14|unisim|vcomponents CLK_DIV16RSD|unisim|vcomponents CLK_DIV16R|unisim|vcomponents CLK_DIV16SD|unisim|vcomponents CLK_DIV16|unisim|vcomponents CLK_DIV2RSD|unisim|vcomponents CLK_DIV2R|unisim|vcomponents CLK_DIV2SD|unisim|vcomponents CLK_DIV2|unisim|vcomponents CLK_DIV4RSD|unisim|vcomponents CLK_DIV4R|unisim|vcomponents CLK_DIV4SD|unisim|vcomponents CLK_DIV4|unisim|vcomponents CLK_DIV6RSD|unisim|vcomponents CLK_DIV6R|unisim|vcomponents CLK_DIV6SD|unisim|vcomponents CLK_DIV6|unisim|vcomponents CLK_DIV8RSD|unisim|vcomponents CLK_DIV8R|unisim|vcomponents CLK_DIV8SD|unisim|vcomponents CLK_DIV8|unisim|vcomponents CONFIG|unisim|vcomponents CRC32|unisim|vcomponents CRC64|unisim|vcomponents DCC_FPGACORE|unisim|vcomponents DCIRESET|unisim|vcomponents DCM_ADV|unisim|vcomponents DCM_BASE|unisim|vcomponents DCM_PS|unisim|vcomponents DCM_SP|unisim|vcomponents DCM|unisim|vcomponents DNA_PORT|unisim|vcomponents DSP48A|unisim|vcomponents DSP48E|unisim|vcomponents DSP48|unisim|vcomponents EMAC|unisim|vcomponents FDCE_1|unisim|vcomponents FDCE|unisim|vcomponents FDCPE_1|unisim|vcomponents FDCPE|unisim|vcomponents FDCPX1|unisim|vcomponents FDCP_1|unisim|vcomponents FDCP|unisim|vcomponents FDC_1|unisim|vcomponents FDC|unisim|vcomponents FDDCE|unisim|vcomponents FDDCPE|unisim|vcomponents FDDCP|unisim|vcomponents FDDC|unisim|vcomponents FDDPE|unisim|vcomponents FDDP|unisim|vcomponents FDDRCPE|unisim|vcomponents FDDRRSE|unisim|vcomponents FDD|unisim|vcomponents FDE_1|unisim|vcomponents FDE|unisim|vcomponents FDPE_1|unisim|vcomponents FDPE|unisim|vcomponents FDP_1|unisim|vcomponents FDP|unisim|vcomponents FDRE_1|unisim|vcomponents FDRE|unisim|vcomponents FDRSE_1|unisim|vcomponents FDRSE|unisim|vcomponents FDRS_1|unisim|vcomponents FDRS|unisim|vcomponents FDR_1|unisim|vcomponents FDR|unisim|vcomponents FDSE_1|unisim|vcomponents FDSE|unisim|vcomponents FDS_1|unisim|vcomponents FDS|unisim|vcomponents FD_1|unisim|vcomponents FD|unisim|vcomponents FIFO16|unisim|vcomponents FIFO18_36|unisim|vcomponents FIFO18|unisim|vcomponents FIFO36_72_EXP|unisim|vcomponents FIFO36_72|unisim|vcomponents FIFO36_EXP|unisim|vcomponents FIFO36|unisim|vcomponents FMAP|unisim|vcomponents FRAME_ECC_VIRTEX4|unisim|vcomponents FRAME_ECC_VIRTEX5|unisim|vcomponents FTCP|unisim|vcomponents FTC|unisim|vcomponents FTP|unisim|vcomponents GND|unisim|vcomponents GT10_10GE_4|unisim|vcomponents GT10_10GE_8|unisim|vcomponents GT10_10GFC_4|unisim|vcomponents GT10_10GFC_8|unisim|vcomponents GT10_AURORAX_4|unisim|vcomponents GT10_AURORAX_8|unisim|vcomponents GT10_AURORA_1|unisim|vcomponents GT10_AURORA_2|unisim|vcomponents GT10_AURORA_4|unisim|vcomponents GT10_CUSTOM|unisim|vcomponents GT10_INFINIBAND_1|unisim|vcomponents GT10_INFINIBAND_2|unisim|vcomponents GT10_INFINIBAND_4|unisim|vcomponents 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GT_XAUI_1|unisim|vcomponents GT_XAUI_2|unisim|vcomponents GT_XAUI_4|unisim|vcomponents GT|unisim|vcomponents IBUFDS_BLVDS_25|unisim|vcomponents IBUFDS_DIFF_OUT|unisim|vcomponents IBUFDS_DLY_ADJ|unisim|vcomponents IBUFDS_LDT_25|unisim|vcomponents IBUFDS_LVDSEXT_25_DCI|unisim|vcomponents IBUFDS_LVDSEXT_25|unisim|vcomponents IBUFDS_LVDSEXT_33_DCI|unisim|vcomponents IBUFDS_LVDSEXT_33|unisim|vcomponents IBUFDS_LVDS_25_DCI|unisim|vcomponents IBUFDS_LVDS_25|unisim|vcomponents IBUFDS_LVDS_33_DCI|unisim|vcomponents IBUFDS_LVDS_33|unisim|vcomponents IBUFDS_LVPECL_25|unisim|vcomponents IBUFDS_LVPECL_33|unisim|vcomponents IBUFDS_ULVDS_25|unisim|vcomponents IBUFDS|unisim|vcomponents IBUFGDS_BLVDS_25|unisim|vcomponents IBUFGDS_DIFF_OUT|unisim|vcomponents IBUFGDS_LDT_25|unisim|vcomponents IBUFGDS_LVDSEXT_25_DCI|unisim|vcomponents IBUFGDS_LVDSEXT_25|unisim|vcomponents IBUFGDS_LVDSEXT_33_DCI|unisim|vcomponents IBUFGDS_LVDSEXT_33|unisim|vcomponents IBUFGDS_LVDS_25_DCI|unisim|vcomponents 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|Architecture||my_computer|my_system09|| |ComponentInstantiation||my_system09|my_computer|my_ACIA_Clock|ACIA_Clock| |ComponentInstantiation||my_system09|my_computer|my_acia|ACIA_6850| |ComponentInstantiation||my_system09|my_computer|my_cpu|cpu09| |ComponentInstantiation||my_system09|my_computer|my_dat|dat_ram| |ComponentInstantiation||my_system09|my_computer|my_flex|flex_ram| |ComponentInstantiation||my_system09|my_computer|my_keyboard|keyboard| |ComponentInstantiation||my_system09|my_computer|my_rom|mon_rom| |ComponentInstantiation||my_system09|my_computer|my_seg|seven_segment| |ComponentInstantiation||my_system09|my_computer|my_vdu|vdu8| |Entity||my_system09 |Use||IEEE|STD_LOGIC_ARITH|all| |Use||IEEE|STD_LOGIC_UNSIGNED|all| |Use||ieee|numeric_std|all| my_computer my_seg my_vdu vdu8 my_keyboard keyboard my_ACIA_Clock ACIA_Clock my_acia ACIA_6850 my_dat dat_ram my_flex flex_ram my_rom mon_rom my_cpu cpu09 ieee.numeric_std.all numeric_std IEEE.STD_LOGIC_UNSIGNED.all IEEE STD_LOGIC_UNSIGNED IEEE.STD_LOGIC_ARITH.all STD_LOGIC_ARITH |File||C:/sb/opencores/System09/src/Flex9/flex9ide.vhd|PLUGIN_Vhdl|1207603951| |Architecture||rtl|FLEX9_C000|| |Architecture||rtl|FLEX9_C800|| |Architecture||rtl|FLEX9_D000|| |Architecture||rtl|FLEX9_D800|| |Architecture||rtl|flex_ram|| |ComponentInstantiation||flex_ram|rtl|addr_c000|FLEX9_C000| |ComponentInstantiation||flex_ram|rtl|addr_c800|FLEX9_C800| |ComponentInstantiation||flex_ram|rtl|addr_d000|FLEX9_D000| |ComponentInstantiation||flex_ram|rtl|addr_d800|FLEX9_D800| |Entity||FLEX9_C000 |Entity||FLEX9_C800 |Entity||FLEX9_D000 |Entity||FLEX9_D800 |Entity||flex_ram |Use||IEEE|STD_LOGIC_1164|all| |Use||IEEE|std_logic_1164|all| |Use||IEEE|std_logic_arith|all| |Use||unisim|vcomponents|all| addr_d800 FLEX9_D800 addr_d000 FLEX9_D000 addr_c800 FLEX9_C800 addr_c000 FLEX9_C000 unisim.vcomponents.all IEEE.STD_LOGIC_1164.all STD_LOGIC_1164 IEEE.std_logic_arith.all std_logic_arith IEEE.std_logic_1164.all |File||C:/sb/opencores/System09/src/sys09bug/sys09xes.vhd|PLUGIN_Vhdl|1207603951| |Architecture||rtl|SYS09BUG_F000|| |Architecture||rtl|SYS09BUG_F800|| |Architecture||rtl|mon_rom|| |ComponentInstantiation||mon_rom|rtl|addr_f000|SYS09BUG_F000| |ComponentInstantiation||mon_rom|rtl|addr_f800|SYS09BUG_F800| |Entity||SYS09BUG_F000 |Entity||SYS09BUG_F800 |Entity||mon_rom addr_f800 SYS09BUG_F800 addr_f000 SYS09BUG_F000 |File||C:/sb/opencores/System09/rtl/VHDL/trap.vhd|PLUGIN_Vhdl|1197219963| |Architecture||trap_arch|trap|| |Entity||trap trap_arch trap |File||C:/sb/opencores/System09/rtl/VHDL/vdu8.vhd|PLUGIN_Vhdl|1197219963| |Architecture||RTL|vdu8|| |ComponentInstantiation||vdu8|RTL|attr_buff_ram|ram_2k| |ComponentInstantiation||vdu8|RTL|char_buff_ram|ram_2k| |ComponentInstantiation||vdu8|RTL|vdu_char_rom|char_rom| |Entity||vdu8 |Use||IEEE|numeric_std|all| RTL attr_buff_ram ram_2k char_buff_ram vdu_char_rom char_rom IEEE.numeric_std.all |File||C:/sb/opencores/System09/rtl/Spartan3/char_rom2k_b16.vhd|PLUGIN_Vhdl|1205509963| |Architecture||rtl|char_rom|| |Entity||char_rom |File||C:/sb/opencores/System09/rtl/VHDL/ps2_keyboard.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ps2_keyboard_interface|| |ComponentInstantiation||ps2_keyboard_interface|rtl|my_key_map|keymap_rom| |Entity||ps2_keyboard_interface ps2_keyboard_interface my_key_map keymap_rom |File||C:/sb/opencores/System09/rtl/System09_Xilinx_ML506/XSA-3S1000.ucf|PLUGIN_AssocModule|1207593908| PLUGIN_AssocModule FILE_UCF |Module||XSA-3S1000.ucf XSA-3S1000.ucf DESUT_UCF |File||C:/sb/opencores/System09/rtl/Spartan3/ram2k_b16.vhd|PLUGIN_Vhdl|1197219959| |Architecture||rtl|ram_2k|| |Entity||ram_2k |File||C:/sb/opencores/System09/rtl/Spartan3/keymap_rom_slice.vhd|PLUGIN_Vhdl|1197219959| |Architecture||rtl|keymap_rom|| |Entity||keymap_rom |Use||ieee|std_logic_arith|all| ieee.std_logic_arith.all |File||C:/sb/opencores/System09/rtl/VHDL/keyboard.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|keyboard|| |ComponentInstantiation||keyboard|rtl|my_ps2_keyboard_interface|ps2_keyboard_interface| |Entity||keyboard my_ps2_keyboard_interface |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_TX.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_TX|| |Entity||ACIA_TX ACIA_TX |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_Clock.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_Clock|| |Entity||ACIA_Clock |PackageBody||bit_funcs| |PackageDecl||bit_funcs| |Use||IEEE|std_logic_unsigned|all| |Use||work|bit_funcs|all| work.bit_funcs.all bit_funcs DESUT_VHDL_PACKAGE_BODY IEEE.std_logic_unsigned.all DESUT_VHDL_PACKAGE_DECL |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_6850.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_6850|| |ComponentInstantiation||ACIA_6850|rtl|RxDev|ACIA_RX| |ComponentInstantiation||ACIA_6850|rtl|TxDev|ACIA_TX| |Entity||ACIA_6850 TxDev RxDev ACIA_RX |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_RX.vhd|PLUGIN_Vhdl|1197219963| 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|Architecture||my_computer|my_system09|| |ComponentInstantiation||my_system09|my_computer|my_ACIA_Clock|ACIA_Clock| |ComponentInstantiation||my_system09|my_computer|my_acia|ACIA_6850| |ComponentInstantiation||my_system09|my_computer|my_cpu|cpu09| |ComponentInstantiation||my_system09|my_computer|my_dat|dat_ram| |ComponentInstantiation||my_system09|my_computer|my_flex|flex_ram| |ComponentInstantiation||my_system09|my_computer|my_keyboard|keyboard| |ComponentInstantiation||my_system09|my_computer|my_rom|mon_rom| |ComponentInstantiation||my_system09|my_computer|my_seg|seven_segment| |ComponentInstantiation||my_system09|my_computer|my_vdu|vdu8| |Entity||my_system09 |Use||IEEE|STD_LOGIC_ARITH|all| |Use||IEEE|STD_LOGIC_UNSIGNED|all| |Use||ieee|numeric_std|all| my_computer my_seg my_vdu vdu8 my_keyboard keyboard my_ACIA_Clock ACIA_Clock my_acia ACIA_6850 my_dat dat_ram my_flex flex_ram my_rom mon_rom my_cpu cpu09 ieee.numeric_std.all numeric_std IEEE.STD_LOGIC_UNSIGNED.all IEEE STD_LOGIC_UNSIGNED IEEE.STD_LOGIC_ARITH.all STD_LOGIC_ARITH |File||C:/sb/opencores/System09/src/Flex9/flex9ide.vhd|PLUGIN_Vhdl|1207603951| |Architecture||rtl|FLEX9_C000|| |Architecture||rtl|FLEX9_C800|| |Architecture||rtl|FLEX9_D000|| |Architecture||rtl|FLEX9_D800|| |Architecture||rtl|flex_ram|| |ComponentInstantiation||flex_ram|rtl|addr_c000|FLEX9_C000| |ComponentInstantiation||flex_ram|rtl|addr_c800|FLEX9_C800| |ComponentInstantiation||flex_ram|rtl|addr_d000|FLEX9_D000| |ComponentInstantiation||flex_ram|rtl|addr_d800|FLEX9_D800| |Entity||FLEX9_C000 |Entity||FLEX9_C800 |Entity||FLEX9_D000 |Entity||FLEX9_D800 |Entity||flex_ram |Use||IEEE|STD_LOGIC_1164|all| |Use||IEEE|std_logic_1164|all| |Use||IEEE|std_logic_arith|all| |Use||unisim|vcomponents|all| addr_d800 FLEX9_D800 addr_d000 FLEX9_D000 addr_c800 FLEX9_C800 addr_c000 FLEX9_C000 unisim.vcomponents.all IEEE.STD_LOGIC_1164.all STD_LOGIC_1164 IEEE.std_logic_arith.all std_logic_arith IEEE.std_logic_1164.all |File||C:/sb/opencores/System09/src/sys09bug/sys09xes.vhd|PLUGIN_Vhdl|1207603951| |Architecture||rtl|SYS09BUG_F000|| |Architecture||rtl|SYS09BUG_F800|| |Architecture||rtl|mon_rom|| |ComponentInstantiation||mon_rom|rtl|addr_f000|SYS09BUG_F000| |ComponentInstantiation||mon_rom|rtl|addr_f800|SYS09BUG_F800| |Entity||SYS09BUG_F000 |Entity||SYS09BUG_F800 |Entity||mon_rom addr_f800 SYS09BUG_F800 addr_f000 SYS09BUG_F000 |File||C:/sb/opencores/System09/rtl/VHDL/trap.vhd|PLUGIN_Vhdl|1197219963| |Architecture||trap_arch|trap|| |Entity||trap trap_arch trap |File||C:/sb/opencores/System09/rtl/VHDL/vdu8.vhd|PLUGIN_Vhdl|1197219963| |Architecture||RTL|vdu8|| |ComponentInstantiation||vdu8|RTL|attr_buff_ram|ram_2k| |ComponentInstantiation||vdu8|RTL|char_buff_ram|ram_2k| |ComponentInstantiation||vdu8|RTL|vdu_char_rom|char_rom| |Entity||vdu8 |Use||IEEE|numeric_std|all| RTL attr_buff_ram ram_2k char_buff_ram vdu_char_rom char_rom IEEE.numeric_std.all |File||C:/sb/opencores/System09/rtl/Spartan3/char_rom2k_b16.vhd|PLUGIN_Vhdl|1205509963| |Architecture||rtl|char_rom|| |Entity||char_rom |File||C:/sb/opencores/System09/rtl/VHDL/ps2_keyboard.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ps2_keyboard_interface|| |ComponentInstantiation||ps2_keyboard_interface|rtl|my_key_map|keymap_rom| |Entity||ps2_keyboard_interface ps2_keyboard_interface my_key_map keymap_rom |File||C:/sb/opencores/System09/rtl/System09_Xilinx_ML506/XSA-3S1000.ucf|PLUGIN_AssocModule|1207593908| PLUGIN_AssocModule FILE_UCF |Module||XSA-3S1000.ucf XSA-3S1000.ucf DESUT_UCF |File||C:/sb/opencores/System09/rtl/Spartan3/ram2k_b16.vhd|PLUGIN_Vhdl|1197219959| |Architecture||rtl|ram_2k|| |Entity||ram_2k |File||C:/sb/opencores/System09/rtl/Spartan3/keymap_rom_slice.vhd|PLUGIN_Vhdl|1197219959| |Architecture||rtl|keymap_rom|| |Entity||keymap_rom |Use||ieee|std_logic_arith|all| ieee.std_logic_arith.all |File||C:/sb/opencores/System09/rtl/VHDL/keyboard.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|keyboard|| |ComponentInstantiation||keyboard|rtl|my_ps2_keyboard_interface|ps2_keyboard_interface| |Entity||keyboard my_ps2_keyboard_interface |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_TX.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_TX|| |Entity||ACIA_TX ACIA_TX |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_Clock.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_Clock|| |Entity||ACIA_Clock |PackageBody||bit_funcs| |PackageDecl||bit_funcs| |Use||IEEE|std_logic_unsigned|all| |Use||work|bit_funcs|all| work.bit_funcs.all bit_funcs DESUT_VHDL_PACKAGE_BODY IEEE.std_logic_unsigned.all DESUT_VHDL_PACKAGE_DECL |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_6850.vhd|PLUGIN_Vhdl|1197219963| |Architecture||rtl|ACIA_6850|| |ComponentInstantiation||ACIA_6850|rtl|RxDev|ACIA_RX| |ComponentInstantiation||ACIA_6850|rtl|TxDev|ACIA_TX| |Entity||ACIA_6850 TxDev RxDev ACIA_RX |File||C:/sb/opencores/System09/rtl/VHDL/ACIA_RX.vhd|PLUGIN_Vhdl|1197219963| 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ю 38 8 6 __OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl Architecture|my_system09|my_computer my_system09 - my_computer /my_system09 - my_computer/my_acia - ACIA_6850 - rtl /my_system09 - my_computer/my_flex - flex_ram - rtl /my_system09 - my_computer/my_keyboard - keyboard - rtl /my_system09 - my_computer/my_rom - mon_rom - rtl /my_system09 - my_computer/my_vdu - vdu8 - RTL my_system09 - my_computer (System09_Xilinx_ML506.vhd) /my_system09 - my_computer xc5vsx50t-3ff1136 Design Utilities DESUT_VHDL_ARCHITECTURE Generate Programming File Implement Design Synthesize - XST User Constraints ModelSim Simulator PK
|
ю 38 8 6 __OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl Architecture|my_system09|my_computer my_system09 - my_computer /my_system09 - my_computer/my_acia - ACIA_6850 - rtl /my_system09 - my_computer/my_flex - flex_ram - rtl /my_system09 - my_computer/my_keyboard - keyboard - rtl /my_system09 - my_computer/my_rom - mon_rom - rtl /my_system09 - my_computer/my_vdu - vdu8 - RTL my_system09 - my_computer (System09_Xilinx_ML506.vhd) /my_system09 - my_computer xc5vsx50t-3ff1136 Design Utilities DESUT_VHDL_ARCHITECTURE Generate Programming File Implement Design Synthesize - XST User Constraints ModelSim Simulator PK
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__REGISTRY__/hprep6/PK
|
__REGISTRY__/hprep6/PK
|
a. . __REGISTRY__/hprep6/regkeysClientMessageOutputFile
|
a. . __REGISTRY__/hprep6/regkeysClientMessageOutputFile
|
_xmsgs/hprep6.xmsgs
|
_xmsgs/hprep6.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/idem/PK
|
__REGISTRY__/idem/PK
|
, , __REGISTRY__/idem/regkeysClientMessageOutputFile
|
, , __REGISTRY__/idem/regkeysClientMessageOutputFile
|
_xmsgs/idem.xmsgs
|
_xmsgs/idem.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/map/PK
|
__REGISTRY__/map/PK
|
[+ + __REGISTRY__/map/regkeysClientMessageOutputFile
|
[+ + __REGISTRY__/map/regkeysClientMessageOutputFile
|
_xmsgs/map.xmsgs
|
_xmsgs/map.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/netgen/PK
|
__REGISTRY__/netgen/PK
|
e6~. . __REGISTRY__/netgen/regkeysClientMessageOutputFile
|
e6~. . __REGISTRY__/netgen/regkeysClientMessageOutputFile
|
_xmsgs/netgen.xmsgs
|
_xmsgs/netgen.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/ngc2edif/PK
|
__REGISTRY__/ngc2edif/PK
|
OUś0 0 __REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
|
OUś0 0 __REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
|
_xmsgs/ngc2edif.xmsgs
|
_xmsgs/ngc2edif.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/ngcbuild/PK
|
__REGISTRY__/ngcbuild/PK
|
E0 0 __REGISTRY__/ngcbuild/regkeysClientMessageOutputFile
|
E0 0 __REGISTRY__/ngcbuild/regkeysClientMessageOutputFile
|
_xmsgs/ngcbuild.xmsgs
|
_xmsgs/ngcbuild.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/ngdbuild/PK
|
__REGISTRY__/ngdbuild/PK
|
Jx0 0 __REGISTRY__/ngdbuild/regkeysClientMessageOutputFile
|
Jx0 0 __REGISTRY__/ngdbuild/regkeysClientMessageOutputFile
|
_xmsgs/ngdbuild.xmsgs
|
_xmsgs/ngdbuild.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/par/PK
|
__REGISTRY__/par/PK
|
+ + __REGISTRY__/par/regkeysClientMessageOutputFile
|
+ + __REGISTRY__/par/regkeysClientMessageOutputFile
|
_xmsgs/par.xmsgs
|
_xmsgs/par.xmsgs
|
s
|
s
|
PK
|
PK
|
__REGISTRY__/ProjectNavigator/PK
|
__REGISTRY__/ProjectNavigator/PK
|
Ǩ& & % __REGISTRY__/ProjectNavigator/regkeysISE_VERSION_LAST_SAVED_WITH
|
% __REGISTRY__/ProjectNavigator/NORMAL/PK
|
9.2.02i
|
) __REGISTRY__/ProjectNavigator/STATUS-ALL/PK
|
s
|
Ǩ& & % __REGISTRY__/ProjectNavigator/regkeysISE_VERSION_LAST_SAVED_WITH
|
PK
|
9.2.02i
|
! __REGISTRY__/ProjectNavigatorGui/PK
|
s
|
( __REGISTRY__/ProjectNavigatorGui/regkeysPK
|
PK
|
__REGISTRY__/runner/PK
|
! __REGISTRY__/ProjectNavigatorGui/PK
|
p7. . __REGISTRY__/runner/regkeysClientMessageOutputFile
|
( __REGISTRY__/ProjectNavigatorGui/regkeysPK
|
_xmsgs/runner.xmsgs
|
__REGISTRY__/runner/PK
|
s
|
p7. . __REGISTRY__/runner/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/runner.xmsgs
|
__REGISTRY__/SrcCtrl/PK
|
s
|
__REGISTRY__/SrcCtrl/regkeysPK
|
PK
|
__REGISTRY__/taengine/PK
|
__REGISTRY__/SrcCtrl/PK
|
0 0 __REGISTRY__/taengine/regkeysClientMessageOutputFile
|
__REGISTRY__/SrcCtrl/regkeysPK
|
_xmsgs/taengine.xmsgs
|
__REGISTRY__/taengine/PK
|
s
|
0 0 __REGISTRY__/taengine/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/taengine.xmsgs
|
__REGISTRY__/trce/PK
|
s
|
|
PK
|
, , __REGISTRY__/trce/regkeysClientMessageOutputFile
|
__REGISTRY__/trce/PK
|
_xmsgs/trce.xmsgs
|
|
s
|
, , __REGISTRY__/trce/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/trce.xmsgs
|
__REGISTRY__/tsim/PK
|
s
|
\-`, , __REGISTRY__/tsim/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/tsim.xmsgs
|
__REGISTRY__/tsim/PK
|
s
|
\-`, , __REGISTRY__/tsim/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/tsim.xmsgs
|
__REGISTRY__/vhpcomp/PK
|
s
|
Di/ / __REGISTRY__/vhpcomp/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/vhpcomp.xmsgs
|
__REGISTRY__/vhpcomp/PK
|
s
|
Di/ / __REGISTRY__/vhpcomp/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/vhpcomp.xmsgs
|
__REGISTRY__/vlogcomp/PK
|
s
|
] 0 0 __REGISTRY__/vlogcomp/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/vlogcomp.xmsgs
|
__REGISTRY__/vlogcomp/PK
|
s
|
] 0 0 __REGISTRY__/vlogcomp/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/vlogcomp.xmsgs
|
__REGISTRY__/xreport/PK
|
s
|
__REGISTRY__/xreport/regkeysPK
|
PK
|
__REGISTRY__/XSLTProcess/PK
|
__REGISTRY__/xreport/PK
|
q3 3 __REGISTRY__/XSLTProcess/regkeysClientMessageOutputFile
|
__REGISTRY__/xreport/regkeysPK
|
_xmsgs/XSLTProcess.xmsgs
|
__REGISTRY__/XSLTProcess/PK
|
s
|
q3 3 __REGISTRY__/XSLTProcess/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/XSLTProcess.xmsgs
|
__REGISTRY__/xst/PK
|
s
|
+ + __REGISTRY__/xst/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/xst.xmsgs
|
__REGISTRY__/xst/PK
|
s
|
+ + __REGISTRY__/xst/regkeysClientMessageOutputFile
|
PK
|
_xmsgs/xst.xmsgs
|
__REGISTRY__/_ProjRepoInternal_/PK
|
s
|
=Jw ' __REGISTRY__/_ProjRepoInternal_/regkeysISE_VERSION_CREATED_WITH
|
PK
|
8.2i
|
__REGISTRY__/_ProjRepoInternal_/PK
|
s
|
=Jw ' __REGISTRY__/_ProjRepoInternal_/regkeysISE_VERSION_CREATED_WITH
|
ISE_VERSION_LAST_SAVED_WITH
|
8.2i
|
9.2.02i
|
s
|
s
|
ISE_VERSION_LAST_SAVED_WITH
|
LastRepoDir
|
9.2.02i
|
C:\sb\opencores\System09\rtl\System09_Xilinx_ML506\
|
s
|
s
|
LastRepoDir
|
OBJSTORE_VERSION
|
C:\sb\opencores\System09\rtl\System09_Xilinx_ML506\
|
1.3
|
s
|
s
|
OBJSTORE_VERSION
|
REGISTRY_VERSION
|
1.3
|
1.1
|
s
|
s
|
REGISTRY_VERSION
|
REPOSITORY_VERSION
|
1.1
|
1.1
|
s
|
s
|
REPOSITORY_VERSION
|
PK
|
1.1
|
$ versionREPOSITORY_VERSION
|
s
|
1.1
|
PK
|
REGISTRY_VERSION
|
jG G versionREPOSITORY_VERSION
|
1.1
|
1.1
|
OBJSTORE_VERSION
|
REGISTRY_VERSION
|
1.3
|
1.1
|
ISE_VERSION_CREATED_WITH
|
OBJSTORE_VERSION
|
8.2i
|
1.3
|
ISE_VERSION_LAST_SAVED_WITH
|
|
9.2.02i
|
|
|
|
