--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- Company : XESS Corp.
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-- Company : XESS Corp.
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-- Engineer : Dave Vanden Bout
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-- Engineer : Dave Vanden Bout
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-- Creation Date : 05/17/2005
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-- Creation Date : 05/17/2005
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-- Copyright : 2005, XESS Corp
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-- Copyright : 2005, XESS Corp
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-- Tool Versions : WebPACK 6.3.03i
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-- Tool Versions : WebPACK 6.3.03i
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--
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--
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-- Description:
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-- Description:
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-- Customizes the generic SDRAM controller module for the XSA Board.
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-- Customizes the generic SDRAM controller module for the XSA Board.
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--
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--
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-- Revision:
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-- Revision:
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-- 1.1.0
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-- 1.2.0
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--
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--
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-- Additional Comments:
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-- Additional Comments:
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-- 1.2.0:
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-- added upper and lower data strobe signals
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-- John Kent 2008-03-23
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-- 1.1.0:
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-- 1.1.0:
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-- Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
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-- Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
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-- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
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-- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
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-- 1.0.0:
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-- 1.0.0:
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-- Initial release.
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-- Initial release.
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--
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--
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-- License:
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-- License:
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-- This code can be freely distributed and modified as long as
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-- This code can be freely distributed and modified as long as
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-- this header is not removed.
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-- this header is not removed.
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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library IEEE, UNISIM;
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library IEEE, UNISIM;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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use WORK.common.all;
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use WORK.common.all;
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use WORK.sdram.all;
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use WORK.sdram.all;
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package XSASDRAM is
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package XSASDRAM is
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component XSASDRAMCntl
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component XSASDRAMCntl
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generic(
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generic(
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FREQ : natural := 100_000; -- operating frequency in KHz
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FREQ : natural := 100_000; -- operating frequency in KHz
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CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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PIPE_EN : boolean := false; -- if true, enable pipelined read operations
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PIPE_EN : boolean := false; -- if true, enable pipelined read operations
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MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
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MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
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MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
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MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
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DATA_WIDTH : natural := 16; -- host & SDRAM data width
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DATA_WIDTH : natural := 16; -- host & SDRAM data width
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NROWS : natural := 8096; -- number of rows in SDRAM array
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NROWS : natural := 8096; -- number of rows in SDRAM array
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NCOLS : natural := 512; -- number of columns in SDRAM array
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NCOLS : natural := 512; -- number of columns in SDRAM array
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HADDR_WIDTH : natural := 24; -- host-side address width
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HADDR_WIDTH : natural := 24; -- host-side address width
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SADDR_WIDTH : natural := 13 -- SDRAM-side address width
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SADDR_WIDTH : natural := 13 -- SDRAM-side address width
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);
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);
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port(
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port(
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-- host side
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-- host side
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clk : in std_logic; -- master clock
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clk : in std_logic; -- master clock
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bufclk : out std_logic; -- buffered master clock
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bufclk : out std_logic; -- buffered master clock
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clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
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clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
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clk2x : out std_logic; -- double-speed host clock
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clk2x : out std_logic; -- double-speed host clock
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lock : out std_logic; -- true when host clock is locked to master clock
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lock : out std_logic; -- true when host clock is locked to master clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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rd : in std_logic; -- initiate read operation
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
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wr : in std_logic; -- initiate write operation
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uds : in std_logic; -- upper data strobe
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lds : in std_logic; -- lower data strobe
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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done : out std_logic; -- read or write operation is done
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done : out std_logic; -- read or write operation is done
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rdDone : out std_logic; -- read done and data is available
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rdDone : out std_logic; -- read done and data is available
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hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host
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hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host
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hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host
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hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host
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hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host
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hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host
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status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM
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status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM
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-- SDRAM side
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-- SDRAM side
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sclkfb : in std_logic; -- clock from SDRAM after PCB delays
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sclkfb : in std_logic; -- clock from SDRAM after PCB delays
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sclk : out std_logic; -- SDRAM clock sync'ed to master clock
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sclk : out std_logic; -- SDRAM clock sync'ed to master clock
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cke : out std_logic; -- clock-enable to SDRAM
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cke : out std_logic; -- clock-enable to SDRAM
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cs_n : out std_logic; -- chip-select to SDRAM
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cs_n : out std_logic; -- chip-select to SDRAM
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ras_n : out std_logic; -- SDRAM row address strobe
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ras_n : out std_logic; -- SDRAM row address strobe
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cas_n : out std_logic; -- SDRAM column address strobe
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cas_n : out std_logic; -- SDRAM column address strobe
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we_n : out std_logic; -- SDRAM write enable
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we_n : out std_logic; -- SDRAM write enable
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
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sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
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sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
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sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
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sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
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dqmh : out std_logic; -- high databits I/O mask
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dqmh : out std_logic; -- high databits I/O mask
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dqml : out std_logic -- low databits I/O mask
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dqml : out std_logic -- low databits I/O mask
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);
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);
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end component;
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end component;
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end package XSASDRAM;
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end package XSASDRAM;
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library IEEE, UNISIM;
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library IEEE, UNISIM;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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use WORK.common.all;
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use WORK.common.all;
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use WORK.sdram.all;
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use WORK.sdram.all;
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entity XSASDRAMCntl is
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entity XSASDRAMCntl is
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generic(
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generic(
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FREQ : natural := 100_000; -- operating frequency in KHz
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FREQ : natural := 100_000; -- operating frequency in KHz
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CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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PIPE_EN : boolean := false; -- if true, enable pipelined read operations
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PIPE_EN : boolean := false; -- if true, enable pipelined read operations
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MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
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MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
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MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
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MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
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DATA_WIDTH : natural := 16; -- host & SDRAM data width
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DATA_WIDTH : natural := 16; -- host & SDRAM data width
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NROWS : natural := 8192; -- number of rows in SDRAM array
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NROWS : natural := 8192; -- number of rows in SDRAM array
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NCOLS : natural := 512; -- number of columns in SDRAM array
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NCOLS : natural := 512; -- number of columns in SDRAM array
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HADDR_WIDTH : natural := 24; -- host-side address width
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HADDR_WIDTH : natural := 24; -- host-side address width
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SADDR_WIDTH : natural := 13 -- SDRAM-side address width
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SADDR_WIDTH : natural := 13 -- SDRAM-side address width
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);
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);
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port(
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port(
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-- host side
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-- host side
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clk : in std_logic; -- master clock
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clk : in std_logic; -- master clock
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bufclk : out std_logic; -- buffered master clock
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bufclk : out std_logic; -- buffered master clock
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clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
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clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
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clk2x : out std_logic; -- double-speed host clock
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clk2x : out std_logic; -- double-speed host clock
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lock : out std_logic; -- true when host clock is locked to master clock
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lock : out std_logic; -- true when host clock is locked to master clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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rd : in std_logic; -- initiate read operation
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
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wr : in std_logic; -- initiate write operation
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uds : in std_logic; -- upper data strobe
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lds : in std_logic; -- lower data strobe
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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done : out std_logic; -- read or write operation is done
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done : out std_logic; -- read or write operation is done
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rdDone : out std_logic; -- read done and data is available
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rdDone : out std_logic; -- read done and data is available
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hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host
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hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host
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hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host
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hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host
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hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host
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hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host
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status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM
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status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM
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-- SDRAM side
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-- SDRAM side
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sclkfb : in std_logic; -- clock from SDRAM after PCB delays
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sclkfb : in std_logic; -- clock from SDRAM after PCB delays
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sclk : out std_logic; -- SDRAM clock sync'ed to master clock
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sclk : out std_logic; -- SDRAM clock sync'ed to master clock
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cke : out std_logic; -- clock-enable to SDRAM
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cke : out std_logic; -- clock-enable to SDRAM
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cs_n : out std_logic; -- chip-select to SDRAM
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cs_n : out std_logic; -- chip-select to SDRAM
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ras_n : out std_logic; -- SDRAM row address strobe
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ras_n : out std_logic; -- SDRAM row address strobe
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cas_n : out std_logic; -- SDRAM column address strobe
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cas_n : out std_logic; -- SDRAM column address strobe
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we_n : out std_logic; -- SDRAM write enable
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we_n : out std_logic; -- SDRAM write enable
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
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sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
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sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
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sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
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sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
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dqmh : out std_logic; -- high databits I/O mask
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dqmh : out std_logic; -- high databits I/O mask
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dqml : out std_logic -- low databits I/O mask
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dqml : out std_logic -- low databits I/O mask
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);
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);
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end XSASDRAMCntl;
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end XSASDRAMCntl;
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architecture arch of XSASDRAMCntl is
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architecture arch of XSASDRAMCntl is
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-- The SDRAM controller and external SDRAM chip will clock on the same edge
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-- The SDRAM controller and external SDRAM chip will clock on the same edge
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-- if the frequency and divided frequency are both greater than the minimum DLL lock frequency.
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-- if the frequency and divided frequency are both greater than the minimum DLL lock frequency.
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-- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
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-- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
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-- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
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-- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
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constant MIN_LOCK_FREQ : real := 25_000.0;
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constant MIN_LOCK_FREQ : real := 25_000.0;
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constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
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constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
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-- Calculate the frequency of the clock for the SDRAM.
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-- Calculate the frequency of the clock for the SDRAM.
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constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
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-- constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
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constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*2)/integer(2.0*CLK_DIV), FREQ);
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-- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1
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-- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1
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-- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output
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-- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output
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-- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
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-- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
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constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
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constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
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|
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signal int_clkin, -- signals for internal logic clock DLL
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signal int_clkin, -- signals for internal logic clock DLL
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int_clk1x, int_clk1x_b,
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int_clk1x, int_clk1x_b,
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int_clk2x, int_clk2x_b,
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int_clk2x, int_clk2x_b,
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int_clkdv, int_clkdv_b : std_logic;
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int_clkdv, int_clkdv_b : std_logic;
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signal ext_clkin, sclkfb_b, ext_clk1x : std_logic; -- signals for external logic clock DLL
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signal ext_clkin, sclkfb_b, ext_clk1x : std_logic; -- signals for external logic clock DLL
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signal dllext_rst, dllext_rst_n : std_logic; -- external DLL reset signal
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signal dllext_rst, dllext_rst_n : std_logic; -- external DLL reset signal
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signal clk_i : std_logic; -- clock for SDRAM controller logic
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signal clk_i : std_logic; -- clock for SDRAM controller logic
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signal int_lock, ext_lock, lock_i : std_logic; -- DLL lock signals
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signal int_lock, ext_lock, lock_i : std_logic; -- DLL lock signals
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|
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-- bus for holding output data from SDRAM
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-- bus for holding output data from SDRAM
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signal sDOut : std_logic_vector(sData'range);
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signal sDOut : std_logic_vector(sData'range);
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signal sDOutEn : std_logic;
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signal sDOutEn : std_logic;
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begin
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begin
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|
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-----------------------------------------------------------
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-----------------------------------------------------------
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-- setup the DLLs for clock generation
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-- setup the DLLs for clock generation
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-----------------------------------------------------------
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-----------------------------------------------------------
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-- master clock must come from a dedicated clock pin
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-- master clock must come from a dedicated clock pin
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clkin : IBUFG port map (I => clk, O => int_clkin);
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clkin_buf : BUFG port map (I => clk, O => int_clkin);
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|
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-- The external DLL is driven from the same source as the internal DLL
|
-- The external DLL is driven from the same source as the internal DLL
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-- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL
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-- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL
|
-- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be
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-- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be
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-- clocked on the opposite edge if the internal and external logic are not in-phase.
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-- clocked on the opposite edge if the internal and external logic are not in-phase.
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ext_clkin <= int_clkin when (IN_PHASE and (CLK_DIV = 1.0)) else
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ext_clkin <= int_clkin when (IN_PHASE and (CLK_DIV = 1.0)) else
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int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
|
int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
|
not int_clkin;
|
not int_clkin;
|
|
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-- Generate the DLLs for sync'ing the clocks as long as the clocks
|
-- Generate the DLLs for sync'ing the clocks as long as the clocks
|
-- have a frequency high enough for the DLLs to lock
|
-- have a frequency high enough for the DLLs to lock
|
gen_dlls : if IN_PHASE generate
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gen_dlls : if IN_PHASE generate
|
|
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-- generate an internal clock sync'ed to the master clock
|
-- generate an internal clock sync'ed to the master clock
|
dllint : CLKDLL
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dllint : CLKDLL
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generic map(
|
generic map(
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CLKDV_DIVIDE => CLKDV_DIVIDE
|
CLKDV_DIVIDE => CLKDV_DIVIDE
|
)
|
)
|
port map(
|
port map(
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CLKIN => int_clkin,
|
CLKIN => int_clkin,
|
CLKFB => int_clk1x_b,
|
CLKFB => int_clk1x_b,
|
CLK0 => int_clk1x,
|
CLK0 => int_clk1x,
|
RST => ZERO,
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RST => ZERO,
|
CLK90 => open,
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CLK90 => open,
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CLK180 => open,
|
CLK180 => open,
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CLK270 => open,
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CLK270 => open,
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CLK2X => int_clk2x,
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CLK2X => int_clk2x,
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CLKDV => int_clkdv,
|
CLKDV => int_clkdv,
|
LOCKED => int_lock
|
LOCKED => int_lock
|
);
|
);
|
|
|
-- sync'ed single, doubled and divided clocks for use by internal logic
|
-- sync'ed single, doubled and divided clocks for use by internal logic
|
int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b);
|
int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b);
|
int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b);
|
int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b);
|
int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b);
|
int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b);
|
|
|
-- The external DLL is held in a reset state until the internal DLL locks.
|
-- The external DLL is held in a reset state until the internal DLL locks.
|
-- Then the external DLL reset is released after a delay set by this shift register.
|
-- Then the external DLL reset is released after a delay set by this shift register.
|
-- This keeps the external DLL from locking onto the internal DLL clock signal
|
-- This keeps the external DLL from locking onto the internal DLL clock signal
|
-- until it is stable.
|
-- until it is stable.
|
SRL16_inst : SRL16
|
SRL16_inst : SRL16
|
generic map (
|
generic map (
|
INIT => X"0000"
|
INIT => X"0000"
|
)
|
)
|
port map (
|
port map (
|
CLK => clk_i,
|
CLK => clk_i,
|
A0 => '1',
|
A0 => '1',
|
A1 => '1',
|
A1 => '1',
|
A2 => '1',
|
A2 => '1',
|
A3 => '1',
|
A3 => '1',
|
D => int_lock,
|
D => int_lock,
|
Q => dllext_rst_n
|
Q => dllext_rst_n
|
);
|
);
|
dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
|
-- Error ???
|
|
-- dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
|
|
dllext_rst <= not dllext_rst_n when CLK_DIV/=1.0 else ZERO;
|
|
|
-- generate an external SDRAM clock sync'ed to the master clock
|
-- generate an external SDRAM clock sync'ed to the master clock
|
sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
|
sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
|
-- sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
|
|
dllext : CLKDLL port map(
|
dllext : CLKDLL port map(
|
CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL
|
CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL
|
CLKFB => sclkfb_b,
|
CLKFB => sclkfb_b,
|
CLK0 => ext_clk1x,
|
CLK0 => ext_clk1x,
|
RST => dllext_rst,
|
RST => dllext_rst,
|
CLK90 => open,
|
CLK90 => open,
|
CLK180 => open,
|
CLK180 => open,
|
CLK270 => open,
|
CLK270 => open,
|
CLK2X => open,
|
CLK2X => open,
|
CLKDV => open,
|
CLKDV => open,
|
LOCKED => ext_lock
|
LOCKED => ext_lock
|
);
|
);
|
|
|
end generate;
|
end generate;
|
|
|
-- The buffered clock is just a buffered version of the master clock.
|
-- The buffered clock is just a buffered version of the master clock.
|
bufclk <= int_clkin;
|
bufclk_bufg : BUFG port map (I => int_clkin, O => bufclk);
|
-- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
|
-- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
|
-- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
|
-- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
|
-- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
|
-- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
|
clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
|
clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
|
int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
|
int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
|
int_clkin;
|
int_clkin;
|
clk1x <= clk_i; -- This is the output of the host-side clock
|
clk1x <= clk_i; -- This is the output of the host-side clock
|
clk2x <= int_clk2x_b when IN_PHASE else int_clkin; -- this is the doubled master clock
|
clk2x <= int_clk2x_b when IN_PHASE else int_clkin; -- this is the doubled master clock
|
sclk <= ext_clk1x when IN_PHASE else ext_clkin; -- this is the clock for the external SDRAM
|
sclk <= ext_clk1x when IN_PHASE else ext_clkin; -- this is the clock for the external SDRAM
|
|
|
-- indicate the lock status of the internal and external DLL
|
-- indicate the lock status of the internal and external DLL
|
lock_i <= int_lock and ext_lock when IN_PHASE else YES;
|
lock_i <= int_lock and ext_lock when IN_PHASE else YES;
|
lock <= lock_i; -- lock signal for the host logic
|
lock <= lock_i; -- lock signal for the host logic
|
|
|
-- SDRAM memory controller module
|
-- SDRAM memory controller module
|
u1 : sdramCntl
|
u1 : sdramCntl
|
generic map(
|
generic map(
|
FREQ => SDRAM_FREQ,
|
FREQ => SDRAM_FREQ,
|
IN_PHASE => IN_PHASE,
|
IN_PHASE => IN_PHASE,
|
PIPE_EN => PIPE_EN,
|
PIPE_EN => PIPE_EN,
|
MAX_NOP => MAX_NOP,
|
MAX_NOP => MAX_NOP,
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
DATA_WIDTH => DATA_WIDTH,
|
DATA_WIDTH => DATA_WIDTH,
|
NROWS => NROWS,
|
NROWS => NROWS,
|
NCOLS => NCOLS,
|
NCOLS => NCOLS,
|
HADDR_WIDTH => HADDR_WIDTH,
|
HADDR_WIDTH => HADDR_WIDTH,
|
SADDR_WIDTH => SADDR_WIDTH
|
SADDR_WIDTH => SADDR_WIDTH
|
)
|
)
|
port map(
|
port map(
|
clk => clk_i, -- master clock from external clock source (unbuffered)
|
clk => clk_i, -- master clock from external clock source (unbuffered)
|
lock => lock_i, -- valid synchronized clocks indicator
|
lock => lock_i, -- valid synchronized clocks indicator
|
rst => rst, -- reset
|
rst => rst, -- reset
|
rd => rd, -- host-side SDRAM read control from memory tester
|
rd => rd, -- host-side SDRAM read control from memory tester
|
wr => wr, -- host-side SDRAM write control from memory tester
|
wr => wr, -- host-side SDRAM write control from memory tester
|
|
uds => uds, -- host-side SDRAM upper data strobe
|
|
lds => lds, -- host-side SDRAM lower data strobe
|
rdPending => rdPending,
|
rdPending => rdPending,
|
opBegun => opBegun, -- SDRAM memory read/write done indicator
|
opBegun => opBegun, -- SDRAM memory read/write done indicator
|
earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator
|
earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator
|
rdDone => rdDone, -- SDRAM memory read/write done indicator
|
rdDone => rdDone, -- SDRAM memory read/write done indicator
|
done => done,
|
done => done,
|
hAddr => hAddr, -- host-side address from memory tester
|
hAddr => hAddr, -- host-side address from memory tester
|
hDIn => hDIn, -- test data pattern from memory tester
|
hDIn => hDIn, -- test data pattern from memory tester
|
hDOut => hDOut, -- SDRAM data output to memory tester
|
hDOut => hDOut, -- SDRAM data output to memory tester
|
status => status, -- SDRAM controller state (for diagnostics)
|
status => status, -- SDRAM controller state (for diagnostics)
|
cke => cke, -- SDRAM clock enable
|
cke => cke, -- SDRAM clock enable
|
ce_n => cs_n, -- SDRAM chip-select
|
ce_n => cs_n, -- SDRAM chip-select
|
ras_n => ras_n, -- SDRAM RAS
|
ras_n => ras_n, -- SDRAM RAS
|
cas_n => cas_n, -- SDRAM CAS
|
cas_n => cas_n, -- SDRAM CAS
|
we_n => we_n, -- SDRAM write-enable
|
we_n => we_n, -- SDRAM write-enable
|
ba => ba, -- SDRAM bank address
|
ba => ba, -- SDRAM bank address
|
sAddr => sAddr, -- SDRAM address
|
sAddr => sAddr, -- SDRAM address
|
sDIn => sData, -- input data from SDRAM
|
sDIn => sData, -- input data from SDRAM
|
sDOut => sDOut, -- output data to SDRAM
|
sDOut => sDOut, -- output data to SDRAM
|
sDOutEn => sDOutEn, -- enable drivers to send data to SDRAM
|
sDOutEn => sDOutEn, -- enable drivers to send data to SDRAM
|
dqmh => dqmh, -- SDRAM DQMH
|
dqmh => dqmh, -- SDRAM DQMH
|
dqml => dqml -- SDRAM DQML
|
dqml => dqml -- SDRAM DQML
|
);
|
);
|
|
|
sData <= sDOut when sDOutEn = YES else (others => 'Z');
|
sData <= sDOut when sDOutEn = YES else (others => 'Z');
|
|
|
end arch;
|
end arch;
|
|
|
