--===========================================================================--
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--===========================================================================--
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--
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--
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-- MC6809 Microprocessor Test Bench 4
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-- MC6809 Microprocessor Test Bench 4
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-- Test Software - SBUG ROM
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-- Test Software - SBUG ROM
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--
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--
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--
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--
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-- John Kent 12st April 2003
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-- John Kent 12st April 2003
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--
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--
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-- Version 1.1 - 25th Jan 2004 - John Kent
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-- Version 1.1 - 25th Jan 2004 - John Kent
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-- removed "test_alu" and "test_cc"
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-- removed "test_alu" and "test_cc"
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity my_testbench is
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entity my_testbench is
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end my_testbench;
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end my_testbench;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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architecture behavior of my_testbench is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal cpu_irq : std_Logic;
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signal cpu_irq : std_Logic;
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signal cpu_firq : std_logic;
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signal cpu_firq : std_logic;
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signal cpu_nmi : std_logic;
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signal cpu_nmi : std_logic;
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-- CPU Interface signals
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal SysClk : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_rw : Std_Logic;
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signal cpu_rw : Std_Logic;
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signal cpu_vma : Std_Logic;
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signal cpu_vma : Std_Logic;
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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signal cpu_halt : Std_logic;
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signal cpu_halt : Std_logic;
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signal cpu_hold : Std_logic;
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signal cpu_hold : Std_logic;
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signal rom_data_out: Std_Logic_Vector(7 downto 0);
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signal rom_data_out: Std_Logic_Vector(7 downto 0);
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signal ram_data_out: Std_Logic_Vector(7 downto 0);
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signal ram_data_out: Std_Logic_Vector(7 downto 0);
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signal ram_cs : Std_Logic;
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signal ram_cs : Std_Logic;
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component cpu09
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component cpu09
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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address: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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halt: in std_logic;
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hold: in std_logic;
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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nmi: in std_logic;
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nmi: in std_logic;
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firq: in std_logic
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firq: in std_logic
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);
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);
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end component;
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end component;
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component sbug_rom
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component sbug_rom
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Port (
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Port (
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MEMclk : in std_logic;
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MEMclk : in std_logic;
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MEMaddr : in std_logic_vector (10 downto 0);
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MEMaddr : in std_logic_vector (10 downto 0);
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MEMrdata : out std_logic_vector (7 downto 0)
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MEMrdata : out std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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component block_ram
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component block_ram
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Port (
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Port (
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MEMclk : in std_logic;
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MEMclk : in std_logic;
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MEMcs : in std_logic;
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MEMcs : in std_logic;
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MEMrw : in std_logic;
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MEMrw : in std_logic;
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MEMaddr : in std_logic_vector (10 downto 0);
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MEMaddr : in std_logic_vector (10 downto 0);
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MEMrdata : out std_logic_vector (7 downto 0);
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MEMrdata : out std_logic_vector (7 downto 0);
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MEMwdata : in std_logic_vector (7 downto 0)
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MEMwdata : in std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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my_cpu : cpu09 port map (
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my_cpu : cpu09 port map (
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clk => SysClk,
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clk => SysClk,
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rst => cpu_reset,
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rst => cpu_reset,
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rw => cpu_rw,
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rw => cpu_rw,
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vma => cpu_vma,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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address => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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data_out => cpu_data_out,
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halt => cpu_halt,
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halt => cpu_halt,
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hold => cpu_hold,
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hold => cpu_hold,
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irq => cpu_irq,
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irq => cpu_irq,
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nmi => cpu_nmi,
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nmi => cpu_nmi,
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firq => cpu_firq
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firq => cpu_firq
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);
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);
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my_ram : block_ram port map (
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my_ram : block_ram port map (
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MEMclk => SysClk,
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MEMclk => SysClk,
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MEMcs => ram_cs,
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MEMcs => ram_cs,
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MEMrw => cpu_rw,
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MEMrw => cpu_rw,
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MEMaddr => cpu_addr(10 downto 0),
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MEMaddr => cpu_addr(10 downto 0),
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MEMrdata => ram_data_out,
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MEMrdata => ram_data_out,
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MEMwdata => cpu_data_out
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MEMwdata => cpu_data_out
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);
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);
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my_rom : sbug_rom port map (
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my_rom : sbug_rom port map (
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MEMclk => SysClk,
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MEMclk => SysClk,
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MEMaddr => cpu_addr(10 downto 0),
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MEMaddr => cpu_addr(10 downto 0),
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MEMrdata => rom_data_out
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MEMrdata => rom_data_out
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);
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);
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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tb : PROCESS
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variable count : integer;
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variable count : integer;
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BEGIN
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BEGIN
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cpu_reset <= '0';
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cpu_reset <= '0';
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SysClk <= '0';
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SysClk <= '0';
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cpu_irq <= '0';
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cpu_irq <= '0';
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cpu_nmi <= '0';
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cpu_nmi <= '0';
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cpu_firq <= '0';
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cpu_firq <= '0';
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cpu_halt <= '0';
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cpu_halt <= '0';
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cpu_hold <= '0';
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cpu_hold <= '0';
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for count in 0 to 512 loop
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for count in 0 to 512 loop
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SysClk <= '0';
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SysClk <= '0';
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if count = 0 then
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if count = 0 then
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cpu_reset <= '1';
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cpu_reset <= '1';
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elsif count = 1 then
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elsif count = 1 then
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cpu_reset <= '0';
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cpu_reset <= '0';
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end if;
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end if;
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wait for 100 ns;
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wait for 100 ns;
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SysClk <= '1';
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SysClk <= '1';
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wait for 100 ns;
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wait for 100 ns;
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end loop;
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end loop;
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wait; -- will wait forever
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wait; -- will wait forever
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END PROCESS;
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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-- *** End Test Bench - User Defined Section ***
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rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
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rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
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begin
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begin
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if( cpu_addr(15 downto 11) = "11111" ) then
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if( cpu_addr(15 downto 11) = "11111" ) then
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cpu_data_in <= rom_data_out;
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cpu_data_in <= rom_data_out;
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ram_cs <= '0';
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ram_cs <= '0';
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else
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else
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cpu_data_in <= ram_data_out;
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cpu_data_in <= ram_data_out;
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ram_cs <= '1';
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ram_cs <= '1';
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end if;
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end if;
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end process;
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end process;
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end behavior; --===================== End of architecture =======================--
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end behavior; --===================== End of architecture =======================--
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