-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- ACIA Clock Divider for System09
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-- ACIA Clock Divider for System09
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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|
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entity ACIA_Clock is
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entity ACIA_Clock is
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generic (
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generic (
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SYS_Clock_Frequency : integer;
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SYS_Clock_Frequency : integer;
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BAUD_Clock_Frequency : integer
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BAUD_Clock_Frequency : integer
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);
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);
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port(
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port(
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clk : in Std_Logic; -- System Clock input
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clk : in Std_Logic; -- System Clock input
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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);
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);
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end ACIA_Clock;
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end ACIA_Clock;
|
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for ACIA_Clock
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-- Architecture for ACIA_Clock
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture rtl of ACIA_Clock is
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architecture rtl of ACIA_Clock is
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|
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constant full_cycle : integer := (SYS_Clock_Frequency / BAUD_Clock_Frequency) - 1;
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constant full_cycle : integer := (SYS_Clock_Frequency / BAUD_Clock_Frequency) - 1;
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constant half_cycle : integer := (full_cycle / 2) - 1;
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constant half_cycle : integer := (full_cycle / 2) - 1;
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--
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--
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-- Baud Rate Clock Divider
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-- Baud Rate Clock Divider
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--
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--
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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--
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--
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my_baud_clock: process( SysClk )
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my_baud_clock: process( SysClk )
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begin
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begin
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if(SysClk'event and SysClk = '0') then
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if(SysClk'event and SysClk = '0') then
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if( BaudCount = 53 ) then
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if( BaudCount = 53 ) then
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baudclk <= '0';
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baudclk <= '0';
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BaudCount <= "000000";
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BaudCount <= "000000";
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else
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else
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if( BaudCount = 26 ) then
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if( BaudCount = 26 ) then
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baudclk <='1';
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baudclk <='1';
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else
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else
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baudclk <=baudclk;
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baudclk <=baudclk;
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end if;
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end if;
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BaudCount <= BaudCount + 1;
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BaudCount <= BaudCount + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
|
|
|
