-- $Id: cpu09.vhd,v 1.2 2008-03-14 15:52:46 dilbert57 Exp $
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--===========================================================================--
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--===========================================================================----
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-- --
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--
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-- Synthesizable 6809 instruction compatible VHDL CPU core --
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-- S Y N T H E Z I A B L E CPU09 - 6809 compatible CPU Core
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-- --
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--
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--===========================================================================--
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-- www.OpenCores.Org - September 2003
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-- This core adheres to the GNU public license
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--
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--
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-- File name : cpu09.vhd
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-- File name : cpu09.vhd
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--
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--
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-- Purpose : 6809 CPU core
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-- Entity name : cpu09
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Purpose : 6809 instruction compatible CPU core written in VHDL
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-- ieee.std_logic_unsigned
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-- Not cycle compatible with the original 6809 CPU
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--
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--
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-- Uses : None
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_unsigned
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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--
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-- Revision History:
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- Version 0.1 - 26 June 2003 - John Kent
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-- Version 0.1 - 26 June 2003 - John Kent
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-- Added extra level in state stack
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-- Added extra level in state stack
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-- fixed some calls to the extended addressing state
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-- fixed some calls to the extended addressing state
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--
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--
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-- Version 0.2 - 5 Sept 2003 - John Kent
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-- Version 0.2 - 5 Sept 2003 - John Kent
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-- Fixed 16 bit indexed offset (was doing read rather than fetch)
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-- Fixed 16 bit indexed offset (was doing read rather than fetch)
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-- Added/Fixed STY and STS instructions.
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-- Added/Fixed STY and STS instructions.
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-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
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-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
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-- CMPX Loaded ACCA and ACCB - Now fixed
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-- CMPX Loaded ACCA and ACCB - Now fixed
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--
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--
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-- Version 1.0 - 6 Sep 2003 - John Kent
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-- Version 1.0 - 6 Sep 2003 - John Kent
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-- Initial release to Open Cores
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-- Initial release to Open Cores
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-- reversed clock edge
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-- reversed clock edge
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--
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--
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-- Version 1.1 - 29 November 2003 John kent
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-- Version 1.1 - 29 November 2003 John kent
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-- ACCA and ACCB indexed offsets are 2's complement.
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-- ACCA and ACCB indexed offsets are 2's complement.
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-- ALU Right Mux now sign extends ACCA & ACCB offsets
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-- ALU Right Mux now sign extends ACCA & ACCB offsets
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-- Absolute Indirect addressing performed a read on the
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-- Absolute Indirect addressing performed a read on the
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-- second byte of the address rather than a fetch
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-- second byte of the address rather than a fetch
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-- so it formed an incorrect address. Now fixed.
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-- so it formed an incorrect address. Now fixed.
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--
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--
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-- Version 1.2 - 29 November 2003 John Kent
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-- Version 1.2 - 29 November 2003 John Kent
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-- LEAX and LEAY affect the Z bit only
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-- LEAX and LEAY affect the Z bit only
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-- LEAS and LEAU do not affect any condition codes
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-- LEAS and LEAU do not affect any condition codes
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-- added an extra ALU control for LEA.
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-- added an extra ALU control for LEA.
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--
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--
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-- Version 1.3 - 12 December 2003 John Kent
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-- Version 1.3 - 12 December 2003 John Kent
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-- CWAI did not work, was missed a PUSH_ST on calling
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-- CWAI did not work, was missed a PUSH_ST on calling
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-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
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-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
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-- finding this fault.
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-- finding this fault.
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--
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--
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-- Version 1.4 - 12 December 2003 John Kent
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-- Version 1.4 - 12 December 2003 John Kent
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-- Missing cc_ctrl assignment in otherwise case of
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-- Missing cc_ctrl assignment in otherwise case of
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-- lea_state resulted in cc_ctrl being latched in
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-- lea_state resulted in cc_ctrl being latched in
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-- that state.
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-- that state.
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-- The otherwise statement should never be reached,
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-- The otherwise statement should never be reached,
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-- and has been fixed simply to resolve synthesis warnings.
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-- and has been fixed simply to resolve synthesis warnings.
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--
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--
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-- Version 1.5 - 17 january 2004 John kent
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-- Version 1.5 - 17 january 2004 John kent
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-- The clear instruction used "alu_ld8" to control the ALU
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-- The clear instruction used "alu_ld8" to control the ALU
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-- rather than "alu_clr". This mean the Carry was not being
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-- rather than "alu_clr". This mean the Carry was not being
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-- cleared correctly.
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-- cleared correctly.
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--
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--
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-- Version 1.6 - 24 January 2004 John Kent
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-- Version 1.6 - 24 January 2004 John Kent
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-- Fixed problems in PSHU instruction
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-- Fixed problems in PSHU instruction
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--
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--
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-- Version 1.7 - 25 January 2004 John Kent
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-- Version 1.7 - 25 January 2004 John Kent
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-- removed redundant "alu_inx" and "alu_dex'
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-- removed redundant "alu_inx" and "alu_dex'
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-- Removed "test_alu" and "test_cc"
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-- Removed "test_alu" and "test_cc"
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-- STD instruction did not set condition codes
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-- STD instruction did not set condition codes
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-- JMP direct was not decoded properly
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-- JMP direct was not decoded properly
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-- CLR direct performed an unwanted read cycle
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-- CLR direct performed an unwanted read cycle
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-- Bogus "latch_md" in Page2 indexed addressing
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-- Bogus "latch_md" in Page2 indexed addressing
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--
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--
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-- Version 1.8 - 27 January 2004 John Kent
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-- Version 1.8 - 27 January 2004 John Kent
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-- CWAI in decode1_state should increment the PC.
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-- CWAI in decode1_state should increment the PC.
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-- ABX is supposed to be an unsigned addition.
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-- ABX is supposed to be an unsigned addition.
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-- Added extra ALU function
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-- Added extra ALU function
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-- ASR8 slightly changed in the ALU.
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-- ASR8 slightly changed in the ALU.
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--
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--
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-- Version 1.9 - 20 August 2005
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-- Version 1.9 - 20 August 2005
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-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
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-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
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-- rather than LSR16. There was a problem with single
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-- rather than LSR16. There was a problem with single
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-- operand instructions using the MD register which is
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-- operand instructions using the MD register which is
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-- sign extended on the first 8 bit fetch.
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-- sign extended on the first 8 bit fetch.
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--
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--
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-- Version 1.10 - 13 September 2005
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-- Version 1.10 - 13 September 2005
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-- TFR & EXG instructions did not work for the Condition Code Register
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-- TFR & EXG instructions did not work for the Condition Code Register
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-- An extra case has been added to the ALU for the alu_tfr control
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-- An extra case has been added to the ALU for the alu_tfr control
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-- to assign the left ALU input (alu_left) to the condition code
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-- to assign the left ALU input (alu_left) to the condition code
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-- outputs (cc_out).
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-- outputs (cc_out).
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--
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--
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-- Version 1.11 - 16 September 2005
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-- Version 1.11 - 16 September 2005
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-- JSR ,X should not predecrement S before calculating the jump address.
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-- JSR ,X should not predecrement S before calculating the jump address.
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-- The reason is that JSR [0,S] needs S to point to the top of the stack
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-- The reason is that JSR [0,S] needs S to point to the top of the stack
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-- to fetch a valid vector address. The solution is to have the addressing
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-- to fetch a valid vector address. The solution is to have the addressing
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-- mode microcode called before decrementing S and then decrementing S in
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-- mode microcode called before decrementing S and then decrementing S in
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-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
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-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
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-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
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-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
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-- pushed on the stack. This adds one extra bus cycle, but resolves the
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-- pushed on the stack. This adds one extra bus cycle, but resolves the
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-- addressing conflict. I've also removed the pre-decement S in
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-- addressing conflict. I've also removed the pre-decement S in
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-- JSR EXTENDED as it also calls JSR_STATE.
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-- JSR EXTENDED as it also calls JSR_STATE.
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--
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--
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-- Version 1.12 - 6th June 2006
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-- Version 1.12 - 6th June 2006
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-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
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-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
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-- This is different to the 6800. CLR should reset the V bit.
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-- This is different to the 6800. CLR should reset the V bit.
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--
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--
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-- Version 1.13 - 7th July 2006
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-- Version 1.13 - 7th July 2006
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-- Disable NMI on reset until S Stack pointer has been loaded.
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-- Disable NMI on reset until S Stack pointer has been loaded.
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-- Added nmi_enable signal in sp_reg process and nmi_handler process.
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-- Added nmi_enable signal in sp_reg process and nmi_handler process.
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--
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--
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-- Version 1.14 - 11th July 2006
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-- Version 1.14 - 11th July 2006
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-- 1. Added new state to RTI called rti_entire_state.
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-- 1. Added new state to RTI called rti_entire_state.
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-- This state tests the CC register after it has been loaded
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-- This state tests the CC register after it has been loaded
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-- from the stack. Previously the current CC was tested which
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-- from the stack. Previously the current CC was tested which
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-- was incorrect. The Entire Flag should be set before the
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-- was incorrect. The Entire Flag should be set before the
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-- interrupt stacks the CC.
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-- interrupt stacks the CC.
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-- 2. On bogus Interrupts, int_cc_state went to rti_state,
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-- 2. On bogus Interrupts, int_cc_state went to rti_state,
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-- which was an enumerated state, but not defined anywhere.
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-- which was an enumerated state, but not defined anywhere.
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-- rti_state has been changed to rti_cc_state so that bogus interrupt
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-- rti_state has been changed to rti_cc_state so that bogus interrupt
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-- will perform an RTI after entering that state.
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-- will perform an RTI after entering that state.
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-- 3. Sync should generate an interrupt if the interrupt masks
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-- 3. Sync should generate an interrupt if the interrupt masks
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-- are cleared. If the interrupt masks are set, then an interrupt
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-- are cleared. If the interrupt masks are set, then an interrupt
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-- will cause the the PC to advance to the next instruction.
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-- will cause the the PC to advance to the next instruction.
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-- Note that I don't wait for an interrupt to be asserted for
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-- Note that I don't wait for an interrupt to be asserted for
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-- three clock cycles.
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-- three clock cycles.
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-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
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-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
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-- the Multiply instruction replacing "alu_add16". This is similar
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-- the Multiply instruction replacing "alu_add16". This is similar
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-- to "alu_add16" except it sets the Carry bit to B7 of the result
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-- to "alu_add16" except it sets the Carry bit to B7 of the result
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-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
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-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
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-- does not affect The Half carry (H), Negative (N) or Overflow (V)
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-- does not affect The Half carry (H), Negative (N) or Overflow (V)
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-- flags. The logic was re-arranged so that it adds md or zero so
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-- flags. The logic was re-arranged so that it adds md or zero so
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-- that the Carry condition code is set on zero multiplicands.
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-- that the Carry condition code is set on zero multiplicands.
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-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
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-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
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-- and Zero Flags. It will also affect the Overflow (V) flag although
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-- and Zero Flags. It will also affect the Overflow (V) flag although
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-- the operation is undefined. It's anyones guess what DAA does to V.
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-- the operation is undefined. It's anyones guess what DAA does to V.
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--
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--
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-- Version 1.15 - 25th Feb 2007 - John Kent
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-- Version 1.15 - 25th Feb 2007 - John Kent
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-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
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-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
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-- Changed sensitivity lists.
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-- Changed sensitivity lists.
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--
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--
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-- Version 1.16 - 5th February 2008 - John Kent
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-- Version 1.16 - 5th February 2008 - John Kent
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-- FIRQ interrupts should take priority over IRQ Interrupts.
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-- FIRQ interrupts should take priority over IRQ Interrupts.
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-- This presumably means they should be tested for before IRQ
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-- This presumably means they should be tested for before IRQ
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-- when they happen concurrently.
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-- when they happen concurrently.
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--
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--
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-- Version 1.17 - 18th February 2008 - John Kent
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-- Version 1.17 - 18th February 2008 - John Kent
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-- NMI in CWAI should mask IRQ and FIRQ interrupts
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-- NMI in CWAI should mask IRQ and FIRQ interrupts
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--
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--
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-- Version 1.18 - 21st February 2008 - John Kent
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-- Version 1.18 - 21st February 2008 - John Kent
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-- Removed default register settings in each case statement
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-- Removed default register settings in each case statement
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-- and placed them at the beginning of the state sequencer.
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-- and placed them at the beginning of the state sequencer.
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-- Modified the SYNC instruction so that the interrupt vector(iv)
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-- Modified the SYNC instruction so that the interrupt vector(iv)
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-- is not set unless an unmasked FIRQ or IRQ is received.
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-- is not set unless an unmasked FIRQ or IRQ is received.
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--
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--
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-- Version 1.19 - 25th February 2008 - John Kent
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-- Version 1.19 - 25th February 2008 - John Kent
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-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
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-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
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-- Enumerated separate states for MASKI and MASKIF states
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-- Enumerated separate states for MASKI and MASKIF states
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-- Removed code on BSR/JSR in fetch cycle
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-- Removed code on BSR/JSR in fetch cycle
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity cpu09 is
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entity cpu09 is
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port (
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port (
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clk: in std_logic;
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clk : in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic;
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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addr : out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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rw : out std_logic;
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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firq: in std_logic;
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firq: in std_logic;
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nmi: in std_logic
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nmi : in std_logic;
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halt : in std_logic;
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hold : in std_logic
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);
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);
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end cpu09;
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end cpu09;
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architecture rtl of cpu09 is
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architecture rtl of cpu09 is
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constant EBIT : integer := 7;
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constant EBIT : integer := 7;
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constant FBIT : integer := 6;
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constant FBIT : integer := 6;
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constant HBIT : integer := 5;
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constant HBIT : integer := 5;
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constant IBIT : integer := 4;
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constant IBIT : integer := 4;
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constant NBIT : integer := 3;
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constant NBIT : integer := 3;
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constant ZBIT : integer := 2;
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constant ZBIT : integer := 2;
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constant VBIT : integer := 1;
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constant VBIT : integer := 1;
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constant CBIT : integer := 0;
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constant CBIT : integer := 0;
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--
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--
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-- Interrupt vector modifiers
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-- Interrupt vector modifiers
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--
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--
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constant RST_VEC : std_logic_vector(2 downto 0) := "111";
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constant RST_VEC : std_logic_vector(2 downto 0) := "111";
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constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
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constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
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constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
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constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
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constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
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constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
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constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
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constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
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constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
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constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
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constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
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constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
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constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
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constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
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type state_type is (-- Start off in Reset
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type state_type is (-- Start off in Reset
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reset_state,
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reset_state,
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-- Fetch Interrupt Vectors (including reset)
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-- Fetch Interrupt Vectors (including reset)
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vect_lo_state, vect_hi_state,
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vect_lo_state, vect_hi_state,
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-- Fetch Instruction Cycle
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-- Fetch Instruction Cycle
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fetch_state,
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fetch_state,
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-- Decode Instruction Cycles
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-- Decode Instruction Cycles
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decode1_state, decode2_state, decode3_state,
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decode1_state, decode2_state, decode3_state,
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-- Calculate Effective Address
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-- Calculate Effective Address
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imm16_state,
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imm16_state,
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indexed_state, index8_state, index16_state, index16_2_state,
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indexed_state, index8_state, index16_state, index16_2_state,
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pcrel8_state, pcrel16_state, pcrel16_2_state,
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pcrel8_state, pcrel16_state, pcrel16_2_state,
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indexaddr_state, indexaddr2_state,
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indexaddr_state, indexaddr2_state,
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postincr1_state, postincr2_state,
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postincr1_state, postincr2_state,
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indirect_state, indirect2_state, indirect3_state,
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indirect_state, indirect2_state, indirect3_state,
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extended_state,
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extended_state,
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-- single ops
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-- single ops
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single_op_read_state,
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single_op_read_state,
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single_op_exec_state,
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single_op_exec_state,
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single_op_write_state,
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single_op_write_state,
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-- Dual op states
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-- Dual op states
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dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
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dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
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dual_op_write8_state, dual_op_write16_state,
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dual_op_write8_state, dual_op_write16_state,
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--
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--
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sync_state, halt_state, error_state,
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sync_state, halt_state, error_state,
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--
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--
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andcc_state, orcc_state,
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andcc_state, orcc_state,
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tfr_state, exg_state, exg1_state,
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tfr_state, exg_state, exg1_state,
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lea_state,
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lea_state,
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-- Multiplication
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-- Multiplication
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mul_state, mulea_state, muld_state,
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mul_state, mulea_state, muld_state,
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mul0_state, mul1_state, mul2_state, mul3_state,
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mul0_state, mul1_state, mul2_state, mul3_state,
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mul4_state, mul5_state, mul6_state, mul7_state,
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mul4_state, mul5_state, mul6_state, mul7_state,
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-- Branches
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-- Branches
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lbranch_state, sbranch_state,
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lbranch_state, sbranch_state,
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-- Jumps, Subroutine Calls and Returns
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-- Jumps, Subroutine Calls and Returns
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jsr_state, jmp_state,
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jsr_state, jmp_state,
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push_return_hi_state, push_return_lo_state,
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push_return_hi_state, push_return_lo_state,
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pull_return_hi_state, pull_return_lo_state,
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pull_return_hi_state, pull_return_lo_state,
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-- Interrupt cycles
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-- Interrupt cycles
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int_nmiirq_state, int_firq_state,
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int_nmiirq_state, int_firq_state,
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int_entire_state, int_fast_state,
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int_entire_state, int_fast_state,
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int_pcl_state, int_pch_state,
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int_pcl_state, int_pch_state,
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int_upl_state, int_uph_state,
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int_upl_state, int_uph_state,
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int_iyl_state, int_iyh_state,
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int_iyl_state, int_iyh_state,
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int_ixl_state, int_ixh_state,
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int_ixl_state, int_ixh_state,
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int_dp_state,
|
int_dp_state,
|
int_accb_state, int_acca_state,
|
int_accb_state, int_acca_state,
|
int_cc_state,
|
int_cc_state,
|
int_cwai_state,
|
int_cwai_state,
|
int_maski_state, int_maskif_state,
|
int_maski_state, int_maskif_state,
|
-- Return From Interrupt
|
-- Return From Interrupt
|
rti_cc_state, rti_entire_state,
|
rti_cc_state, rti_entire_state,
|
rti_acca_state, rti_accb_state,
|
rti_acca_state, rti_accb_state,
|
rti_dp_state,
|
rti_dp_state,
|
rti_ixl_state, rti_ixh_state,
|
rti_ixl_state, rti_ixh_state,
|
rti_iyl_state, rti_iyh_state,
|
rti_iyl_state, rti_iyh_state,
|
rti_upl_state, rti_uph_state,
|
rti_upl_state, rti_uph_state,
|
rti_pcl_state, rti_pch_state,
|
rti_pcl_state, rti_pch_state,
|
-- Push Registers using SP
|
-- Push Registers using SP
|
pshs_state,
|
pshs_state,
|
pshs_pcl_state, pshs_pch_state,
|
pshs_pcl_state, pshs_pch_state,
|
pshs_upl_state, pshs_uph_state,
|
pshs_upl_state, pshs_uph_state,
|
pshs_iyl_state, pshs_iyh_state,
|
pshs_iyl_state, pshs_iyh_state,
|
pshs_ixl_state, pshs_ixh_state,
|
pshs_ixl_state, pshs_ixh_state,
|
pshs_dp_state,
|
pshs_dp_state,
|
pshs_acca_state, pshs_accb_state,
|
pshs_acca_state, pshs_accb_state,
|
pshs_cc_state,
|
pshs_cc_state,
|
-- Pull Registers using SP
|
-- Pull Registers using SP
|
puls_state,
|
puls_state,
|
puls_cc_state,
|
puls_cc_state,
|
puls_acca_state, puls_accb_state,
|
puls_acca_state, puls_accb_state,
|
puls_dp_state,
|
puls_dp_state,
|
puls_ixl_state, puls_ixh_state,
|
puls_ixl_state, puls_ixh_state,
|
puls_iyl_state, puls_iyh_state,
|
puls_iyl_state, puls_iyh_state,
|
puls_upl_state, puls_uph_state,
|
puls_upl_state, puls_uph_state,
|
puls_pcl_state, puls_pch_state,
|
puls_pcl_state, puls_pch_state,
|
-- Push Registers using UP
|
-- Push Registers using UP
|
pshu_state,
|
pshu_state,
|
pshu_pcl_state, pshu_pch_state,
|
pshu_pcl_state, pshu_pch_state,
|
pshu_spl_state, pshu_sph_state,
|
pshu_spl_state, pshu_sph_state,
|
pshu_iyl_state, pshu_iyh_state,
|
pshu_iyl_state, pshu_iyh_state,
|
pshu_ixl_state, pshu_ixh_state,
|
pshu_ixl_state, pshu_ixh_state,
|
pshu_dp_state,
|
pshu_dp_state,
|
pshu_acca_state, pshu_accb_state,
|
pshu_acca_state, pshu_accb_state,
|
pshu_cc_state,
|
pshu_cc_state,
|
-- Pull Registers using UP
|
-- Pull Registers using UP
|
pulu_state,
|
pulu_state,
|
pulu_cc_state,
|
pulu_cc_state,
|
pulu_acca_state, pulu_accb_state,
|
pulu_acca_state, pulu_accb_state,
|
pulu_dp_state,
|
pulu_dp_state,
|
pulu_ixl_state, pulu_ixh_state,
|
pulu_ixl_state, pulu_ixh_state,
|
pulu_iyl_state, pulu_iyh_state,
|
pulu_iyl_state, pulu_iyh_state,
|
pulu_spl_state, pulu_sph_state,
|
pulu_spl_state, pulu_sph_state,
|
pulu_pcl_state, pulu_pch_state );
|
pulu_pcl_state, pulu_pch_state );
|
|
|
type stack_type is array(2 downto 0) of state_type;
|
type stack_type is array(2 downto 0) of state_type;
|
type st_type is (idle_st, push_st, pull_st );
|
type st_type is (idle_st, push_st, pull_st );
|
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
|
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
|
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
|
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
|
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
|
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
|
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
|
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
|
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
|
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
|
type op_type is (reset_op, fetch_op, latch_op );
|
type op_type is (reset_op, fetch_op, latch_op );
|
type pre_type is (reset_pre, fetch_pre, latch_pre );
|
type pre_type is (reset_pre, fetch_pre, latch_pre );
|
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
|
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
|
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
|
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
|
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
|
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
|
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
|
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
|
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
|
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
|
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
|
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
|
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
|
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
|
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
|
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
|
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
|
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
|
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
|
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
|
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
|
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
|
type iv_type is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
|
type iv_type is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
|
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
|
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
|
type left_type is (cc_left, acca_left, accb_left, dp_left,
|
type left_type is (cc_left, acca_left, accb_left, dp_left,
|
ix_left, iy_left, up_left, sp_left,
|
ix_left, iy_left, up_left, sp_left,
|
accd_left, md_left, pc_left, ea_left );
|
accd_left, md_left, pc_left, ea_left );
|
type right_type is (ea_right, zero_right, one_right, two_right,
|
type right_type is (ea_right, zero_right, one_right, two_right,
|
acca_right, accb_right, accd_right,
|
acca_right, accb_right, accd_right,
|
md_right, md_sign5_right, md_sign8_right );
|
md_right, md_sign5_right, md_sign8_right );
|
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
|
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
|
alu_and, alu_ora, alu_eor,
|
alu_and, alu_ora, alu_eor,
|
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
|
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
|
alu_lsr16, alu_lsl16,
|
alu_lsr16, alu_lsl16,
|
alu_ror8, alu_rol8, alu_mul,
|
alu_ror8, alu_rol8, alu_mul,
|
alu_asr8, alu_asl8, alu_lsr8,
|
alu_asr8, alu_asl8, alu_lsr8,
|
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
|
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
|
alu_seif, alu_sei, alu_see, alu_cle,
|
alu_seif, alu_sei, alu_see, alu_cle,
|
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
|
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
|
|
|
signal op_code: std_logic_vector(7 downto 0);
|
signal op_code: std_logic_vector(7 downto 0);
|
signal pre_code: std_logic_vector(7 downto 0);
|
signal pre_code: std_logic_vector(7 downto 0);
|
signal acca: std_logic_vector(7 downto 0);
|
signal acca: std_logic_vector(7 downto 0);
|
signal accb: std_logic_vector(7 downto 0);
|
signal accb: std_logic_vector(7 downto 0);
|
signal cc: std_logic_vector(7 downto 0);
|
signal cc: std_logic_vector(7 downto 0);
|
signal cc_out: std_logic_vector(7 downto 0);
|
signal cc_out: std_logic_vector(7 downto 0);
|
signal dp: std_logic_vector(7 downto 0);
|
signal dp: std_logic_vector(7 downto 0);
|
signal xreg: std_logic_vector(15 downto 0);
|
signal xreg: std_logic_vector(15 downto 0);
|
signal yreg: std_logic_vector(15 downto 0);
|
signal yreg: std_logic_vector(15 downto 0);
|
signal sp: std_logic_vector(15 downto 0);
|
signal sp: std_logic_vector(15 downto 0);
|
signal up: std_logic_vector(15 downto 0);
|
signal up: std_logic_vector(15 downto 0);
|
signal ea: std_logic_vector(15 downto 0);
|
signal ea: std_logic_vector(15 downto 0);
|
signal pc: std_logic_vector(15 downto 0);
|
signal pc: std_logic_vector(15 downto 0);
|
signal md: std_logic_vector(15 downto 0);
|
signal md: std_logic_vector(15 downto 0);
|
signal left: std_logic_vector(15 downto 0);
|
signal left: std_logic_vector(15 downto 0);
|
signal right: std_logic_vector(15 downto 0);
|
signal right: std_logic_vector(15 downto 0);
|
signal out_alu: std_logic_vector(15 downto 0);
|
signal out_alu: std_logic_vector(15 downto 0);
|
signal iv: std_logic_vector(2 downto 0);
|
signal iv: std_logic_vector(2 downto 0);
|
signal nmi_req: std_logic;
|
signal nmi_req: std_logic;
|
signal nmi_ack: std_logic;
|
signal nmi_ack: std_logic;
|
signal nmi_enable: std_logic;
|
signal nmi_enable: std_logic;
|
|
|
signal state: state_type;
|
signal state: state_type;
|
signal next_state: state_type;
|
signal next_state: state_type;
|
signal saved_state: state_type;
|
signal saved_state: state_type;
|
signal return_state: state_type;
|
signal return_state: state_type;
|
signal state_stack: stack_type;
|
signal state_stack: stack_type;
|
signal st_ctrl: st_type;
|
signal st_ctrl: st_type;
|
signal pc_ctrl: pc_type;
|
signal pc_ctrl: pc_type;
|
signal ea_ctrl: ea_type;
|
signal ea_ctrl: ea_type;
|
signal op_ctrl: op_type;
|
signal op_ctrl: op_type;
|
signal pre_ctrl: pre_type;
|
signal pre_ctrl: pre_type;
|
signal md_ctrl: md_type;
|
signal md_ctrl: md_type;
|
signal acca_ctrl: acca_type;
|
signal acca_ctrl: acca_type;
|
signal accb_ctrl: accb_type;
|
signal accb_ctrl: accb_type;
|
signal ix_ctrl: ix_type;
|
signal ix_ctrl: ix_type;
|
signal iy_ctrl: iy_type;
|
signal iy_ctrl: iy_type;
|
signal cc_ctrl: cc_type;
|
signal cc_ctrl: cc_type;
|
signal dp_ctrl: dp_type;
|
signal dp_ctrl: dp_type;
|
signal sp_ctrl: sp_type;
|
signal sp_ctrl: sp_type;
|
signal up_ctrl: up_type;
|
signal up_ctrl: up_type;
|
signal iv_ctrl: iv_type;
|
signal iv_ctrl: iv_type;
|
signal left_ctrl: left_type;
|
signal left_ctrl: left_type;
|
signal right_ctrl: right_type;
|
signal right_ctrl: right_type;
|
signal alu_ctrl: alu_type;
|
signal alu_ctrl: alu_type;
|
signal addr_ctrl: addr_type;
|
signal addr_ctrl: addr_type;
|
signal dout_ctrl: dout_type;
|
signal dout_ctrl: dout_type;
|
signal nmi_ctrl: nmi_type;
|
signal nmi_ctrl: nmi_type;
|
|
|
|
|
begin
|
begin
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- State machine stack
|
-- State machine stack
|
--
|
--
|
----------------------------------
|
----------------------------------
|
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
|
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
|
-- return_state, fetch_state )
|
-- return_state, fetch_state )
|
state_stack_proc: process( clk, state_stack )
|
state_stack_proc: process( clk, state_stack )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
state_stack(0) <= state_stack(0);
|
state_stack(0) <= state_stack(0);
|
state_stack(1) <= state_stack(1);
|
state_stack(1) <= state_stack(1);
|
state_stack(2) <= state_stack(2);
|
state_stack(2) <= state_stack(2);
|
else
|
else
|
case st_ctrl is
|
case st_ctrl is
|
when idle_st =>
|
when idle_st =>
|
state_stack(0) <= state_stack(0);
|
state_stack(0) <= state_stack(0);
|
state_stack(1) <= state_stack(1);
|
state_stack(1) <= state_stack(1);
|
state_stack(2) <= state_stack(2);
|
state_stack(2) <= state_stack(2);
|
when push_st =>
|
when push_st =>
|
state_stack(0) <= return_state;
|
state_stack(0) <= return_state;
|
state_stack(1) <= state_stack(0);
|
state_stack(1) <= state_stack(0);
|
state_stack(2) <= state_stack(1);
|
state_stack(2) <= state_stack(1);
|
when pull_st =>
|
when pull_st =>
|
state_stack(0) <= state_stack(1);
|
state_stack(0) <= state_stack(1);
|
state_stack(1) <= state_stack(2);
|
state_stack(1) <= state_stack(2);
|
state_stack(2) <= fetch_state;
|
state_stack(2) <= fetch_state;
|
when others =>
|
when others =>
|
state_stack(0) <= state_stack(0);
|
state_stack(0) <= state_stack(0);
|
state_stack(1) <= state_stack(1);
|
state_stack(1) <= state_stack(1);
|
state_stack(2) <= state_stack(2);
|
state_stack(2) <= state_stack(2);
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
saved_state <= state_stack(0);
|
saved_state <= state_stack(0);
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Program Counter Control
|
-- Program Counter Control
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
|
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
|
pc_reg: process( clk )
|
pc_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
pc <= pc;
|
pc <= pc;
|
else
|
else
|
case pc_ctrl is
|
case pc_ctrl is
|
when reset_pc =>
|
when reset_pc =>
|
pc <= "0000000000000000";
|
pc <= "0000000000000000";
|
when load_pc =>
|
when load_pc =>
|
pc <= out_alu(15 downto 0);
|
pc <= out_alu(15 downto 0);
|
when pull_lo_pc =>
|
when pull_lo_pc =>
|
pc(7 downto 0) <= data_in;
|
pc(7 downto 0) <= data_in;
|
when pull_hi_pc =>
|
when pull_hi_pc =>
|
pc(15 downto 8) <= data_in;
|
pc(15 downto 8) <= data_in;
|
when incr_pc =>
|
when incr_pc =>
|
pc <= pc + 1;
|
pc <= pc + 1;
|
when others =>
|
when others =>
|
-- when latch_pc =>
|
-- when latch_pc =>
|
pc <= pc;
|
pc <= pc;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Effective Address Control
|
-- Effective Address Control
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
|
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
|
ea_reg: process( clk )
|
ea_reg: process( clk )
|
begin
|
begin
|
|
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
ea <= ea;
|
ea <= ea;
|
else
|
else
|
case ea_ctrl is
|
case ea_ctrl is
|
when reset_ea =>
|
when reset_ea =>
|
ea <= "0000000000000000";
|
ea <= "0000000000000000";
|
when fetch_first_ea =>
|
when fetch_first_ea =>
|
ea(7 downto 0) <= data_in;
|
ea(7 downto 0) <= data_in;
|
ea(15 downto 8) <= dp;
|
ea(15 downto 8) <= dp;
|
when fetch_next_ea =>
|
when fetch_next_ea =>
|
ea(15 downto 8) <= ea(7 downto 0);
|
ea(15 downto 8) <= ea(7 downto 0);
|
ea(7 downto 0) <= data_in;
|
ea(7 downto 0) <= data_in;
|
when load_ea =>
|
when load_ea =>
|
ea <= out_alu(15 downto 0);
|
ea <= out_alu(15 downto 0);
|
when others =>
|
when others =>
|
-- when latch_ea =>
|
-- when latch_ea =>
|
ea <= ea;
|
ea <= ea;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- Accumulator A
|
-- Accumulator A
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
|
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
|
acca_reg : process( clk )
|
acca_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
acca <= acca;
|
acca <= acca;
|
else
|
else
|
case acca_ctrl is
|
case acca_ctrl is
|
when reset_acca =>
|
when reset_acca =>
|
acca <= "00000000";
|
acca <= "00000000";
|
when load_acca =>
|
when load_acca =>
|
acca <= out_alu(7 downto 0);
|
acca <= out_alu(7 downto 0);
|
when load_hi_acca =>
|
when load_hi_acca =>
|
acca <= out_alu(15 downto 8);
|
acca <= out_alu(15 downto 8);
|
when pull_acca =>
|
when pull_acca =>
|
acca <= data_in;
|
acca <= data_in;
|
when others =>
|
when others =>
|
-- when latch_acca =>
|
-- when latch_acca =>
|
acca <= acca;
|
acca <= acca;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- Accumulator B
|
-- Accumulator B
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
|
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
|
accb_reg : process( clk )
|
accb_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
accb <= accb;
|
accb <= accb;
|
else
|
else
|
case accb_ctrl is
|
case accb_ctrl is
|
when reset_accb =>
|
when reset_accb =>
|
accb <= "00000000";
|
accb <= "00000000";
|
when load_accb =>
|
when load_accb =>
|
accb <= out_alu(7 downto 0);
|
accb <= out_alu(7 downto 0);
|
when pull_accb =>
|
when pull_accb =>
|
accb <= data_in;
|
accb <= data_in;
|
when others =>
|
when others =>
|
-- when latch_accb =>
|
-- when latch_accb =>
|
accb <= accb;
|
accb <= accb;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- X Index register
|
-- X Index register
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
|
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
|
ix_reg : process( clk )
|
ix_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
xreg <= xreg;
|
xreg <= xreg;
|
else
|
else
|
case ix_ctrl is
|
case ix_ctrl is
|
when reset_ix =>
|
when reset_ix =>
|
xreg <= "0000000000000000";
|
xreg <= "0000000000000000";
|
when load_ix =>
|
when load_ix =>
|
xreg <= out_alu(15 downto 0);
|
xreg <= out_alu(15 downto 0);
|
when pull_hi_ix =>
|
when pull_hi_ix =>
|
xreg(15 downto 8) <= data_in;
|
xreg(15 downto 8) <= data_in;
|
when pull_lo_ix =>
|
when pull_lo_ix =>
|
xreg(7 downto 0) <= data_in;
|
xreg(7 downto 0) <= data_in;
|
when others =>
|
when others =>
|
-- when latch_ix =>
|
-- when latch_ix =>
|
xreg <= xreg;
|
xreg <= xreg;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- Y Index register
|
-- Y Index register
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
|
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
|
iy_reg : process( clk )
|
iy_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
yreg <= yreg;
|
yreg <= yreg;
|
else
|
else
|
case iy_ctrl is
|
case iy_ctrl is
|
when reset_iy =>
|
when reset_iy =>
|
yreg <= "0000000000000000";
|
yreg <= "0000000000000000";
|
when load_iy =>
|
when load_iy =>
|
yreg <= out_alu(15 downto 0);
|
yreg <= out_alu(15 downto 0);
|
when pull_hi_iy =>
|
when pull_hi_iy =>
|
yreg(15 downto 8) <= data_in;
|
yreg(15 downto 8) <= data_in;
|
when pull_lo_iy =>
|
when pull_lo_iy =>
|
yreg(7 downto 0) <= data_in;
|
yreg(7 downto 0) <= data_in;
|
when others =>
|
when others =>
|
-- when latch_iy =>
|
-- when latch_iy =>
|
yreg <= yreg;
|
yreg <= yreg;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- S stack pointer
|
-- S stack pointer
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
|
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
|
sp_reg : process( clk )
|
sp_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
sp <= sp;
|
sp <= sp;
|
nmi_enable <= nmi_enable;
|
nmi_enable <= nmi_enable;
|
else
|
else
|
case sp_ctrl is
|
case sp_ctrl is
|
when reset_sp =>
|
when reset_sp =>
|
sp <= "0000000000000000";
|
sp <= "0000000000000000";
|
nmi_enable <= '0';
|
nmi_enable <= '0';
|
when load_sp =>
|
when load_sp =>
|
sp <= out_alu(15 downto 0);
|
sp <= out_alu(15 downto 0);
|
nmi_enable <= '1';
|
nmi_enable <= '1';
|
when pull_hi_sp =>
|
when pull_hi_sp =>
|
sp(15 downto 8) <= data_in;
|
sp(15 downto 8) <= data_in;
|
nmi_enable <= nmi_enable;
|
nmi_enable <= nmi_enable;
|
when pull_lo_sp =>
|
when pull_lo_sp =>
|
sp(7 downto 0) <= data_in;
|
sp(7 downto 0) <= data_in;
|
nmi_enable <= '1';
|
nmi_enable <= '1';
|
when others =>
|
when others =>
|
-- when latch_sp =>
|
-- when latch_sp =>
|
sp <= sp;
|
sp <= sp;
|
nmi_enable <= nmi_enable;
|
nmi_enable <= nmi_enable;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- U stack pointer
|
-- U stack pointer
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
|
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
|
up_reg : process( clk )
|
up_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
up <= up;
|
up <= up;
|
else
|
else
|
case up_ctrl is
|
case up_ctrl is
|
when reset_up =>
|
when reset_up =>
|
up <= "0000000000000000";
|
up <= "0000000000000000";
|
when load_up =>
|
when load_up =>
|
up <= out_alu(15 downto 0);
|
up <= out_alu(15 downto 0);
|
when pull_hi_up =>
|
when pull_hi_up =>
|
up(15 downto 8) <= data_in;
|
up(15 downto 8) <= data_in;
|
when pull_lo_up =>
|
when pull_lo_up =>
|
up(7 downto 0) <= data_in;
|
up(7 downto 0) <= data_in;
|
when others =>
|
when others =>
|
-- when latch_up =>
|
-- when latch_up =>
|
up <= up;
|
up <= up;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- Memory Data
|
-- Memory Data
|
--
|
--
|
--------------------------------
|
--------------------------------
|
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
|
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
|
md_reg : process( clk )
|
md_reg : process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
md <= md;
|
md <= md;
|
else
|
else
|
case md_ctrl is
|
case md_ctrl is
|
when reset_md =>
|
when reset_md =>
|
md <= "0000000000000000";
|
md <= "0000000000000000";
|
when load_md =>
|
when load_md =>
|
md <= out_alu(15 downto 0);
|
md <= out_alu(15 downto 0);
|
when fetch_first_md => -- sign extend md for branches
|
when fetch_first_md => -- sign extend md for branches
|
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
|
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
|
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
|
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
|
md(7 downto 0) <= data_in;
|
md(7 downto 0) <= data_in;
|
when fetch_next_md =>
|
when fetch_next_md =>
|
md(15 downto 8) <= md(7 downto 0);
|
md(15 downto 8) <= md(7 downto 0);
|
md(7 downto 0) <= data_in;
|
md(7 downto 0) <= data_in;
|
when shiftl_md =>
|
when shiftl_md =>
|
md(15 downto 1) <= md(14 downto 0);
|
md(15 downto 1) <= md(14 downto 0);
|
md(0) <= '0';
|
md(0) <= '0';
|
when others =>
|
when others =>
|
-- when latch_md =>
|
-- when latch_md =>
|
md <= md;
|
md <= md;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Condition Codes
|
-- Condition Codes
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
|
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
|
cc_reg: process( clk )
|
cc_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
cc <= cc;
|
cc <= cc;
|
else
|
else
|
case cc_ctrl is
|
case cc_ctrl is
|
when reset_cc =>
|
when reset_cc =>
|
cc <= "11010000"; -- set EBIT, FBIT & IBIT
|
cc <= "11010000"; -- set EBIT, FBIT & IBIT
|
when load_cc =>
|
when load_cc =>
|
cc <= cc_out;
|
cc <= cc_out;
|
when pull_cc =>
|
when pull_cc =>
|
cc <= data_in;
|
cc <= data_in;
|
when others =>
|
when others =>
|
-- when latch_cc =>
|
-- when latch_cc =>
|
cc <= cc;
|
cc <= cc;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Direct Page register
|
-- Direct Page register
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
|
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
|
dp_reg: process( clk )
|
dp_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
dp <= dp;
|
dp <= dp;
|
else
|
else
|
case dp_ctrl is
|
case dp_ctrl is
|
when reset_dp =>
|
when reset_dp =>
|
dp <= "00000000";
|
dp <= "00000000";
|
when load_dp =>
|
when load_dp =>
|
dp <= out_alu(7 downto 0);
|
dp <= out_alu(7 downto 0);
|
when pull_dp =>
|
when pull_dp =>
|
dp <= data_in;
|
dp <= data_in;
|
when others =>
|
when others =>
|
-- when latch_dp =>
|
-- when latch_dp =>
|
dp <= dp;
|
dp <= dp;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- interrupt vector
|
-- interrupt vector
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--iv_mux: process( clk, iv_ctrl, hold, iv )
|
--iv_mux: process( clk, iv_ctrl, hold, iv )
|
iv_mux: process( clk )
|
iv_mux: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
iv <= iv;
|
iv <= iv;
|
else
|
else
|
case iv_ctrl is
|
case iv_ctrl is
|
when reset_iv =>
|
when reset_iv =>
|
iv <= RST_VEC;
|
iv <= RST_VEC;
|
when nmi_iv =>
|
when nmi_iv =>
|
iv <= NMI_VEC;
|
iv <= NMI_VEC;
|
when swi_iv =>
|
when swi_iv =>
|
iv <= SWI_VEC;
|
iv <= SWI_VEC;
|
when irq_iv =>
|
when irq_iv =>
|
iv <= IRQ_VEC;
|
iv <= IRQ_VEC;
|
when firq_iv =>
|
when firq_iv =>
|
iv <= FIRQ_VEC;
|
iv <= FIRQ_VEC;
|
when swi2_iv =>
|
when swi2_iv =>
|
iv <= SWI2_VEC;
|
iv <= SWI2_VEC;
|
when swi3_iv =>
|
when swi3_iv =>
|
iv <= SWI3_VEC;
|
iv <= SWI3_VEC;
|
when resv_iv =>
|
when resv_iv =>
|
iv <= RESV_VEC;
|
iv <= RESV_VEC;
|
when others =>
|
when others =>
|
iv <= iv;
|
iv <= iv;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- op code register
|
-- op code register
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
|
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
|
op_reg: process( clk )
|
op_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
op_code <= op_code;
|
op_code <= op_code;
|
else
|
else
|
case op_ctrl is
|
case op_ctrl is
|
when reset_op =>
|
when reset_op =>
|
op_code <= "00010010";
|
op_code <= "00010010";
|
when fetch_op =>
|
when fetch_op =>
|
op_code <= data_in;
|
op_code <= data_in;
|
when others =>
|
when others =>
|
-- when latch_op =>
|
-- when latch_op =>
|
op_code <= op_code;
|
op_code <= op_code;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- pre byte op code register
|
-- pre byte op code register
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
|
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
|
pre_reg: process( clk )
|
pre_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if hold= '1' then
|
if hold= '1' then
|
pre_code <= pre_code;
|
pre_code <= pre_code;
|
else
|
else
|
case pre_ctrl is
|
case pre_ctrl is
|
when reset_pre =>
|
when reset_pre =>
|
pre_code <= "00000000";
|
pre_code <= "00000000";
|
when fetch_pre =>
|
when fetch_pre =>
|
pre_code <= data_in;
|
pre_code <= data_in;
|
when others =>
|
when others =>
|
-- when latch_pre =>
|
-- when latch_pre =>
|
pre_code <= pre_code;
|
pre_code <= pre_code;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- state machine
|
-- state machine
|
--
|
--
|
--------------------------------
|
--------------------------------
|
|
|
--change_state: process( clk, rst, state, hold, next_state )
|
--change_state: process( clk, rst, state, hold, next_state )
|
change_state: process( clk )
|
change_state: process( clk )
|
begin
|
begin
|
if clk'event and clk = '0' then
|
if clk'event and clk = '0' then
|
if rst = '1' then
|
if rst = '1' then
|
state <= reset_state;
|
state <= reset_state;
|
else
|
else
|
if hold = '1' then
|
if hold = '1' then
|
state <= state;
|
state <= state;
|
else
|
else
|
state <= next_state;
|
state <= next_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
-- output
|
-- output
|
|
|
------------------------------------
|
------------------------------------
|
--
|
--
|
-- Nmi register
|
-- Nmi register
|
--
|
--
|
------------------------------------
|
------------------------------------
|
|
|
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
|
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
|
nmi_reg: process( clk )
|
nmi_reg: process( clk )
|
begin
|
begin
|
if clk'event and clk='0' then
|
if clk'event and clk='0' then
|
if hold = '1' then
|
if hold = '1' then
|
nmi_ack <= nmi_ack;
|
nmi_ack <= nmi_ack;
|
else
|
else
|
case nmi_ctrl is
|
case nmi_ctrl is
|
when set_nmi =>
|
when set_nmi =>
|
nmi_ack <= '1';
|
nmi_ack <= '1';
|
when reset_nmi =>
|
when reset_nmi =>
|
nmi_ack <= '0';
|
nmi_ack <= '0';
|
when others =>
|
when others =>
|
-- when latch_nmi =>
|
-- when latch_nmi =>
|
nmi_ack <= nmi_ack;
|
nmi_ack <= nmi_ack;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
------------------------------------
|
------------------------------------
|
--
|
--
|
-- Detect Edge of NMI interrupt
|
-- Detect Edge of NMI interrupt
|
--
|
--
|
------------------------------------
|
------------------------------------
|
|
|
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
|
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
|
nmi_handler : process( clk )
|
nmi_handler : process( rst, clk )
|
begin
|
begin
|
if clk'event and clk='0' then
|
|
if rst='1' then
|
if rst='1' then
|
nmi_req <= '0';
|
nmi_req <= '0';
|
else
|
elsif clk'event and clk='0' then
|
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
|
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
|
nmi_req <= '1';
|
nmi_req <= '1';
|
else
|
else
|
if (nmi='0') and (nmi_ack='1') then
|
if (nmi='0') and (nmi_ack='1') then
|
nmi_req <= '0';
|
nmi_req <= '0';
|
else
|
|
nmi_req <= nmi_req;
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Address output multiplexer
|
-- Address output multiplexer
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
|
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
|
begin
|
begin
|
case addr_ctrl is
|
case addr_ctrl is
|
when idle_ad =>
|
when idle_ad =>
|
address <= "1111111111111111";
|
|
vma <= '0';
|
vma <= '0';
|
|
addr <= "1111111111111111";
|
rw <= '1';
|
rw <= '1';
|
when fetch_ad =>
|
when fetch_ad =>
|
address <= pc;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= pc;
|
rw <= '1';
|
rw <= '1';
|
when read_ad =>
|
when read_ad =>
|
address <= ea;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= ea;
|
rw <= '1';
|
rw <= '1';
|
when write_ad =>
|
when write_ad =>
|
address <= ea;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= ea;
|
rw <= '0';
|
rw <= '0';
|
when pushs_ad =>
|
when pushs_ad =>
|
address <= sp;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= sp;
|
rw <= '0';
|
rw <= '0';
|
when pulls_ad =>
|
when pulls_ad =>
|
address <= sp;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= sp;
|
rw <= '1';
|
rw <= '1';
|
when pushu_ad =>
|
when pushu_ad =>
|
address <= up;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= up;
|
rw <= '0';
|
rw <= '0';
|
when pullu_ad =>
|
when pullu_ad =>
|
address <= up;
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= up;
|
rw <= '1';
|
rw <= '1';
|
when int_hi_ad =>
|
when int_hi_ad =>
|
address <= "111111111111" & iv & "0";
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= "111111111111" & iv & "0";
|
rw <= '1';
|
rw <= '1';
|
when int_lo_ad =>
|
when int_lo_ad =>
|
address <= "111111111111" & iv & "1";
|
|
vma <= '1';
|
vma <= '1';
|
|
addr <= "111111111111" & iv & "1";
|
rw <= '1';
|
rw <= '1';
|
when others =>
|
when others =>
|
address <= "1111111111111111";
|
|
vma <= '0';
|
vma <= '0';
|
|
addr <= "1111111111111111";
|
rw <= '1';
|
rw <= '1';
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
--------------------------------
|
--------------------------------
|
--
|
--
|
-- Data Bus output
|
-- Data Bus output
|
--
|
--
|
--------------------------------
|
--------------------------------
|
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
|
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
|
begin
|
begin
|
case dout_ctrl is
|
case dout_ctrl is
|
when cc_dout => -- condition code register
|
when cc_dout => -- condition code register
|
data_out <= cc;
|
data_out <= cc;
|
when acca_dout => -- accumulator a
|
when acca_dout => -- accumulator a
|
data_out <= acca;
|
data_out <= acca;
|
when accb_dout => -- accumulator b
|
when accb_dout => -- accumulator b
|
data_out <= accb;
|
data_out <= accb;
|
when dp_dout => -- direct page register
|
when dp_dout => -- direct page register
|
data_out <= dp;
|
data_out <= dp;
|
when ix_lo_dout => -- X index reg
|
when ix_lo_dout => -- X index reg
|
data_out <= xreg(7 downto 0);
|
data_out <= xreg(7 downto 0);
|
when ix_hi_dout => -- X index reg
|
when ix_hi_dout => -- X index reg
|
data_out <= xreg(15 downto 8);
|
data_out <= xreg(15 downto 8);
|
when iy_lo_dout => -- Y index reg
|
when iy_lo_dout => -- Y index reg
|
data_out <= yreg(7 downto 0);
|
data_out <= yreg(7 downto 0);
|
when iy_hi_dout => -- Y index reg
|
when iy_hi_dout => -- Y index reg
|
data_out <= yreg(15 downto 8);
|
data_out <= yreg(15 downto 8);
|
when up_lo_dout => -- U stack pointer
|
when up_lo_dout => -- U stack pointer
|
data_out <= up(7 downto 0);
|
data_out <= up(7 downto 0);
|
when up_hi_dout => -- U stack pointer
|
when up_hi_dout => -- U stack pointer
|
data_out <= up(15 downto 8);
|
data_out <= up(15 downto 8);
|
when sp_lo_dout => -- S stack pointer
|
when sp_lo_dout => -- S stack pointer
|
data_out <= sp(7 downto 0);
|
data_out <= sp(7 downto 0);
|
when sp_hi_dout => -- S stack pointer
|
when sp_hi_dout => -- S stack pointer
|
data_out <= sp(15 downto 8);
|
data_out <= sp(15 downto 8);
|
when md_lo_dout => -- alu output
|
when md_lo_dout => -- alu output
|
data_out <= md(7 downto 0);
|
data_out <= md(7 downto 0);
|
when md_hi_dout => -- alu output
|
when md_hi_dout => -- alu output
|
data_out <= md(15 downto 8);
|
data_out <= md(15 downto 8);
|
when pc_lo_dout => -- low order pc
|
when pc_lo_dout => -- low order pc
|
data_out <= pc(7 downto 0);
|
data_out <= pc(7 downto 0);
|
when pc_hi_dout => -- high order pc
|
when pc_hi_dout => -- high order pc
|
data_out <= pc(15 downto 8);
|
data_out <= pc(15 downto 8);
|
when others =>
|
when others =>
|
data_out <= "00000000";
|
data_out <= "00000000";
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Left Mux
|
-- Left Mux
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
|
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
|
begin
|
begin
|
case left_ctrl is
|
case left_ctrl is
|
when cc_left =>
|
when cc_left =>
|
left(15 downto 8) <= "00000000";
|
left(15 downto 8) <= "00000000";
|
left(7 downto 0) <= cc;
|
left(7 downto 0) <= cc;
|
when acca_left =>
|
when acca_left =>
|
left(15 downto 8) <= "00000000";
|
left(15 downto 8) <= "00000000";
|
left(7 downto 0) <= acca;
|
left(7 downto 0) <= acca;
|
when accb_left =>
|
when accb_left =>
|
left(15 downto 8) <= "00000000";
|
left(15 downto 8) <= "00000000";
|
left(7 downto 0) <= accb;
|
left(7 downto 0) <= accb;
|
when dp_left =>
|
when dp_left =>
|
left(15 downto 8) <= "00000000";
|
left(15 downto 8) <= "00000000";
|
left(7 downto 0) <= dp;
|
left(7 downto 0) <= dp;
|
when accd_left =>
|
when accd_left =>
|
left(15 downto 8) <= acca;
|
left(15 downto 8) <= acca;
|
left(7 downto 0) <= accb;
|
left(7 downto 0) <= accb;
|
when md_left =>
|
when md_left =>
|
left <= md;
|
left <= md;
|
when ix_left =>
|
when ix_left =>
|
left <= xreg;
|
left <= xreg;
|
when iy_left =>
|
when iy_left =>
|
left <= yreg;
|
left <= yreg;
|
when sp_left =>
|
when sp_left =>
|
left <= sp;
|
left <= sp;
|
when up_left =>
|
when up_left =>
|
left <= up;
|
left <= up;
|
when pc_left =>
|
when pc_left =>
|
left <= pc;
|
left <= pc;
|
when others =>
|
when others =>
|
-- when ea_left =>
|
-- when ea_left =>
|
left <= ea;
|
left <= ea;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Right Mux
|
-- Right Mux
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
right_mux: process( right_ctrl, md, acca, accb, ea )
|
right_mux: process( right_ctrl, md, acca, accb, ea )
|
begin
|
begin
|
case right_ctrl is
|
case right_ctrl is
|
when ea_right =>
|
when ea_right =>
|
right <= ea;
|
right <= ea;
|
when zero_right =>
|
when zero_right =>
|
right <= "0000000000000000";
|
right <= "0000000000000000";
|
when one_right =>
|
when one_right =>
|
right <= "0000000000000001";
|
right <= "0000000000000001";
|
when two_right =>
|
when two_right =>
|
right <= "0000000000000010";
|
right <= "0000000000000010";
|
when acca_right =>
|
when acca_right =>
|
if acca(7) = '0' then
|
if acca(7) = '0' then
|
right <= "00000000" & acca(7 downto 0);
|
right <= "00000000" & acca(7 downto 0);
|
else
|
else
|
right <= "11111111" & acca(7 downto 0);
|
right <= "11111111" & acca(7 downto 0);
|
end if;
|
end if;
|
when accb_right =>
|
when accb_right =>
|
if accb(7) = '0' then
|
if accb(7) = '0' then
|
right <= "00000000" & accb(7 downto 0);
|
right <= "00000000" & accb(7 downto 0);
|
else
|
else
|
right <= "11111111" & accb(7 downto 0);
|
right <= "11111111" & accb(7 downto 0);
|
end if;
|
end if;
|
when accd_right =>
|
when accd_right =>
|
right <= acca & accb;
|
right <= acca & accb;
|
when md_sign5_right =>
|
when md_sign5_right =>
|
if md(4) = '0' then
|
if md(4) = '0' then
|
right <= "00000000000" & md(4 downto 0);
|
right <= "00000000000" & md(4 downto 0);
|
else
|
else
|
right <= "11111111111" & md(4 downto 0);
|
right <= "11111111111" & md(4 downto 0);
|
end if;
|
end if;
|
when md_sign8_right =>
|
when md_sign8_right =>
|
if md(7) = '0' then
|
if md(7) = '0' then
|
right <= "00000000" & md(7 downto 0);
|
right <= "00000000" & md(7 downto 0);
|
else
|
else
|
right <= "11111111" & md(7 downto 0);
|
right <= "11111111" & md(7 downto 0);
|
end if;
|
end if;
|
when others =>
|
when others =>
|
-- when md_right =>
|
-- when md_right =>
|
right <= md;
|
right <= md;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
----------------------------------
|
----------------------------------
|
--
|
--
|
-- Arithmetic Logic Unit
|
-- Arithmetic Logic Unit
|
--
|
--
|
----------------------------------
|
----------------------------------
|
|
|
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
|
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
|
variable valid_lo, valid_hi : boolean;
|
variable valid_lo, valid_hi : boolean;
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable daa_reg : std_logic_vector(7 downto 0);
|
variable daa_reg : std_logic_vector(7 downto 0);
|
begin
|
begin
|
|
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_adc | alu_sbc |
|
when alu_adc | alu_sbc |
|
alu_rol8 | alu_ror8 =>
|
alu_rol8 | alu_ror8 =>
|
carry_in := cc(CBIT);
|
carry_in := cc(CBIT);
|
when alu_asr8 =>
|
when alu_asr8 =>
|
carry_in := left(7);
|
carry_in := left(7);
|
when others =>
|
when others =>
|
carry_in := '0';
|
carry_in := '0';
|
end case;
|
end case;
|
|
|
valid_lo := left(3 downto 0) <= 9;
|
valid_lo := left(3 downto 0) <= 9;
|
valid_hi := left(7 downto 4) <= 9;
|
valid_hi := left(7 downto 4) <= 9;
|
|
|
if (cc(CBIT) = '0') then
|
if (cc(CBIT) = '0') then
|
if( cc(HBIT) = '1' ) then
|
if( cc(HBIT) = '1' ) then
|
if valid_hi then
|
if valid_hi then
|
daa_reg := "00000110";
|
daa_reg := "00000110";
|
else
|
else
|
daa_reg := "01100110";
|
daa_reg := "01100110";
|
end if;
|
end if;
|
else
|
else
|
if valid_lo then
|
if valid_lo then
|
if valid_hi then
|
if valid_hi then
|
daa_reg := "00000000";
|
daa_reg := "00000000";
|
else
|
else
|
daa_reg := "01100000";
|
daa_reg := "01100000";
|
end if;
|
end if;
|
else
|
else
|
if( left(7 downto 4) <= 8 ) then
|
if( left(7 downto 4) <= 8 ) then
|
daa_reg := "00000110";
|
daa_reg := "00000110";
|
else
|
else
|
daa_reg := "01100110";
|
daa_reg := "01100110";
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
if ( cc(HBIT) = '1' )then
|
if ( cc(HBIT) = '1' )then
|
daa_reg := "01100110";
|
daa_reg := "01100110";
|
else
|
else
|
if valid_lo then
|
if valid_lo then
|
daa_reg := "01100000";
|
daa_reg := "01100000";
|
else
|
else
|
daa_reg := "01100110";
|
daa_reg := "01100110";
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_inc |
|
when alu_add8 | alu_inc |
|
alu_add16 | alu_adc | alu_mul =>
|
alu_add16 | alu_adc | alu_mul =>
|
out_alu <= left + right + ("000000000000000" & carry_in);
|
out_alu <= left + right + ("000000000000000" & carry_in);
|
when alu_sub8 | alu_dec |
|
when alu_sub8 | alu_dec |
|
alu_sub16 | alu_sbc =>
|
alu_sub16 | alu_sbc =>
|
out_alu <= left - right - ("000000000000000" & carry_in);
|
out_alu <= left - right - ("000000000000000" & carry_in);
|
when alu_abx =>
|
when alu_abx =>
|
out_alu <= left + ("00000000" & right(7 downto 0)) ;
|
out_alu <= left + ("00000000" & right(7 downto 0)) ;
|
when alu_and =>
|
when alu_and =>
|
out_alu <= left and right; -- and/bit
|
out_alu <= left and right; -- and/bit
|
when alu_ora =>
|
when alu_ora =>
|
out_alu <= left or right; -- or
|
out_alu <= left or right; -- or
|
when alu_eor =>
|
when alu_eor =>
|
out_alu <= left xor right; -- eor/xor
|
out_alu <= left xor right; -- eor/xor
|
when alu_lsl16 | alu_asl8 | alu_rol8 =>
|
when alu_lsl16 | alu_asl8 | alu_rol8 =>
|
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
|
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
|
when alu_lsr16 =>
|
when alu_lsr16 =>
|
out_alu <= carry_in & left(15 downto 1); -- lsr16
|
out_alu <= carry_in & left(15 downto 1); -- lsr16
|
when alu_lsr8 | alu_asr8 | alu_ror8 =>
|
when alu_lsr8 | alu_asr8 | alu_ror8 =>
|
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
|
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
|
when alu_neg =>
|
when alu_neg =>
|
out_alu <= right - left; -- neg (right=0)
|
out_alu <= right - left; -- neg (right=0)
|
when alu_com =>
|
when alu_com =>
|
out_alu <= not left;
|
out_alu <= not left;
|
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
|
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
|
out_alu <= right; -- clr, ld
|
out_alu <= right; -- clr, ld
|
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
|
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
|
out_alu <= left;
|
out_alu <= left;
|
when alu_daa =>
|
when alu_daa =>
|
out_alu <= left + ("00000000" & daa_reg);
|
out_alu <= left + ("00000000" & daa_reg);
|
when alu_sex =>
|
when alu_sex =>
|
if left(7) = '0' then
|
if left(7) = '0' then
|
out_alu <= "00000000" & left(7 downto 0);
|
out_alu <= "00000000" & left(7 downto 0);
|
else
|
else
|
out_alu <= "11111111" & left(7 downto 0);
|
out_alu <= "11111111" & left(7 downto 0);
|
end if;
|
end if;
|
when others =>
|
when others =>
|
out_alu <= left; -- nop
|
out_alu <= left; -- nop
|
end case;
|
end case;
|
|
|
--
|
--
|
-- carry bit
|
-- carry bit
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_adc =>
|
when alu_add8 | alu_adc =>
|
cc_out(CBIT) <= (left(7) and right(7)) or
|
cc_out(CBIT) <= (left(7) and right(7)) or
|
(left(7) and not out_alu(7)) or
|
(left(7) and not out_alu(7)) or
|
(right(7) and not out_alu(7));
|
(right(7) and not out_alu(7));
|
when alu_sub8 | alu_sbc =>
|
when alu_sub8 | alu_sbc =>
|
cc_out(CBIT) <= ((not left(7)) and right(7)) or
|
cc_out(CBIT) <= ((not left(7)) and right(7)) or
|
((not left(7)) and out_alu(7)) or
|
((not left(7)) and out_alu(7)) or
|
(right(7) and out_alu(7));
|
(right(7) and out_alu(7));
|
when alu_add16 =>
|
when alu_add16 =>
|
cc_out(CBIT) <= (left(15) and right(15)) or
|
cc_out(CBIT) <= (left(15) and right(15)) or
|
(left(15) and not out_alu(15)) or
|
(left(15) and not out_alu(15)) or
|
(right(15) and not out_alu(15));
|
(right(15) and not out_alu(15));
|
when alu_sub16 =>
|
when alu_sub16 =>
|
cc_out(CBIT) <= ((not left(15)) and right(15)) or
|
cc_out(CBIT) <= ((not left(15)) and right(15)) or
|
((not left(15)) and out_alu(15)) or
|
((not left(15)) and out_alu(15)) or
|
(right(15) and out_alu(15));
|
(right(15) and out_alu(15));
|
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
|
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
|
cc_out(CBIT) <= left(0);
|
cc_out(CBIT) <= left(0);
|
when alu_rol8 | alu_asl8 =>
|
when alu_rol8 | alu_asl8 =>
|
cc_out(CBIT) <= left(7);
|
cc_out(CBIT) <= left(7);
|
when alu_lsl16 =>
|
when alu_lsl16 =>
|
cc_out(CBIT) <= left(15);
|
cc_out(CBIT) <= left(15);
|
when alu_com =>
|
when alu_com =>
|
cc_out(CBIT) <= '1';
|
cc_out(CBIT) <= '1';
|
when alu_neg | alu_clr =>
|
when alu_neg | alu_clr =>
|
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
|
when alu_mul =>
|
when alu_mul =>
|
cc_out(CBIT) <= out_alu(7);
|
cc_out(CBIT) <= out_alu(7);
|
when alu_daa =>
|
when alu_daa =>
|
if ( daa_reg(7 downto 4) = "0110" ) then
|
if ( daa_reg(7 downto 4) = "0110" ) then
|
cc_out(CBIT) <= '1';
|
cc_out(CBIT) <= '1';
|
else
|
else
|
cc_out(CBIT) <= '0';
|
cc_out(CBIT) <= '0';
|
end if;
|
end if;
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
|
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
|
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(CBIT) <= left(CBIT);
|
cc_out(CBIT) <= left(CBIT);
|
when others =>
|
when others =>
|
cc_out(CBIT) <= cc(CBIT);
|
cc_out(CBIT) <= cc(CBIT);
|
end case;
|
end case;
|
--
|
--
|
-- Zero flag
|
-- Zero flag
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_sub8 |
|
when alu_add8 | alu_sub8 |
|
alu_adc | alu_sbc |
|
alu_adc | alu_sbc |
|
alu_and | alu_ora | alu_eor |
|
alu_and | alu_ora | alu_eor |
|
alu_inc | alu_dec |
|
alu_inc | alu_dec |
|
alu_neg | alu_com | alu_clr |
|
alu_neg | alu_com | alu_clr |
|
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
|
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
|
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
|
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
|
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
|
when alu_add16 | alu_sub16 | alu_mul |
|
when alu_add16 | alu_sub16 | alu_mul |
|
alu_lsl16 | alu_lsr16 |
|
alu_lsl16 | alu_lsr16 |
|
alu_ld16 | alu_st16 | alu_lea =>
|
alu_ld16 | alu_st16 | alu_lea =>
|
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
|
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
|
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
|
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
|
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
|
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
|
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
|
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(ZBIT) <= left(ZBIT);
|
cc_out(ZBIT) <= left(ZBIT);
|
when others =>
|
when others =>
|
cc_out(ZBIT) <= cc(ZBIT);
|
cc_out(ZBIT) <= cc(ZBIT);
|
end case;
|
end case;
|
|
|
--
|
--
|
-- negative flag
|
-- negative flag
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_sub8 |
|
when alu_add8 | alu_sub8 |
|
alu_adc | alu_sbc |
|
alu_adc | alu_sbc |
|
alu_and | alu_ora | alu_eor |
|
alu_and | alu_ora | alu_eor |
|
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
|
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
|
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
|
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
|
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
|
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
|
cc_out(NBIT) <= out_alu(7);
|
cc_out(NBIT) <= out_alu(7);
|
when alu_add16 | alu_sub16 |
|
when alu_add16 | alu_sub16 |
|
alu_lsl16 | alu_lsr16 |
|
alu_lsl16 | alu_lsr16 |
|
alu_ld16 | alu_st16 =>
|
alu_ld16 | alu_st16 =>
|
cc_out(NBIT) <= out_alu(15);
|
cc_out(NBIT) <= out_alu(15);
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
|
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
|
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(NBIT) <= left(NBIT);
|
cc_out(NBIT) <= left(NBIT);
|
when others =>
|
when others =>
|
cc_out(NBIT) <= cc(NBIT);
|
cc_out(NBIT) <= cc(NBIT);
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Interrupt mask flag
|
-- Interrupt mask flag
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
|
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
|
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(IBIT) <= left(IBIT);
|
cc_out(IBIT) <= left(IBIT);
|
when alu_seif | alu_sei =>
|
when alu_seif | alu_sei =>
|
cc_out(IBIT) <= '1';
|
cc_out(IBIT) <= '1';
|
when others =>
|
when others =>
|
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
|
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Half Carry flag
|
-- Half Carry flag
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_adc =>
|
when alu_add8 | alu_adc =>
|
cc_out(HBIT) <= (left(3) and right(3)) or
|
cc_out(HBIT) <= (left(3) and right(3)) or
|
(right(3) and not out_alu(3)) or
|
(right(3) and not out_alu(3)) or
|
(left(3) and not out_alu(3));
|
(left(3) and not out_alu(3));
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
|
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
|
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(HBIT) <= left(HBIT);
|
cc_out(HBIT) <= left(HBIT);
|
when others =>
|
when others =>
|
cc_out(HBIT) <= cc(HBIT);
|
cc_out(HBIT) <= cc(HBIT);
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Overflow flag
|
-- Overflow flag
|
--
|
--
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_add8 | alu_adc =>
|
when alu_add8 | alu_adc =>
|
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
|
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
|
((not left(7)) and (not right(7)) and out_alu(7));
|
((not left(7)) and (not right(7)) and out_alu(7));
|
when alu_sub8 | alu_sbc =>
|
when alu_sub8 | alu_sbc =>
|
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
|
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
|
((not left(7)) and right(7) and out_alu(7));
|
((not left(7)) and right(7) and out_alu(7));
|
when alu_add16 =>
|
when alu_add16 =>
|
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
|
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
|
((not left(15)) and (not right(15)) and out_alu(15));
|
((not left(15)) and (not right(15)) and out_alu(15));
|
when alu_sub16 =>
|
when alu_sub16 =>
|
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
|
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
|
((not left(15)) and right(15) and out_alu(15));
|
((not left(15)) and right(15) and out_alu(15));
|
when alu_inc =>
|
when alu_inc =>
|
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
|
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
|
left(3) and left(2) and left(1) and left(0));
|
left(3) and left(2) and left(1) and left(0));
|
when alu_dec | alu_neg =>
|
when alu_dec | alu_neg =>
|
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
|
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
|
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
|
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
|
-- 6809 Programming reference manual says
|
-- 6809 Programming reference manual says
|
-- V not affected by ASR, LSR and ROR
|
-- V not affected by ASR, LSR and ROR
|
-- This is different to the 6800
|
-- This is different to the 6800
|
-- John Kent 6th June 2006
|
-- John Kent 6th June 2006
|
-- when alu_asr8 =>
|
-- when alu_asr8 =>
|
-- cc_out(VBIT) <= left(0) xor left(7);
|
-- cc_out(VBIT) <= left(0) xor left(7);
|
-- when alu_lsr8 | alu_lsr16 =>
|
-- when alu_lsr8 | alu_lsr16 =>
|
-- cc_out(VBIT) <= left(0);
|
-- cc_out(VBIT) <= left(0);
|
-- when alu_ror8 =>
|
-- when alu_ror8 =>
|
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
|
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
|
when alu_lsl16 =>
|
when alu_lsl16 =>
|
cc_out(VBIT) <= left(15) xor left(14);
|
cc_out(VBIT) <= left(15) xor left(14);
|
when alu_rol8 | alu_asl8 =>
|
when alu_rol8 | alu_asl8 =>
|
cc_out(VBIT) <= left(7) xor left(6);
|
cc_out(VBIT) <= left(7) xor left(6);
|
--
|
--
|
-- 11th July 2006 - John Kent
|
-- 11th July 2006 - John Kent
|
-- What DAA does with V is anyones guess
|
-- What DAA does with V is anyones guess
|
-- It is undefined in the 6809 programming manual
|
-- It is undefined in the 6809 programming manual
|
--
|
--
|
when alu_daa =>
|
when alu_daa =>
|
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
|
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
|
-- CLR resets V Bit
|
-- CLR resets V Bit
|
-- John Kent 6th June 2006
|
-- John Kent 6th June 2006
|
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
|
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
|
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
|
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
|
cc_out(VBIT) <= '0';
|
cc_out(VBIT) <= '0';
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
|
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
|
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(VBIT) <= left(VBIT);
|
cc_out(VBIT) <= left(VBIT);
|
when others =>
|
when others =>
|
cc_out(VBIT) <= cc(VBIT);
|
cc_out(VBIT) <= cc(VBIT);
|
end case;
|
end case;
|
|
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
|
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
|
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(FBIT) <= left(FBIT);
|
cc_out(FBIT) <= left(FBIT);
|
when alu_seif =>
|
when alu_seif =>
|
cc_out(FBIT) <= '1';
|
cc_out(FBIT) <= '1';
|
when others =>
|
when others =>
|
cc_out(FBIT) <= cc(FBIT);
|
cc_out(FBIT) <= cc(FBIT);
|
end case;
|
end case;
|
|
|
case alu_ctrl is
|
case alu_ctrl is
|
when alu_andcc =>
|
when alu_andcc =>
|
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
|
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
|
when alu_orcc =>
|
when alu_orcc =>
|
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
|
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
|
when alu_tfr =>
|
when alu_tfr =>
|
cc_out(EBIT) <= left(EBIT);
|
cc_out(EBIT) <= left(EBIT);
|
when alu_see =>
|
when alu_see =>
|
cc_out(EBIT) <= '1';
|
cc_out(EBIT) <= '1';
|
when alu_cle =>
|
when alu_cle =>
|
cc_out(EBIT) <= '0';
|
cc_out(EBIT) <= '0';
|
when others =>
|
when others =>
|
cc_out(EBIT) <= cc(EBIT);
|
cc_out(EBIT) <= cc(EBIT);
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
------------------------------------
|
------------------------------------
|
--
|
--
|
-- state sequencer
|
-- state sequencer
|
--
|
--
|
------------------------------------
|
------------------------------------
|
process( state, saved_state,
|
process( state, saved_state,
|
op_code, pre_code,
|
op_code, pre_code,
|
cc, ea, md, iv,
|
cc, ea, md, iv,
|
irq, firq, nmi_req, nmi_ack, halt )
|
irq, firq, nmi_req, nmi_ack, halt )
|
variable cond_true : boolean; -- variable used to evaluate coditional branches
|
variable cond_true : boolean; -- variable used to evaluate coditional branches
|
begin
|
begin
|
-- Registers preserved
|
-- Registers preserved
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
dp_ctrl <= latch_dp;
|
dp_ctrl <= latch_dp;
|
ix_ctrl <= latch_ix;
|
ix_ctrl <= latch_ix;
|
iy_ctrl <= latch_iy;
|
iy_ctrl <= latch_iy;
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
pc_ctrl <= latch_pc;
|
pc_ctrl <= latch_pc;
|
md_ctrl <= latch_md;
|
md_ctrl <= latch_md;
|
ea_ctrl <= latch_ea;
|
ea_ctrl <= latch_ea;
|
iv_ctrl <= latch_iv;
|
iv_ctrl <= latch_iv;
|
op_ctrl <= latch_op;
|
op_ctrl <= latch_op;
|
pre_ctrl <= latch_pre;
|
pre_ctrl <= latch_pre;
|
nmi_ctrl <= latch_nmi;
|
nmi_ctrl <= latch_nmi;
|
-- ALU Idle
|
-- ALU Idle
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
-- Bus idle
|
-- Bus idle
|
addr_ctrl <= idle_ad;
|
addr_ctrl <= idle_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
-- Next State Fetch
|
-- Next State Fetch
|
st_ctrl <= idle_st;
|
st_ctrl <= idle_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
case state is
|
case state is
|
when reset_state => -- released from reset
|
when reset_state => -- released from reset
|
-- reset the registers
|
-- reset the registers
|
op_ctrl <= reset_op;
|
op_ctrl <= reset_op;
|
pre_ctrl <= reset_pre;
|
pre_ctrl <= reset_pre;
|
cc_ctrl <= reset_cc;
|
cc_ctrl <= reset_cc;
|
acca_ctrl <= reset_acca;
|
acca_ctrl <= reset_acca;
|
accb_ctrl <= reset_accb;
|
accb_ctrl <= reset_accb;
|
dp_ctrl <= reset_dp;
|
dp_ctrl <= reset_dp;
|
ix_ctrl <= reset_ix;
|
ix_ctrl <= reset_ix;
|
iy_ctrl <= reset_iy;
|
iy_ctrl <= reset_iy;
|
up_ctrl <= reset_up;
|
up_ctrl <= reset_up;
|
sp_ctrl <= reset_sp;
|
sp_ctrl <= reset_sp;
|
pc_ctrl <= reset_pc;
|
pc_ctrl <= reset_pc;
|
ea_ctrl <= reset_ea;
|
ea_ctrl <= reset_ea;
|
md_ctrl <= reset_md;
|
md_ctrl <= reset_md;
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
|
|
--
|
--
|
-- Jump via interrupt vector
|
-- Jump via interrupt vector
|
-- iv holds interrupt type
|
-- iv holds interrupt type
|
-- fetch PC hi from vector location
|
-- fetch PC hi from vector location
|
--
|
--
|
when vect_hi_state =>
|
when vect_hi_state =>
|
-- fetch pc low interrupt vector
|
-- fetch pc low interrupt vector
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= int_hi_ad;
|
addr_ctrl <= int_hi_ad;
|
next_state <= vect_lo_state;
|
next_state <= vect_lo_state;
|
--
|
--
|
-- jump via interrupt vector
|
-- jump via interrupt vector
|
-- iv holds vector type
|
-- iv holds vector type
|
-- fetch PC lo from vector location
|
-- fetch PC lo from vector location
|
--
|
--
|
when vect_lo_state =>
|
when vect_lo_state =>
|
-- fetch the vector low byte
|
-- fetch the vector low byte
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= int_lo_ad;
|
addr_ctrl <= int_lo_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Here to fetch an instruction
|
-- Here to fetch an instruction
|
-- PC points to opcode
|
-- PC points to opcode
|
-- Should service interrupt requests at this point
|
-- Should service interrupt requests at this point
|
-- either from the timer
|
-- either from the timer
|
-- or from the external input.
|
-- or from the external input.
|
--
|
--
|
when fetch_state =>
|
when fetch_state =>
|
-- fetch the op code
|
-- fetch the op code
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
pre_ctrl <= fetch_pre;
|
pre_ctrl <= fetch_pre;
|
ea_ctrl <= reset_ea;
|
ea_ctrl <= reset_ea;
|
-- Fetch op code
|
-- Fetch op code
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
--
|
--
|
case op_code(7 downto 6) is
|
case op_code(7 downto 6) is
|
when "10" => -- acca
|
when "10" => -- acca
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- suba
|
when "0000" => -- suba
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "0001" => -- cmpa
|
when "0001" => -- cmpa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0010" => -- sbca
|
when "0010" => -- sbca
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sbc;
|
alu_ctrl <= alu_sbc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "0011" =>
|
when "0011" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- cmpd
|
when "00010000" => -- page 2 -- cmpd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "00010001" => -- page 3 -- cmpu
|
when "00010001" => -- page 3 -- cmpu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others => -- page 1 -- subd
|
when others => -- page 1 -- subd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
end case;
|
end case;
|
when "0100" => -- anda
|
when "0100" => -- anda
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "0101" => -- bita
|
when "0101" => -- bita
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0110" => -- ldaa
|
when "0110" => -- ldaa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "0111" => -- staa
|
when "0111" => -- staa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1000" => -- eora
|
when "1000" => -- eora
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_eor;
|
alu_ctrl <= alu_eor;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1001" => -- adca
|
when "1001" => -- adca
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_adc;
|
alu_ctrl <= alu_adc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1010" => -- oraa
|
when "1010" => -- oraa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ora;
|
alu_ctrl <= alu_ora;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1011" => -- adda
|
when "1011" => -- adda
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add8;
|
alu_ctrl <= alu_add8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1100" =>
|
when "1100" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- cmpy
|
when "00010000" => -- page 2 -- cmpy
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "00010001" => -- page 3 -- cmps
|
when "00010001" => -- page 3 -- cmps
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others => -- page 1 -- cmpx
|
when others => -- page 1 -- cmpx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
end case;
|
end case;
|
when "1101" => -- bsr / jsr
|
when "1101" => -- bsr / jsr
|
null;
|
null;
|
when "1110" => -- ldx
|
when "1110" => -- ldx
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- ldy
|
when "00010000" => -- page 2 -- ldy
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when others => -- page 1 -- ldx
|
when others => -- page 1 -- ldx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
end case;
|
end case;
|
when "1111" => -- stx
|
when "1111" => -- stx
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sty
|
when "00010000" => -- page 2 -- sty
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others => -- page 1 -- stx
|
when others => -- page 1 -- stx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
when "11" => -- accb dual op
|
when "11" => -- accb dual op
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- subb
|
when "0000" => -- subb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0001" => -- cmpb
|
when "0001" => -- cmpb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0010" => -- sbcb
|
when "0010" => -- sbcb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sbc;
|
alu_ctrl <= alu_sbc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0011" => -- addd
|
when "0011" => -- addd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0100" => -- andb
|
when "0100" => -- andb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0101" => -- bitb
|
when "0101" => -- bitb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0110" => -- ldab
|
when "0110" => -- ldab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0111" => -- stab
|
when "0111" => -- stab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1000" => -- eorb
|
when "1000" => -- eorb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_eor;
|
alu_ctrl <= alu_eor;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1001" => -- adcb
|
when "1001" => -- adcb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_adc;
|
alu_ctrl <= alu_adc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1010" => -- orab
|
when "1010" => -- orab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ora;
|
alu_ctrl <= alu_ora;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1011" => -- addb
|
when "1011" => -- addb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add8;
|
alu_ctrl <= alu_add8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1100" => -- ldd
|
when "1100" => -- ldd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1101" => -- std
|
when "1101" => -- std
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1110" => -- ldu
|
when "1110" => -- ldu
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- lds
|
when "00010000" => -- page 2 -- lds
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when others => -- page 1 -- ldu
|
when others => -- page 1 -- ldu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end case;
|
end case;
|
when "1111" =>
|
when "1111" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sts
|
when "00010000" => -- page 2 -- sts
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others => -- page 1 -- stu
|
when others => -- page 1 -- stu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
if halt = '1' then
|
if halt = '1' then
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= halt_state;
|
next_state <= halt_state;
|
-- service non maskable interrupts
|
-- service non maskable interrupts
|
elsif (nmi_req = '1') and (nmi_ack = '0') then
|
elsif (nmi_req = '1') and (nmi_ack = '0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
next_state <= int_nmiirq_state;
|
next_state <= int_nmiirq_state;
|
-- service maskable interrupts
|
-- service maskable interrupts
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if(nmi_req = '0') and (nmi_ack='1') then
|
if(nmi_req = '0') and (nmi_ack='1') then
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
end if;
|
end if;
|
--
|
--
|
-- FIRQ & IRQ are level sensitive
|
-- FIRQ & IRQ are level sensitive
|
--
|
--
|
if (firq = '1') and (cc(FBIT) = '0') then
|
if (firq = '1') and (cc(FBIT) = '0') then
|
iv_ctrl <= firq_iv;
|
iv_ctrl <= firq_iv;
|
next_state <= int_firq_state;
|
next_state <= int_firq_state;
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
iv_ctrl <= irq_iv;
|
iv_ctrl <= irq_iv;
|
next_state <= int_nmiirq_state;
|
next_state <= int_nmiirq_state;
|
else
|
else
|
-- Advance the PC to fetch next instruction byte
|
-- Advance the PC to fetch next instruction byte
|
iv_ctrl <= reset_iv; -- default to reset
|
iv_ctrl <= reset_iv; -- default to reset
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= decode1_state;
|
next_state <= decode1_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
--
|
--
|
-- Here to decode instruction
|
-- Here to decode instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode1_state =>
|
when decode1_state =>
|
-- fetch first byte of address or immediate data
|
-- fetch first byte of address or immediate data
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- direct single op (2 bytes)
|
-- direct single op (2 bytes)
|
-- 6809 => 6 cycles
|
-- 6809 => 6 cycles
|
-- cpu09 => 5 cycles
|
-- cpu09 => 5 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 3 md_lo=(ea) / pc=pc
|
-- 3 md_lo=(ea) / pc=pc
|
-- 4 alu_left=md / md=alu_out / pc=pc
|
-- 4 alu_left=md / md=alu_out / pc=pc
|
-- 5 (ea)=md_lo / pc=pc
|
-- 5 (ea)=md_lo / pc=pc
|
--
|
--
|
-- Exception is JMP
|
-- Exception is JMP
|
-- 6809 => 3 cycles
|
-- 6809 => 3 cycles
|
-- cpu09 => 3 cycles
|
-- cpu09 => 3 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 3 pc=ea
|
-- 3 pc=ea
|
--
|
--
|
when "0000" =>
|
when "0000" =>
|
-- advance the PC
|
-- advance the PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
next_state <= jmp_state;
|
next_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
next_state <= single_op_exec_state;
|
next_state <= single_op_exec_state;
|
when others =>
|
when others =>
|
next_state <= single_op_read_state;
|
next_state <= single_op_read_state;
|
end case;
|
end case;
|
|
|
-- acca / accb inherent instructions
|
-- acca / accb inherent instructions
|
when "0001" =>
|
when "0001" =>
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
--
|
--
|
-- Page2 pre byte
|
-- Page2 pre byte
|
-- pre=(pc) / pc=pc+1
|
-- pre=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
--
|
--
|
when "0000" => -- page2
|
when "0000" => -- page2
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= decode2_state;
|
next_state <= decode2_state;
|
|
|
--
|
--
|
-- Page3 pre byte
|
-- Page3 pre byte
|
-- pre=(pc) / pc=pc+1
|
-- pre=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
--
|
--
|
when "0001" => -- page3
|
when "0001" => -- page3
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= decode3_state;
|
next_state <= decode3_state;
|
|
|
--
|
--
|
-- nop - No operation ( 1 byte )
|
-- nop - No operation ( 1 byte )
|
-- 6809 => 2 cycles
|
-- 6809 => 2 cycles
|
-- cpu09 => 2 cycles
|
-- cpu09 => 2 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 decode
|
-- 2 decode
|
--
|
--
|
when "0010" => -- nop
|
when "0010" => -- nop
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- sync - halt execution until an interrupt is received
|
-- sync - halt execution until an interrupt is received
|
-- interrupt may be NMI, IRQ or FIRQ
|
-- interrupt may be NMI, IRQ or FIRQ
|
-- program execution continues if the
|
-- program execution continues if the
|
-- interrupt is asserted for 3 clock cycles
|
-- interrupt is asserted for 3 clock cycles
|
-- note that registers are not pushed onto the stack
|
-- note that registers are not pushed onto the stack
|
-- CPU09 => Interrupts need only be asserted for one clock cycle
|
-- CPU09 => Interrupts need only be asserted for one clock cycle
|
--
|
--
|
when "0011" => -- sync
|
when "0011" => -- sync
|
next_state <= sync_state;
|
next_state <= sync_state;
|
|
|
--
|
--
|
-- lbra -- long branch (3 bytes)
|
-- lbra -- long branch (3 bytes)
|
-- 6809 => 5 cycles
|
-- 6809 => 5 cycles
|
-- cpu09 => 4 cycles
|
-- cpu09 => 4 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 4 pc=pc+md
|
-- 4 pc=pc+md
|
--
|
--
|
when "0110" =>
|
when "0110" =>
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
--
|
--
|
-- lbsr - long branch to subroutine (3 bytes)
|
-- lbsr - long branch to subroutine (3 bytes)
|
-- 6809 => 9 cycles
|
-- 6809 => 9 cycles
|
-- cpu09 => 6 cycles
|
-- cpu09 => 6 cycles
|
-- 1 op=(pc) /pc=pc+1
|
-- 1 op=(pc) /pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
|
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
|
-- 5 (sp)=pc_hi / pc=pc
|
-- 5 (sp)=pc_hi / pc=pc
|
-- 6 pc=pc+md
|
-- 6 pc=pc+md
|
--
|
--
|
when "0111" =>
|
when "0111" =>
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
when "1001" => -- daa
|
when "1001" => -- daa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_daa;
|
alu_ctrl <= alu_daa;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1010" => -- orcc
|
when "1010" => -- orcc
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= orcc_state;
|
next_state <= orcc_state;
|
|
|
when "1100" => -- andcc
|
when "1100" => -- andcc
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= andcc_state;
|
next_state <= andcc_state;
|
|
|
when "1101" => -- sex
|
when "1101" => -- sex
|
-- have sex
|
-- have sex
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_sex;
|
alu_ctrl <= alu_sex;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1110" => -- exg
|
when "1110" => -- exg
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= exg_state;
|
next_state <= exg_state;
|
|
|
when "1111" => -- tfr
|
when "1111" => -- tfr
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- call transfer as a subroutine
|
-- call transfer as a subroutine
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= tfr_state;
|
next_state <= tfr_state;
|
|
|
when others =>
|
when others =>
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- Short branch conditional
|
-- Short branch conditional
|
-- 6809 => always 3 cycles
|
-- 6809 => always 3 cycles
|
-- cpu09 => always = 3 cycles
|
-- cpu09 => always = 3 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
|
-- 3 if cc tru pc=pc+md else pc=pc
|
-- 3 if cc tru pc=pc+md else pc=pc
|
--
|
--
|
when "0010" => -- branch conditional
|
when "0010" => -- branch conditional
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= sbranch_state;
|
next_state <= sbranch_state;
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
--
|
--
|
-- lea - load effective address (2+ bytes)
|
-- lea - load effective address (2+ bytes)
|
-- 6809 => 4 cycles + addressing mode
|
-- 6809 => 4 cycles + addressing mode
|
-- cpu09 => 4 cycles + addressing mode
|
-- cpu09 => 4 cycles + addressing mode
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 md_lo=(pc) / pc=pc+1
|
-- 2 md_lo=(pc) / pc=pc+1
|
-- 3 calculate ea
|
-- 3 calculate ea
|
-- 4 ix/iy/sp/up = ea
|
-- 4 ix/iy/sp/up = ea
|
--
|
--
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" | -- leax
|
when "0000" | -- leax
|
"0001" | -- leay
|
"0001" | -- leay
|
"0010" | -- leas
|
"0010" | -- leas
|
"0011" => -- leau
|
"0011" => -- leau
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= lea_state;
|
return_state <= lea_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
--
|
--
|
-- pshs - push registers onto sp stack
|
-- pshs - push registers onto sp stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 ea_lo=(pc) / pc=pc+1
|
-- 2 ea_lo=(pc) / pc=pc+1
|
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
|
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
|
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
|
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
|
-- 5 if ea(7) = 1 (sp)=pch
|
-- 5 if ea(7) = 1 (sp)=pch
|
-- if ea(6 downto 0) != "0000000" then sp=sp-1
|
-- if ea(6 downto 0) != "0000000" then sp=sp-1
|
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
|
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
|
-- 7 if ea(6) = 1 (sp)=uph
|
-- 7 if ea(6) = 1 (sp)=uph
|
-- if ea(5 downto 0) != "000000" then sp=sp-1
|
-- if ea(5 downto 0) != "000000" then sp=sp-1
|
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
|
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
|
-- 9 if ea(5) = 1 (sp)=iyh
|
-- 9 if ea(5) = 1 (sp)=iyh
|
-- if ea(4 downto 0) != "00000" then sp=sp-1
|
-- if ea(4 downto 0) != "00000" then sp=sp-1
|
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
|
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
|
-- 11 if ea(4) = 1 (sp)=ixh
|
-- 11 if ea(4) = 1 (sp)=ixh
|
-- if ea(3 downto 0) != "0000" then sp=sp-1
|
-- if ea(3 downto 0) != "0000" then sp=sp-1
|
-- 12 if ea(3) = 1 (sp)=dp
|
-- 12 if ea(3) = 1 (sp)=dp
|
-- if ea(2 downto 0) != "000" then sp=sp-1
|
-- if ea(2 downto 0) != "000" then sp=sp-1
|
-- 13 if ea(2) = 1 (sp)=accb
|
-- 13 if ea(2) = 1 (sp)=accb
|
-- if ea(1 downto 0) != "00" then sp=sp-1
|
-- if ea(1 downto 0) != "00" then sp=sp-1
|
-- 14 if ea(1) = 1 (sp)=acca
|
-- 14 if ea(1) = 1 (sp)=acca
|
-- if ea(0 downto 0) != "0" then sp=sp-1
|
-- if ea(0 downto 0) != "0" then sp=sp-1
|
-- 15 if ea(0) = 1 (sp)=cc
|
-- 15 if ea(0) = 1 (sp)=cc
|
--
|
--
|
when "0100" => -- pshs
|
when "0100" => -- pshs
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= pshs_state;
|
next_state <= pshs_state;
|
|
|
--
|
--
|
-- puls - pull registers of sp stack
|
-- puls - pull registers of sp stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0101" => -- puls
|
when "0101" => -- puls
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= puls_state;
|
next_state <= puls_state;
|
|
|
--
|
--
|
-- pshu - push registers onto up stack
|
-- pshu - push registers onto up stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0110" => -- pshu
|
when "0110" => -- pshu
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= pshu_state;
|
next_state <= pshu_state;
|
|
|
--
|
--
|
-- pulu - pull registers of up stack
|
-- pulu - pull registers of up stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0111" => -- pulu
|
when "0111" => -- pulu
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= pulu_state;
|
next_state <= pulu_state;
|
|
|
--
|
--
|
-- rts - return from subroutine
|
-- rts - return from subroutine
|
-- 6809 => 5 cycles
|
-- 6809 => 5 cycles
|
-- cpu09 => 4 cycles
|
-- cpu09 => 4 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 decode op
|
-- 2 decode op
|
-- 3 pc_hi = (sp) / sp=sp+1
|
-- 3 pc_hi = (sp) / sp=sp+1
|
-- 4 pc_lo = (sp) / sp=sp+1
|
-- 4 pc_lo = (sp) / sp=sp+1
|
--
|
--
|
when "1001" =>
|
when "1001" =>
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= pull_return_hi_state;
|
next_state <= pull_return_hi_state;
|
|
|
--
|
--
|
-- add accb to index register
|
-- add accb to index register
|
-- *** Note: this is an unsigned addition.
|
-- *** Note: this is an unsigned addition.
|
-- does not affect any condition codes
|
-- does not affect any condition codes
|
-- 6809 => 3 cycles
|
-- 6809 => 3 cycles
|
-- cpu09 => 2 cycles
|
-- cpu09 => 2 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
|
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
|
--
|
--
|
when "1010" => -- abx
|
when "1010" => -- abx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_abx;
|
alu_ctrl <= alu_abx;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1011" => -- rti
|
when "1011" => -- rti
|
next_state <= rti_cc_state;
|
next_state <= rti_cc_state;
|
|
|
when "1100" => -- cwai #$<cc_mask>
|
when "1100" => -- cwai #$<cc_mask>
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
-- increment pc
|
-- increment pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= int_entire_state; -- set entire flag
|
return_state <= int_entire_state; -- set entire flag
|
next_state <= andcc_state;
|
next_state <= andcc_state;
|
|
|
when "1101" => -- mul
|
when "1101" => -- mul
|
next_state <= mul_state;
|
next_state <= mul_state;
|
|
|
when "1111" => -- swi
|
when "1111" => -- swi
|
-- predecrement SP
|
-- predecrement SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= swi_iv;
|
iv_ctrl <= swi_iv;
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
--
|
--
|
-- Accumulator A Single operand
|
-- Accumulator A Single operand
|
-- source = acca, dest = acca
|
-- source = acca, dest = acca
|
-- Do not advance PC
|
-- Do not advance PC
|
-- Typically 2 cycles 1 bytes
|
-- Typically 2 cycles 1 bytes
|
-- 1 opcode fetch
|
-- 1 opcode fetch
|
-- 2 post byte fetch / instruction decode
|
-- 2 post byte fetch / instruction decode
|
-- Note that there is no post byte
|
-- Note that there is no post byte
|
-- so do not advance PC in decode cycle
|
-- so do not advance PC in decode cycle
|
-- Re-run opcode fetch cycle after decode
|
-- Re-run opcode fetch cycle after decode
|
--
|
--
|
when "0100" => -- acca single op
|
when "0100" => -- acca single op
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0011" => -- com
|
when "0011" => -- com
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_com;
|
alu_ctrl <= alu_com;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0100" => -- lsr
|
when "0100" => -- lsr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_lsr8;
|
alu_ctrl <= alu_lsr8;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0110" => -- ror
|
when "0110" => -- ror
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ror8;
|
alu_ctrl <= alu_ror8;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0111" => -- asr
|
when "0111" => -- asr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asr8;
|
alu_ctrl <= alu_asr8;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1000" => -- asl
|
when "1000" => -- asl
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asl8;
|
alu_ctrl <= alu_asl8;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1001" => -- rol
|
when "1001" => -- rol
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_rol8;
|
alu_ctrl <= alu_rol8;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1010" => -- dec
|
when "1010" => -- dec
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_dec;
|
alu_ctrl <= alu_dec;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1011" => -- undefined
|
when "1011" => -- undefined
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
when "1100" => -- inc
|
when "1100" => -- inc
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_inc;
|
alu_ctrl <= alu_inc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1101" => -- tst
|
when "1101" => -- tst
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1110" => -- jmp (not defined)
|
when "1110" => -- jmp (not defined)
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_clr;
|
alu_ctrl <= alu_clr;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others =>
|
when others =>
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
end case;
|
end case;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Single Operand accb
|
-- Single Operand accb
|
-- source = accb, dest = accb
|
-- source = accb, dest = accb
|
-- Typically 2 cycles 1 bytes
|
-- Typically 2 cycles 1 bytes
|
-- 1 opcode fetch
|
-- 1 opcode fetch
|
-- 2 post byte fetch / instruction decode
|
-- 2 post byte fetch / instruction decode
|
-- Note that there is no post byte
|
-- Note that there is no post byte
|
-- so do not advance PC in decode cycle
|
-- so do not advance PC in decode cycle
|
-- Re-run opcode fetch cycle after decode
|
-- Re-run opcode fetch cycle after decode
|
--
|
--
|
when "0101" =>
|
when "0101" =>
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0011" => -- com
|
when "0011" => -- com
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_com;
|
alu_ctrl <= alu_com;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0100" => -- lsr
|
when "0100" => -- lsr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_lsr8;
|
alu_ctrl <= alu_lsr8;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0110" => -- ror
|
when "0110" => -- ror
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ror8;
|
alu_ctrl <= alu_ror8;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "0111" => -- asr
|
when "0111" => -- asr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asr8;
|
alu_ctrl <= alu_asr8;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1000" => -- asl
|
when "1000" => -- asl
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asl8;
|
alu_ctrl <= alu_asl8;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1001" => -- rol
|
when "1001" => -- rol
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_rol8;
|
alu_ctrl <= alu_rol8;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1010" => -- dec
|
when "1010" => -- dec
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_dec;
|
alu_ctrl <= alu_dec;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1011" => -- undefined
|
when "1011" => -- undefined
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
when "1100" => -- inc
|
when "1100" => -- inc
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_inc;
|
alu_ctrl <= alu_inc;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1101" => -- tst
|
when "1101" => -- tst
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1110" => -- jmp (undefined)
|
when "1110" => -- jmp (undefined)
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_clr;
|
alu_ctrl <= alu_clr;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when others =>
|
when others =>
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
end case;
|
end case;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Single operand indexed
|
-- Single operand indexed
|
-- Two byte instruction so advance PC
|
-- Two byte instruction so advance PC
|
-- EA should hold index offset
|
-- EA should hold index offset
|
--
|
--
|
when "0110" => -- indexed single op
|
when "0110" => -- indexed single op
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
return_state <= single_op_exec_state;
|
return_state <= single_op_exec_state;
|
when others =>
|
when others =>
|
return_state <= single_op_read_state;
|
return_state <= single_op_read_state;
|
end case;
|
end case;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
--
|
--
|
-- Single operand extended addressing
|
-- Single operand extended addressing
|
-- three byte instruction so advance the PC
|
-- three byte instruction so advance the PC
|
-- Low order EA holds high order address
|
-- Low order EA holds high order address
|
--
|
--
|
when "0111" => -- extended single op
|
when "0111" => -- extended single op
|
-- increment PC
|
-- increment PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
return_state <= single_op_exec_state;
|
return_state <= single_op_exec_state;
|
when others =>
|
when others =>
|
return_state <= single_op_read_state;
|
return_state <= single_op_read_state;
|
end case;
|
end case;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd #
|
when "0011" | -- subd #
|
"1100" | -- cmpx #
|
"1100" | -- cmpx #
|
"1110" => -- ldx #
|
"1110" => -- ldx #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
--
|
--
|
-- bsr offset - Branch to subroutine (2 bytes)
|
-- bsr offset - Branch to subroutine (2 bytes)
|
-- 6809 => 7 cycles
|
-- 6809 => 7 cycles
|
-- cpu09 => 5 cycles
|
-- cpu09 => 5 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
|
-- 3 (sp)=pc_lo / sp=sp-1
|
-- 3 (sp)=pc_lo / sp=sp-1
|
-- 4 (sp)=pc_hi
|
-- 4 (sp)=pc_hi
|
-- 5 pc=pc+md
|
-- 5 pc=pc+md
|
--
|
--
|
when "1101" => -- bsr
|
when "1101" => -- bsr
|
-- pre decrement SP
|
-- pre decrement SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
--
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= sbranch_state;
|
return_state <= sbranch_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "0111" => -- sta direct
|
when "0111" => -- sta direct
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
when "1111" => -- stx direct
|
when "1111" => -- stx direct
|
-- idle ALU
|
-- idle ALU
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
--
|
--
|
-- jsr direct - Jump to subroutine in direct page (2 bytes)
|
-- jsr direct - Jump to subroutine in direct page (2 bytes)
|
-- 6809 => 7 cycles
|
-- 6809 => 7 cycles
|
-- cpu09 => 5 cycles
|
-- cpu09 => 5 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
|
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
|
-- 3 (sp)=pc_lo / sp=sp-1
|
-- 3 (sp)=pc_lo / sp=sp-1
|
-- 4 (sp)=pc_hi
|
-- 4 (sp)=pc_hi
|
-- 5 pc=ea
|
-- 5 pc=ea
|
--
|
--
|
when "1101" => -- jsr direct
|
when "1101" => -- jsr direct
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
--
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
when others =>
|
when others =>
|
next_state <= dual_op_read8_state;
|
next_state <= dual_op_read8_state;
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "0111" => -- staa ,x
|
when "0111" => -- staa ,x
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1111" => -- stx ,x
|
when "1111" => -- stx ,x
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1101" => -- jsr ,x
|
when "1101" => -- jsr ,x
|
-- DO NOT pre decrement SP
|
-- DO NOT pre decrement SP
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jsr_state;
|
return_state <= jsr_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "0111" => -- staa >
|
when "0111" => -- staa >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1111" => -- stx >
|
when "1111" => -- stx >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1101" => -- jsr >extended
|
when "1101" => -- jsr >extended
|
-- DO NOT pre decrement sp
|
-- DO NOT pre decrement sp
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jsr_state;
|
return_state <= jsr_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
end case;
|
end case;
|
|
|
when "1100" => -- accb immediate
|
when "1100" => -- accb immediate
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd #
|
when "0011" | -- addd #
|
"1100" | -- ldd #
|
"1100" | -- ldd #
|
"1110" => -- ldu #
|
"1110" => -- ldu #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
|
|
when "1101" => -- accb direct
|
when "1101" => -- accb direct
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "0111" => -- stab direct
|
when "0111" => -- stab direct
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
when "1101" => -- std direct
|
when "1101" => -- std direct
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when "1111" => -- stu direct
|
when "1111" => -- stu direct
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= dual_op_read8_state;
|
next_state <= dual_op_read8_state;
|
end case;
|
end case;
|
|
|
when "1110" => -- accb indexed
|
when "1110" => -- accb indexed
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "0111" => -- stab indexed
|
when "0111" => -- stab indexed
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1101" => -- std indexed
|
when "1101" => -- std indexed
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1111" => -- stu indexed
|
when "1111" => -- stu indexed
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
end case;
|
end case;
|
|
|
when "1111" => -- accb extended
|
when "1111" => -- accb extended
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "0111" => -- stab extended
|
when "0111" => -- stab extended
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1101" => -- std extended
|
when "1101" => -- std extended
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1111" => -- stu extended
|
when "1111" => -- stu extended
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Here to decode prefix 2 instruction
|
-- Here to decode prefix 2 instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode2_state =>
|
when decode2_state =>
|
-- fetch first byte of address or immediate data
|
-- fetch first byte of address or immediate data
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- lbcc -- long branch conditional
|
-- lbcc -- long branch conditional
|
-- 6809 => branch 6 cycles, no branch 5 cycles
|
-- 6809 => branch 6 cycles, no branch 5 cycles
|
-- cpu09 => always 5 cycles
|
-- cpu09 => always 5 cycles
|
-- 1 pre=(pc) / pc=pc+1
|
-- 1 pre=(pc) / pc=pc+1
|
-- 2 op=(pc) / pc=pc+1
|
-- 2 op=(pc) / pc=pc+1
|
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 5 if cond pc=pc+md else pc=pc
|
-- 5 if cond pc=pc+md else pc=pc
|
--
|
--
|
when "0010" =>
|
when "0010" =>
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1111" => -- swi 2
|
when "1111" => -- swi 2
|
-- predecrement sp
|
-- predecrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= swi2_iv;
|
iv_ctrl <= swi2_iv;
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd #
|
when "0011" | -- cmpd #
|
"1100" | -- cmpy #
|
"1100" | -- cmpy #
|
"1110" => -- ldy #
|
"1110" => -- ldy #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd <
|
when "0011" | -- cmpd <
|
"1100" | -- cmpy <
|
"1100" | -- cmpy <
|
"1110" => -- ldy <
|
"1110" => -- ldy <
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "1111" => -- sty <
|
when "1111" => -- sty <
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd ,ind
|
when "0011" | -- cmpd ,ind
|
"1100" | -- cmpy ,ind
|
"1100" | -- cmpy ,ind
|
"1110" => -- ldy ,ind
|
"1110" => -- ldy ,ind
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1111" => -- sty ,ind
|
when "1111" => -- sty ,ind
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd <
|
when "0011" | -- cmpd <
|
"1100" | -- cmpy <
|
"1100" | -- cmpy <
|
"1110" => -- ldy <
|
"1110" => -- ldy <
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1111" => -- sty >
|
when "1111" => -- sty >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1100" => -- accb immediate
|
when "1100" => -- accb immediate
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef #
|
when "0011" | -- undef #
|
"1100" | -- undef #
|
"1100" | -- undef #
|
"1110" => -- lds #
|
"1110" => -- lds #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1101" => -- accb direct
|
when "1101" => -- accb direct
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef <
|
when "0011" | -- undef <
|
"1100" | -- undef <
|
"1100" | -- undef <
|
"1110" => -- lds <
|
"1110" => -- lds <
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "1111" => -- sts <
|
when "1111" => -- sts <
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1110" => -- accb indexed
|
when "1110" => -- accb indexed
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef ,ind
|
when "0011" | -- undef ,ind
|
"1100" | -- undef ,ind
|
"1100" | -- undef ,ind
|
"1110" => -- lds ,ind
|
"1110" => -- lds ,ind
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1111" => -- sts ,ind
|
when "1111" => -- sts ,ind
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1111" => -- accb extended
|
when "1111" => -- accb extended
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef >
|
when "0011" | -- undef >
|
"1100" | -- undef >
|
"1100" | -- undef >
|
"1110" => -- lds >
|
"1110" => -- lds >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1111" => -- sts >
|
when "1111" => -- sts >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- Here to decode instruction
|
-- Here to decode instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode3_state =>
|
when decode3_state =>
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1111" => -- swi3
|
when "1111" => -- swi3
|
-- predecrement sp
|
-- predecrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= swi3_iv;
|
iv_ctrl <= swi3_iv;
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu #
|
when "0011" | -- cmpu #
|
"1100" | -- cmps #
|
"1100" | -- cmps #
|
"1110" => -- undef #
|
"1110" => -- undef #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu <
|
when "0011" | -- cmpu <
|
"1100" | -- cmps <
|
"1100" | -- cmps <
|
"1110" => -- undef <
|
"1110" => -- undef <
|
st_ctrl <= idle_st;
|
st_ctrl <= idle_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu ,X
|
when "0011" | -- cmpu ,X
|
"1100" | -- cmps ,X
|
"1100" | -- cmps ,X
|
"1110" => -- undef ,X
|
"1110" => -- undef ,X
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu >
|
when "0011" | -- cmpu >
|
"1100" | -- cmps >
|
"1100" | -- cmps >
|
"1110" => -- undef >
|
"1110" => -- undef >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- here if ea holds low byte
|
-- here if ea holds low byte
|
-- Direct
|
-- Direct
|
-- Extended
|
-- Extended
|
-- Indexed
|
-- Indexed
|
-- read memory location
|
-- read memory location
|
--
|
--
|
when single_op_read_state =>
|
when single_op_read_state =>
|
-- read memory into md
|
-- read memory into md
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
next_state <= single_op_exec_state;
|
next_state <= single_op_exec_state;
|
|
|
when single_op_exec_state =>
|
when single_op_exec_state =>
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0011" => -- com
|
when "0011" => -- com
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_com;
|
alu_ctrl <= alu_com;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0100" => -- lsr
|
when "0100" => -- lsr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_lsr8;
|
alu_ctrl <= alu_lsr8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0110" => -- ror
|
when "0110" => -- ror
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ror8;
|
alu_ctrl <= alu_ror8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0111" => -- asr
|
when "0111" => -- asr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asr8;
|
alu_ctrl <= alu_asr8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1000" => -- asl
|
when "1000" => -- asl
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asl8;
|
alu_ctrl <= alu_asl8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1001" => -- rol
|
when "1001" => -- rol
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_rol8;
|
alu_ctrl <= alu_rol8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1010" => -- dec
|
when "1010" => -- dec
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_dec;
|
alu_ctrl <= alu_dec;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1011" => -- undefined
|
when "1011" => -- undefined
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1100" => -- inc
|
when "1100" => -- inc
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_inc;
|
alu_ctrl <= alu_inc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1101" => -- tst
|
when "1101" => -- tst
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_clr;
|
alu_ctrl <= alu_clr;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when others =>
|
when others =>
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- single operand 8 bit write
|
-- single operand 8 bit write
|
-- Write low 8 bits of ALU output
|
-- Write low 8 bits of ALU output
|
-- EA holds address
|
-- EA holds address
|
-- MD holds data
|
-- MD holds data
|
--
|
--
|
when single_op_write_state =>
|
when single_op_write_state =>
|
-- write ALU low byte output
|
-- write ALU low byte output
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- here if ea holds address of low byte
|
-- here if ea holds address of low byte
|
-- read memory location
|
-- read memory location
|
--
|
--
|
when dual_op_read8_state =>
|
when dual_op_read8_state =>
|
-- read first data byte from ea
|
-- read first data byte from ea
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Here to read a 16 bit value into MD
|
-- Here to read a 16 bit value into MD
|
-- pointed to by the EA register
|
-- pointed to by the EA register
|
-- The first byte is read
|
-- The first byte is read
|
-- and the EA is incremented
|
-- and the EA is incremented
|
--
|
--
|
when dual_op_read16_state =>
|
when dual_op_read16_state =>
|
-- increment the effective address
|
-- increment the effective address
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- read the high byte of the 16 bit data
|
-- read the high byte of the 16 bit data
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
next_state <= dual_op_read16_2_state;
|
next_state <= dual_op_read16_2_state;
|
|
|
--
|
--
|
-- here to read the second byte
|
-- here to read the second byte
|
-- pointed to by EA into MD
|
-- pointed to by EA into MD
|
--
|
--
|
when dual_op_read16_2_state =>
|
when dual_op_read16_2_state =>
|
-- read the low byte of the 16 bit data
|
-- read the low byte of the 16 bit data
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- 16 bit Write state
|
-- 16 bit Write state
|
-- EA hold address of memory to write to
|
-- EA hold address of memory to write to
|
-- Advance the effective address in ALU
|
-- Advance the effective address in ALU
|
-- decode op_code to determine which
|
-- decode op_code to determine which
|
-- register to write
|
-- register to write
|
--
|
--
|
when dual_op_write16_state =>
|
when dual_op_write16_state =>
|
-- increment the effective address
|
-- increment the effective address
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- write the ALU hi byte at ea
|
-- write the ALU hi byte at ea
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
if op_code(6) = '0' then
|
if op_code(6) = '0' then
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1111" => -- stx / sty
|
when "1111" => -- stx / sty
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sty
|
when "00010000" => -- page 2 -- sty
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
when others => -- page 1 -- stx
|
when others => -- page 1 -- stx
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_hi_dout;
|
dout_ctrl <= md_hi_dout;
|
end case;
|
end case;
|
else
|
else
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1101" => -- std
|
when "1101" => -- std
|
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
|
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
|
when "1111" => -- stu / sts
|
when "1111" => -- stu / sts
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sts
|
when "00010000" => -- page 2 -- sts
|
dout_ctrl <= sp_hi_dout;
|
dout_ctrl <= sp_hi_dout;
|
when others => -- page 1 -- stu
|
when others => -- page 1 -- stu
|
dout_ctrl <= up_hi_dout;
|
dout_ctrl <= up_hi_dout;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_hi_dout;
|
dout_ctrl <= md_hi_dout;
|
end case;
|
end case;
|
end if;
|
end if;
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
--
|
--
|
-- Dual operand 8 bit write
|
-- Dual operand 8 bit write
|
-- Write 8 bit accumulator
|
-- Write 8 bit accumulator
|
-- or low byte of 16 bit register
|
-- or low byte of 16 bit register
|
-- EA holds address
|
-- EA holds address
|
-- decode opcode to determine
|
-- decode opcode to determine
|
-- which register to apply to the bus
|
-- which register to apply to the bus
|
-- Also set the condition codes here
|
-- Also set the condition codes here
|
--
|
--
|
when dual_op_write8_state =>
|
when dual_op_write8_state =>
|
if op_code(6) = '0' then
|
if op_code(6) = '0' then
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0111" => -- sta
|
when "0111" => -- sta
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
when "1111" => -- stx / sty
|
when "1111" => -- stx / sty
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sty
|
when "00010000" => -- page 2 -- sty
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
when others => -- page 1 -- stx
|
when others => -- page 1 -- stx
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
end case;
|
end case;
|
else
|
else
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0111" => -- stb
|
when "0111" => -- stb
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
when "1101" => -- std
|
when "1101" => -- std
|
dout_ctrl <= accb_dout; -- accb is low byte of accd
|
dout_ctrl <= accb_dout; -- accb is low byte of accd
|
when "1111" => -- stu / sts
|
when "1111" => -- stu / sts
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sts
|
when "00010000" => -- page 2 -- sts
|
dout_ctrl <= sp_lo_dout;
|
dout_ctrl <= sp_lo_dout;
|
when others => -- page 1 -- stu
|
when others => -- page 1 -- stu
|
dout_ctrl <= up_lo_dout;
|
dout_ctrl <= up_lo_dout;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- write ALU low byte output
|
-- write ALU low byte output
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- 16 bit immediate addressing mode
|
-- 16 bit immediate addressing mode
|
--
|
--
|
when imm16_state =>
|
when imm16_state =>
|
-- increment pc
|
-- increment pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch next immediate byte
|
-- fetch next immediate byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
--
|
--
|
-- md & ea holds 8 bit index offset
|
-- md & ea holds 8 bit index offset
|
-- calculate the effective memory address
|
-- calculate the effective memory address
|
-- using the alu
|
-- using the alu
|
--
|
--
|
when indexed_state =>
|
when indexed_state =>
|
--
|
--
|
-- decode indexing mode
|
-- decode indexing mode
|
--
|
--
|
if md(7) = '0' then
|
if md(7) = '0' then
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= md_sign5_right;
|
right_ctrl <= md_sign5_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
else
|
else
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" => -- ,R+
|
when "0000" => -- ,R+
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
--
|
--
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
next_state <= postincr1_state;
|
next_state <= postincr1_state;
|
|
|
when "0001" => -- ,R++
|
when "0001" => -- ,R++
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
next_state <= postincr2_state;
|
next_state <= postincr2_state;
|
|
|
when "0010" => -- ,-R
|
when "0010" => -- ,-R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when "0011" => -- ,--R
|
when "0011" => -- ,--R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
right_ctrl <= two_right;
|
right_ctrl <= two_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0100" => -- ,R (zero offset)
|
when "0100" => -- ,R (zero offset)
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0101" => -- ACCB,R
|
when "0101" => -- ACCB,R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0110" => -- ACCA,R
|
when "0110" => -- ACCA,R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= acca_right;
|
right_ctrl <= acca_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0111" => -- undefined
|
when "0111" => -- undefined
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1000" => -- offset8,R
|
when "1000" => -- offset8,R
|
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
|
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= index8_state;
|
next_state <= index8_state;
|
|
|
when "1001" => -- offset16,R
|
when "1001" => -- offset16,R
|
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
|
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= index16_state;
|
next_state <= index16_state;
|
|
|
when "1010" => -- undefined
|
when "1010" => -- undefined
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
--
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1011" => -- ACCD,R
|
when "1011" => -- ACCD,R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= accd_right;
|
right_ctrl <= accd_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1100" => -- offset8,PC
|
when "1100" => -- offset8,PC
|
-- fetch 8 bit offset
|
-- fetch 8 bit offset
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= pcrel8_state;
|
next_state <= pcrel8_state;
|
|
|
when "1101" => -- offset16,PC
|
when "1101" => -- offset16,PC
|
-- fetch offset
|
-- fetch offset
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= pcrel16_state;
|
next_state <= pcrel16_state;
|
|
|
when "1110" => -- undefined
|
when "1110" => -- undefined
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
-- when "1111" => -- [,address]
|
-- when "1111" => -- [,address]
|
-- advance PC to pick up address
|
-- advance PC to pick up address
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
next_state <= indexaddr_state;
|
next_state <= indexaddr_state;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- load index register with ea plus one
|
-- load index register with ea plus one
|
when postincr1_state =>
|
when postincr1_state =>
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "01" =>
|
when "01" =>
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "10" =>
|
when "10" =>
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
-- return to previous state
|
-- return to previous state
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- load index register with ea plus two
|
-- load index register with ea plus two
|
when postincr2_state =>
|
when postincr2_state =>
|
-- increment register by two (address)
|
-- increment register by two (address)
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= two_right;
|
right_ctrl <= two_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "01" =>
|
when "01" =>
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "10" =>
|
when "10" =>
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
-- return to previous state
|
-- return to previous state
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
--
|
--
|
-- ea = index register + md (8 bit signed offset)
|
-- ea = index register + md (8 bit signed offset)
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when index8_state =>
|
when index8_state =>
|
case ea(6 downto 5) is
|
case ea(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
-- ea = index reg + md
|
-- ea = index reg + md
|
right_ctrl <= md_sign8_right;
|
right_ctrl <= md_sign8_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- fetch low byte of 16 bit indexed offset
|
-- fetch low byte of 16 bit indexed offset
|
when index16_state =>
|
when index16_state =>
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
next_state <= index16_2_state;
|
next_state <= index16_2_state;
|
|
|
-- ea = index register + md (16 bit offset)
|
-- ea = index register + md (16 bit offset)
|
-- ea holds post byte
|
-- ea holds post byte
|
when index16_2_state =>
|
when index16_2_state =>
|
case ea(6 downto 5) is
|
case ea(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
-- ea = index reg + md
|
-- ea = index reg + md
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
--
|
--
|
-- pc relative with 8 bit signed offest
|
-- pc relative with 8 bit signed offest
|
-- md holds signed offset
|
-- md holds signed offset
|
--
|
--
|
when pcrel8_state =>
|
when pcrel8_state =>
|
-- ea = pc + signed md
|
-- ea = pc + signed md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_sign8_right;
|
right_ctrl <= md_sign8_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- pc relative addressing with 16 bit offset
|
-- pc relative addressing with 16 bit offset
|
-- pick up the low byte of the offset in md
|
-- pick up the low byte of the offset in md
|
-- advance the pc
|
-- advance the pc
|
when pcrel16_state =>
|
when pcrel16_state =>
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
next_state <= pcrel16_2_state;
|
next_state <= pcrel16_2_state;
|
|
|
-- pc relative with16 bit signed offest
|
-- pc relative with16 bit signed offest
|
-- md holds signed offset
|
-- md holds signed offset
|
when pcrel16_2_state =>
|
when pcrel16_2_state =>
|
-- ea = pc + md
|
-- ea = pc + md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- indexed to address
|
-- indexed to address
|
-- pick up the low byte of the address
|
-- pick up the low byte of the address
|
-- advance the pc
|
-- advance the pc
|
when indexaddr_state =>
|
when indexaddr_state =>
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
next_state <= indexaddr2_state;
|
next_state <= indexaddr2_state;
|
|
|
-- indexed to absolute address
|
-- indexed to absolute address
|
-- md holds address
|
-- md holds address
|
-- ea hold indexing mode byte
|
-- ea hold indexing mode byte
|
when indexaddr2_state =>
|
when indexaddr2_state =>
|
-- ea = md
|
-- ea = md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
--
|
--
|
-- load md with high byte of indirect address
|
-- load md with high byte of indirect address
|
-- pointed to by ea
|
-- pointed to by ea
|
-- increment ea
|
-- increment ea
|
--
|
--
|
when indirect_state =>
|
when indirect_state =>
|
-- increment ea
|
-- increment ea
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- fetch high byte
|
-- fetch high byte
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
next_state <= indirect2_state;
|
next_state <= indirect2_state;
|
--
|
--
|
-- load md with low byte of indirect address
|
-- load md with low byte of indirect address
|
-- pointed to by ea
|
-- pointed to by ea
|
-- ea has previously been incremented
|
-- ea has previously been incremented
|
--
|
--
|
when indirect2_state =>
|
when indirect2_state =>
|
-- fetch high byte
|
-- fetch high byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
next_state <= indirect3_state;
|
next_state <= indirect3_state;
|
--
|
--
|
-- complete idirect addressing
|
-- complete idirect addressing
|
-- by loading ea with md
|
-- by loading ea with md
|
--
|
--
|
when indirect3_state =>
|
when indirect3_state =>
|
-- load ea with md
|
-- load ea with md
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- return to previous state
|
-- return to previous state
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
--
|
--
|
-- ea holds the low byte of the absolute address
|
-- ea holds the low byte of the absolute address
|
-- Move ea low byte into ea high byte
|
-- Move ea low byte into ea high byte
|
-- load new ea low byte to for absolute 16 bit address
|
-- load new ea low byte to for absolute 16 bit address
|
-- advance the program counter
|
-- advance the program counter
|
--
|
--
|
when extended_state => -- fetch ea low byte
|
when extended_state => -- fetch ea low byte
|
-- increment pc
|
-- increment pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch next effective address bytes
|
-- fetch next effective address bytes
|
ea_ctrl <= fetch_next_ea;
|
ea_ctrl <= fetch_next_ea;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
-- return to previous state
|
-- return to previous state
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when lea_state => -- here on load effective address
|
when lea_state => -- here on load effective address
|
-- load index register with effective address
|
-- load index register with effective address
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= ea_right;
|
right_ctrl <= ea_right;
|
alu_ctrl <= alu_lea;
|
alu_ctrl <= alu_lea;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- leax
|
when "0000" => -- leax
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "0001" => -- leay
|
when "0001" => -- leay
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "0010" => -- leas
|
when "0010" => -- leas
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when "0011" => -- leau
|
when "0011" => -- leau
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- jump to subroutine
|
-- jump to subroutine
|
-- sp=sp-1
|
-- sp=sp-1
|
-- call push_return_lo_state to save pc
|
-- call push_return_lo_state to save pc
|
-- return to jmp_state
|
-- return to jmp_state
|
--
|
--
|
when jsr_state =>
|
when jsr_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- call push_return_state
|
-- call push_return_state
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
--
|
--
|
-- Load pc with ea
|
-- Load pc with ea
|
-- (JMP)
|
-- (JMP)
|
--
|
--
|
when jmp_state =>
|
when jmp_state =>
|
-- load PC with effective address
|
-- load PC with effective address
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= ea_right;
|
right_ctrl <= ea_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- long branch or branch to subroutine
|
-- long branch or branch to subroutine
|
-- pick up next md byte
|
-- pick up next md byte
|
-- md_hi = md_lo
|
-- md_hi = md_lo
|
-- md_lo = (pc)
|
-- md_lo = (pc)
|
-- pc=pc+1
|
-- pc=pc+1
|
-- if a lbsr push return address
|
-- if a lbsr push return address
|
-- continue to sbranch_state
|
-- continue to sbranch_state
|
-- to evaluate conditional branches
|
-- to evaluate conditional branches
|
--
|
--
|
when lbranch_state =>
|
when lbranch_state =>
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch the next byte into md_lo
|
-- fetch the next byte into md_lo
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
-- if lbsr - push return address
|
-- if lbsr - push return address
|
-- then continue on to short branch
|
-- then continue on to short branch
|
if op_code = "00010111" then
|
if op_code = "00010111" then
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= sbranch_state;
|
return_state <= sbranch_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
else
|
else
|
next_state <= sbranch_state;
|
next_state <= sbranch_state;
|
end if;
|
end if;
|
|
|
--
|
--
|
-- here to execute conditional branch
|
-- here to execute conditional branch
|
-- short conditional branch md = signed 8 bit offset
|
-- short conditional branch md = signed 8 bit offset
|
-- long branch md = 16 bit offset
|
-- long branch md = 16 bit offset
|
--
|
--
|
when sbranch_state =>
|
when sbranch_state =>
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
-- Test condition for branch
|
-- Test condition for branch
|
if op_code(7 downto 4) = "0010" then -- conditional branch
|
if op_code(7 downto 4) = "0010" then -- conditional branch
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- bra
|
when "0000" => -- bra
|
cond_true := (1 = 1);
|
cond_true := (1 = 1);
|
when "0001" => -- brn
|
when "0001" => -- brn
|
cond_true := (1 = 0);
|
cond_true := (1 = 0);
|
when "0010" => -- bhi
|
when "0010" => -- bhi
|
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
|
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
|
when "0011" => -- bls
|
when "0011" => -- bls
|
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
|
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
|
when "0100" => -- bcc/bhs
|
when "0100" => -- bcc/bhs
|
cond_true := (cc(CBIT) = '0');
|
cond_true := (cc(CBIT) = '0');
|
when "0101" => -- bcs/blo
|
when "0101" => -- bcs/blo
|
cond_true := (cc(CBIT) = '1');
|
cond_true := (cc(CBIT) = '1');
|
when "0110" => -- bne
|
when "0110" => -- bne
|
cond_true := (cc(ZBIT) = '0');
|
cond_true := (cc(ZBIT) = '0');
|
when "0111" => -- beq
|
when "0111" => -- beq
|
cond_true := (cc(ZBIT) = '1');
|
cond_true := (cc(ZBIT) = '1');
|
when "1000" => -- bvc
|
when "1000" => -- bvc
|
cond_true := (cc(VBIT) = '0');
|
cond_true := (cc(VBIT) = '0');
|
when "1001" => -- bvs
|
when "1001" => -- bvs
|
cond_true := (cc(VBIT) = '1');
|
cond_true := (cc(VBIT) = '1');
|
when "1010" => -- bpl
|
when "1010" => -- bpl
|
cond_true := (cc(NBIT) = '0');
|
cond_true := (cc(NBIT) = '0');
|
when "1011" => -- bmi
|
when "1011" => -- bmi
|
cond_true := (cc(NBIT) = '1');
|
cond_true := (cc(NBIT) = '1');
|
when "1100" => -- bge
|
when "1100" => -- bge
|
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
|
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
|
when "1101" => -- blt
|
when "1101" => -- blt
|
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
|
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
|
when "1110" => -- bgt
|
when "1110" => -- bgt
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
|
when "1111" => -- ble
|
when "1111" => -- ble
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
else
|
else
|
cond_true := (1 = 1); -- lbra, lbsr, bsr
|
cond_true := (1 = 1); -- lbra, lbsr, bsr
|
end if;
|
end if;
|
if cond_true then
|
if cond_true then
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
end if;
|
end if;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- push return address onto the S stack
|
-- push return address onto the S stack
|
--
|
--
|
-- (sp) = pc_lo
|
-- (sp) = pc_lo
|
-- sp = sp - 1
|
-- sp = sp - 1
|
--
|
--
|
when push_return_lo_state =>
|
when push_return_lo_state =>
|
-- decrement the sp
|
-- decrement the sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write PC low
|
-- write PC low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
next_state <= push_return_hi_state;
|
next_state <= push_return_hi_state;
|
|
|
--
|
--
|
-- push program counter hi byte onto the stack
|
-- push program counter hi byte onto the stack
|
-- (sp) = pc_hi
|
-- (sp) = pc_hi
|
-- sp = sp
|
-- sp = sp
|
-- return to originating state
|
-- return to originating state
|
--
|
--
|
when push_return_hi_state =>
|
when push_return_hi_state =>
|
-- write pc hi bytes
|
-- write pc hi bytes
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when pull_return_hi_state =>
|
when pull_return_hi_state =>
|
-- increment the sp
|
-- increment the sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc hi
|
-- read pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= pull_return_lo_state;
|
next_state <= pull_return_lo_state;
|
|
|
when pull_return_lo_state =>
|
when pull_return_lo_state =>
|
-- increment the SP
|
-- increment the SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when andcc_state =>
|
when andcc_state =>
|
-- AND CC with md
|
-- AND CC with md
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_andcc;
|
alu_ctrl <= alu_andcc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when orcc_state =>
|
when orcc_state =>
|
-- OR CC with md
|
-- OR CC with md
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_orcc;
|
alu_ctrl <= alu_orcc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when tfr_state =>
|
when tfr_state =>
|
-- select source register
|
-- select source register
|
case md(7 downto 4) is
|
case md(7 downto 4) is
|
when "0000" =>
|
when "0000" =>
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
when "0001" =>
|
when "0001" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "0010" =>
|
when "0010" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "0011" =>
|
when "0011" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when "0100" =>
|
when "0100" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
when "0101" =>
|
when "0101" =>
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
when "1000" =>
|
when "1000" =>
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
when "1001" =>
|
when "1001" =>
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
when "1010" =>
|
when "1010" =>
|
left_ctrl <= cc_left;
|
left_ctrl <= cc_left;
|
when "1011" =>
|
when "1011" =>
|
left_ctrl <= dp_left;
|
left_ctrl <= dp_left;
|
when others =>
|
when others =>
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
-- select destination register
|
-- select destination register
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" => -- accd
|
when "0000" => -- accd
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0001" => -- ix
|
when "0001" => -- ix
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "0010" => -- iy
|
when "0010" => -- iy
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "0011" => -- up
|
when "0011" => -- up
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when "0100" => -- sp
|
when "0100" => -- sp
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when "0101" => -- pc
|
when "0101" => -- pc
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
when "1000" => -- acca
|
when "1000" => -- acca
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1001" => -- accb
|
when "1001" => -- accb
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1010" => -- cc
|
when "1010" => -- cc
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1011" => --dp
|
when "1011" => --dp
|
dp_ctrl <= load_dp;
|
dp_ctrl <= load_dp;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when exg_state =>
|
when exg_state =>
|
-- save destination register
|
-- save destination register
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" =>
|
when "0000" =>
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
when "0001" =>
|
when "0001" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "0010" =>
|
when "0010" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
when "0011" =>
|
when "0011" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
when "0100" =>
|
when "0100" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
when "0101" =>
|
when "0101" =>
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
when "1000" =>
|
when "1000" =>
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
when "1001" =>
|
when "1001" =>
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
when "1010" =>
|
when "1010" =>
|
left_ctrl <= cc_left;
|
left_ctrl <= cc_left;
|
when "1011" =>
|
when "1011" =>
|
left_ctrl <= dp_left;
|
left_ctrl <= dp_left;
|
when others =>
|
when others =>
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- call tranfer microcode
|
-- call tranfer microcode
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= exg1_state;
|
return_state <= exg1_state;
|
next_state <= tfr_state;
|
next_state <= tfr_state;
|
|
|
when exg1_state =>
|
when exg1_state =>
|
-- restore destination
|
-- restore destination
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
-- save as source register
|
-- save as source register
|
case md(7 downto 4) is
|
case md(7 downto 4) is
|
when "0000" => -- accd
|
when "0000" => -- accd
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "0001" => -- ix
|
when "0001" => -- ix
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
when "0010" => -- iy
|
when "0010" => -- iy
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
when "0011" => -- up
|
when "0011" => -- up
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
when "0100" => -- sp
|
when "0100" => -- sp
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when "0101" => -- pc
|
when "0101" => -- pc
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
when "1000" => -- acca
|
when "1000" => -- acca
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
when "1001" => -- accb
|
when "1001" => -- accb
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
when "1010" => -- cc
|
when "1010" => -- cc
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
when "1011" => --dp
|
when "1011" => --dp
|
dp_ctrl <= load_dp;
|
dp_ctrl <= load_dp;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when mul_state =>
|
when mul_state =>
|
-- move acca to md
|
-- move acca to md
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
next_state <= mulea_state;
|
next_state <= mulea_state;
|
|
|
when mulea_state =>
|
when mulea_state =>
|
-- move accb to ea
|
-- move accb to ea
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
next_state <= muld_state;
|
next_state <= muld_state;
|
|
|
when muld_state =>
|
when muld_state =>
|
-- clear accd
|
-- clear accd
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
next_state <= mul0_state;
|
next_state <= mul0_state;
|
|
|
when mul0_state =>
|
when mul0_state =>
|
-- if bit 0 of ea set, add accd to md
|
-- if bit 0 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul1_state;
|
next_state <= mul1_state;
|
|
|
when mul1_state =>
|
when mul1_state =>
|
-- if bit 1 of ea set, add accd to md
|
-- if bit 1 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul2_state;
|
next_state <= mul2_state;
|
|
|
when mul2_state =>
|
when mul2_state =>
|
-- if bit 2 of ea set, add accd to md
|
-- if bit 2 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul3_state;
|
next_state <= mul3_state;
|
|
|
when mul3_state =>
|
when mul3_state =>
|
-- if bit 3 of ea set, add accd to md
|
-- if bit 3 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul4_state;
|
next_state <= mul4_state;
|
|
|
when mul4_state =>
|
when mul4_state =>
|
-- if bit 4 of ea set, add accd to md
|
-- if bit 4 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul5_state;
|
next_state <= mul5_state;
|
|
|
when mul5_state =>
|
when mul5_state =>
|
-- if bit 5 of ea set, add accd to md
|
-- if bit 5 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul6_state;
|
next_state <= mul6_state;
|
|
|
when mul6_state =>
|
when mul6_state =>
|
-- if bit 6 of ea set, add accd to md
|
-- if bit 6 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= mul7_state;
|
next_state <= mul7_state;
|
|
|
when mul7_state =>
|
when mul7_state =>
|
-- if bit 7 of ea set, add accd to md
|
-- if bit 7 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
end if;
|
end if;
|
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Enter here on pushs
|
-- Enter here on pushs
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when pshs_state =>
|
when pshs_state =>
|
-- decrement sp if any registers to be pushed
|
-- decrement sp if any registers to be pushed
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
|
-- idle address
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= cc_dout;
|
if ea(7 downto 0) = "00000000" then
|
if ea(7 downto 0) = "00000000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pshs_pcl_state;
|
next_state <= pshs_pcl_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pshs_upl_state;
|
next_state <= pshs_upl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshs_iyl_state;
|
next_state <= pshs_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_pcl_state =>
|
when pshs_pcl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
next_state <= pshs_pch_state;
|
next_state <= pshs_pch_state;
|
|
|
when pshs_pch_state =>
|
when pshs_pch_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(6 downto 0) = "0000000" then
|
if ea(6 downto 0) = "0000000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pshs_upl_state;
|
next_state <= pshs_upl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshs_iyl_state;
|
next_state <= pshs_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
|
|
when pshs_upl_state =>
|
when pshs_upl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_lo_dout;
|
dout_ctrl <= up_lo_dout;
|
next_state <= pshs_uph_state;
|
next_state <= pshs_uph_state;
|
|
|
when pshs_uph_state =>
|
when pshs_uph_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(5 downto 0) = "000000" then
|
if ea(5 downto 0) = "000000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_hi_dout;
|
dout_ctrl <= up_hi_dout;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pshs_iyl_state;
|
next_state <= pshs_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_iyl_state =>
|
when pshs_iyl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write iy low
|
-- write iy low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
next_state <= pshs_iyh_state;
|
next_state <= pshs_iyh_state;
|
|
|
when pshs_iyh_state =>
|
when pshs_iyh_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(4 downto 0) = "00000" then
|
if ea(4 downto 0) = "00000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write iy hi
|
-- write iy hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_ixl_state =>
|
when pshs_ixl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
next_state <= pshs_ixh_state;
|
next_state <= pshs_ixh_state;
|
|
|
when pshs_ixh_state =>
|
when pshs_ixh_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(3 downto 0) = "0000" then
|
if ea(3 downto 0) = "0000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_dp_state =>
|
when pshs_dp_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(2 downto 0) = "000" then
|
if ea(2 downto 0) = "000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write dp
|
-- write dp
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_accb_state =>
|
when pshs_accb_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(1 downto 0) = "00" then
|
if ea(1 downto 0) = "00" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_acca_state =>
|
when pshs_acca_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
else
|
else
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
end if;
|
end if;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_cc_state =>
|
when pshs_cc_state =>
|
-- idle sp
|
-- idle sp
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- enter here on PULS
|
-- enter here on PULS
|
-- ea hold register mask
|
-- ea hold register mask
|
--
|
--
|
when puls_state =>
|
when puls_state =>
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= puls_cc_state;
|
next_state <= puls_cc_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= puls_acca_state;
|
next_state <= puls_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= puls_accb_state;
|
next_state <= puls_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_cc_state =>
|
when puls_cc_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= puls_acca_state;
|
next_state <= puls_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= puls_accb_state;
|
next_state <= puls_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_acca_state =>
|
when puls_acca_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= puls_accb_state;
|
next_state <= puls_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_accb_state =>
|
when puls_accb_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_dp_state =>
|
when puls_dp_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_ixh_state =>
|
when puls_ixh_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull ix hi
|
-- pull ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= puls_ixl_state;
|
next_state <= puls_ixl_state;
|
|
|
when puls_ixl_state =>
|
when puls_ixl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_iyh_state =>
|
when puls_iyh_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull iy hi
|
-- pull iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= puls_iyl_state;
|
next_state <= puls_iyl_state;
|
|
|
when puls_iyl_state =>
|
when puls_iyl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_uph_state =>
|
when puls_uph_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull up hi
|
-- pull up hi
|
up_ctrl <= pull_hi_up;
|
up_ctrl <= pull_hi_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= puls_upl_state;
|
next_state <= puls_upl_state;
|
|
|
when puls_upl_state =>
|
when puls_upl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up low
|
-- read up low
|
up_ctrl <= pull_lo_up;
|
up_ctrl <= pull_lo_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_pch_state =>
|
when puls_pch_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= puls_pcl_state;
|
next_state <= puls_pcl_state;
|
|
|
when puls_pcl_state =>
|
when puls_pcl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Enter here on pshu
|
-- Enter here on pshu
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when pshu_state =>
|
when pshu_state =>
|
-- decrement up if any registers to be pushed
|
-- decrement up if any registers to be pushed
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(7 downto 0) = "00000000" then
|
if ea(7 downto 0) = "00000000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write idle bus
|
-- write idle bus
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pshu_pcl_state;
|
next_state <= pshu_pcl_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pshu_spl_state;
|
next_state <= pshu_spl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshu_iyl_state;
|
next_state <= pshu_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
--
|
--
|
-- push PC onto U stack
|
-- push PC onto U stack
|
--
|
--
|
when pshu_pcl_state =>
|
when pshu_pcl_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
next_state <= pshu_pch_state;
|
next_state <= pshu_pch_state;
|
|
|
when pshu_pch_state =>
|
when pshu_pch_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(6 downto 0) = "0000000" then
|
if ea(6 downto 0) = "0000000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pshu_spl_state;
|
next_state <= pshu_spl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshu_iyl_state;
|
next_state <= pshu_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_spl_state =>
|
when pshu_spl_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write sp low
|
-- write sp low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= sp_lo_dout;
|
dout_ctrl <= sp_lo_dout;
|
next_state <= pshu_sph_state;
|
next_state <= pshu_sph_state;
|
|
|
when pshu_sph_state =>
|
when pshu_sph_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(5 downto 0) = "000000" then
|
if ea(5 downto 0) = "000000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write sp hi
|
-- write sp hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= sp_hi_dout;
|
dout_ctrl <= sp_hi_dout;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pshu_iyl_state;
|
next_state <= pshu_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_iyl_state =>
|
when pshu_iyl_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write iy low
|
-- write iy low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
next_state <= pshu_iyh_state;
|
next_state <= pshu_iyh_state;
|
|
|
when pshu_iyh_state =>
|
when pshu_iyh_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(4 downto 0) = "00000" then
|
if ea(4 downto 0) = "00000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write iy hi
|
-- write iy hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_ixl_state =>
|
when pshu_ixl_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
next_state <= pshu_ixh_state;
|
next_state <= pshu_ixh_state;
|
|
|
when pshu_ixh_state =>
|
when pshu_ixh_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(3 downto 0) = "0000" then
|
if ea(3 downto 0) = "0000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_dp_state =>
|
when pshu_dp_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(2 downto 0) = "000" then
|
if ea(2 downto 0) = "000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write dp
|
-- write dp
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_accb_state =>
|
when pshu_accb_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(1 downto 0) = "00" then
|
if ea(1 downto 0) = "00" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_acca_state =>
|
when pshu_acca_state =>
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(0) = '0' then
|
if ea(0) = '0' then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_cc_state =>
|
when pshu_cc_state =>
|
-- idle up
|
-- idle up
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- enter here on PULU
|
-- enter here on PULU
|
-- ea hold register mask
|
-- ea hold register mask
|
--
|
--
|
when pulu_state =>
|
when pulu_state =>
|
-- idle UP
|
-- idle UP
|
-- idle bus
|
-- idle bus
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pulu_cc_state;
|
next_state <= pulu_cc_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pulu_acca_state;
|
next_state <= pulu_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pulu_accb_state;
|
next_state <= pulu_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_cc_state =>
|
when pulu_cc_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pulu_acca_state;
|
next_state <= pulu_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pulu_accb_state;
|
next_state <= pulu_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_acca_state =>
|
when pulu_acca_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pulu_accb_state;
|
next_state <= pulu_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_accb_state =>
|
when pulu_accb_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_dp_state =>
|
when pulu_dp_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_ixh_state =>
|
when pulu_ixh_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read ix hi
|
-- read ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
next_state <= pulu_ixl_state;
|
next_state <= pulu_ixl_state;
|
|
|
when pulu_ixl_state =>
|
when pulu_ixl_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_iyh_state =>
|
when pulu_iyh_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read iy hi
|
-- read iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
next_state <= pulu_iyl_state;
|
next_state <= pulu_iyl_state;
|
|
|
when pulu_iyl_state =>
|
when pulu_iyl_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_sph_state =>
|
when pulu_sph_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read sp hi
|
-- read sp hi
|
sp_ctrl <= pull_hi_sp;
|
sp_ctrl <= pull_hi_sp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
next_state <= pulu_spl_state;
|
next_state <= pulu_spl_state;
|
|
|
when pulu_spl_state =>
|
when pulu_spl_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read sp low
|
-- read sp low
|
sp_ctrl <= pull_lo_sp;
|
sp_ctrl <= pull_lo_sp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_pch_state =>
|
when pulu_pch_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
next_state <= pulu_pcl_state;
|
next_state <= pulu_pcl_state;
|
|
|
when pulu_pcl_state =>
|
when pulu_pcl_state =>
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- pop the Condition codes
|
-- pop the Condition codes
|
--
|
--
|
when rti_cc_state =>
|
when rti_cc_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_entire_state;
|
next_state <= rti_entire_state;
|
|
|
--
|
--
|
-- Added RTI cycle 11th July 2006 John Kent.
|
-- Added RTI cycle 11th July 2006 John Kent.
|
-- test the "Entire" Flag
|
-- test the "Entire" Flag
|
-- that has just been popped off the stack
|
-- that has just been popped off the stack
|
--
|
--
|
when rti_entire_state =>
|
when rti_entire_state =>
|
--
|
--
|
-- The Entire flag must be recovered from the stack
|
-- The Entire flag must be recovered from the stack
|
-- before testing.
|
-- before testing.
|
--
|
--
|
if cc(EBIT) = '1' then
|
if cc(EBIT) = '1' then
|
next_state <= rti_acca_state;
|
next_state <= rti_acca_state;
|
else
|
else
|
next_state <= rti_pch_state;
|
next_state <= rti_pch_state;
|
end if;
|
end if;
|
|
|
when rti_acca_state =>
|
when rti_acca_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_accb_state;
|
next_state <= rti_accb_state;
|
|
|
when rti_accb_state =>
|
when rti_accb_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_dp_state;
|
next_state <= rti_dp_state;
|
|
|
when rti_dp_state =>
|
when rti_dp_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_ixh_state;
|
next_state <= rti_ixh_state;
|
|
|
when rti_ixh_state =>
|
when rti_ixh_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix hi
|
-- read ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_ixl_state;
|
next_state <= rti_ixl_state;
|
|
|
when rti_ixl_state =>
|
when rti_ixl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_iyh_state;
|
next_state <= rti_iyh_state;
|
|
|
when rti_iyh_state =>
|
when rti_iyh_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy hi
|
-- read iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_iyl_state;
|
next_state <= rti_iyl_state;
|
|
|
when rti_iyl_state =>
|
when rti_iyl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_uph_state;
|
next_state <= rti_uph_state;
|
|
|
|
|
when rti_uph_state =>
|
when rti_uph_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up hi
|
-- read up hi
|
up_ctrl <= pull_hi_up;
|
up_ctrl <= pull_hi_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_upl_state;
|
next_state <= rti_upl_state;
|
|
|
when rti_upl_state =>
|
when rti_upl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up low
|
-- read up low
|
up_ctrl <= pull_lo_up;
|
up_ctrl <= pull_lo_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_pch_state;
|
next_state <= rti_pch_state;
|
|
|
when rti_pch_state =>
|
when rti_pch_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= rti_pcl_state;
|
next_state <= rti_pcl_state;
|
|
|
when rti_pcl_state =>
|
when rti_pcl_state =>
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc low
|
-- pull pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- here on IRQ or NMI interrupt
|
-- here on IRQ or NMI interrupt
|
-- pre decrement the sp
|
-- pre decrement the sp
|
-- Idle bus cycle
|
-- Idle bus cycle
|
--
|
--
|
when int_nmiirq_state =>
|
when int_nmiirq_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
--
|
--
|
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
|
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
|
-- clear Entire Flag on FIRQ
|
-- clear Entire Flag on FIRQ
|
-- before stacking all registers
|
-- before stacking all registers
|
--
|
--
|
when int_entire_state =>
|
when int_entire_state =>
|
-- set entire flag
|
-- set entire flag
|
alu_ctrl <= alu_see;
|
alu_ctrl <= alu_see;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
next_state <= int_pcl_state;
|
next_state <= int_pcl_state;
|
|
|
--
|
--
|
-- here on FIRQ interrupt
|
-- here on FIRQ interrupt
|
-- pre decrement the sp
|
-- pre decrement the sp
|
-- Idle bus cycle
|
-- Idle bus cycle
|
--
|
--
|
when int_firq_state =>
|
when int_firq_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
next_state <= int_fast_state;
|
next_state <= int_fast_state;
|
--
|
--
|
-- clear Entire Flag on FIRQ
|
-- clear Entire Flag on FIRQ
|
-- before stacking all registers
|
-- before stacking all registers
|
--
|
--
|
when int_fast_state =>
|
when int_fast_state =>
|
-- clear entire flag
|
-- clear entire flag
|
alu_ctrl <= alu_cle;
|
alu_ctrl <= alu_cle;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
next_state <= int_pcl_state;
|
next_state <= int_pcl_state;
|
|
|
when int_pcl_state =>
|
when int_pcl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
next_state <= int_pch_state;
|
next_state <= int_pch_state;
|
|
|
when int_pch_state =>
|
when int_pch_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
if cc(EBIT) = '1' then
|
if cc(EBIT) = '1' then
|
next_state <= int_upl_state;
|
next_state <= int_upl_state;
|
else
|
else
|
next_state <= int_cc_state;
|
next_state <= int_cc_state;
|
end if;
|
end if;
|
|
|
when int_upl_state =>
|
when int_upl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write up low
|
-- write up low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_lo_dout;
|
dout_ctrl <= up_lo_dout;
|
next_state <= int_uph_state;
|
next_state <= int_uph_state;
|
|
|
when int_uph_state =>
|
when int_uph_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_hi_dout;
|
dout_ctrl <= up_hi_dout;
|
next_state <= int_iyl_state;
|
next_state <= int_iyl_state;
|
|
|
when int_iyl_state =>
|
when int_iyl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
next_state <= int_iyh_state;
|
next_state <= int_iyh_state;
|
|
|
when int_iyh_state =>
|
when int_iyh_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
next_state <= int_ixl_state;
|
next_state <= int_ixl_state;
|
|
|
when int_ixl_state =>
|
when int_ixl_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
next_state <= int_ixh_state;
|
next_state <= int_ixh_state;
|
|
|
when int_ixh_state =>
|
when int_ixh_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
next_state <= int_dp_state;
|
next_state <= int_dp_state;
|
|
|
when int_dp_state =>
|
when int_dp_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
next_state <= int_accb_state;
|
next_state <= int_accb_state;
|
|
|
when int_accb_state =>
|
when int_accb_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
next_state <= int_acca_state;
|
next_state <= int_acca_state;
|
|
|
when int_acca_state =>
|
when int_acca_state =>
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
next_state <= int_cc_state;
|
next_state <= int_cc_state;
|
|
|
when int_cc_state =>
|
when int_cc_state =>
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
case iv is
|
case iv is
|
when NMI_VEC =>
|
when NMI_VEC =>
|
next_state <= int_maskif_state;
|
next_state <= int_maskif_state;
|
when SWI_VEC =>
|
when SWI_VEC =>
|
next_state <= int_maskif_state;
|
next_state <= int_maskif_state;
|
when FIRQ_VEC =>
|
when FIRQ_VEC =>
|
next_state <= int_maskif_state;
|
next_state <= int_maskif_state;
|
when IRQ_VEC =>
|
when IRQ_VEC =>
|
next_state <= int_maski_state;
|
next_state <= int_maski_state;
|
when SWI2_VEC =>
|
when SWI2_VEC =>
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
when SWI3_VEC =>
|
when SWI3_VEC =>
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
when others =>
|
when others =>
|
if op_code = "00111100" then -- CWAI
|
if op_code = "00111100" then -- CWAI
|
next_state <= int_cwai_state;
|
next_state <= int_cwai_state;
|
else
|
else
|
next_state <= rti_cc_state; -- spurious interrupt, do a RTI
|
next_state <= rti_cc_state; -- spurious interrupt, do a RTI
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- wait here for an inteerupt
|
-- wait here for an inteerupt
|
--
|
--
|
when int_cwai_state =>
|
when int_cwai_state =>
|
if (nmi_req = '1') and (nmi_ack='0') then
|
if (nmi_req = '1') and (nmi_ack='0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
next_state <= int_maskif_state;
|
next_state <= int_maskif_state;
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if (nmi_req = '0') and (nmi_ack='1') then
|
if (nmi_req = '0') and (nmi_ack='1') then
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
end if;
|
end if;
|
--
|
--
|
-- FIRQ is level sensitive
|
-- FIRQ is level sensitive
|
--
|
--
|
if (firq = '1') and (cc(FBIT) = '0') then
|
if (firq = '1') and (cc(FBIT) = '0') then
|
iv_ctrl <= firq_iv;
|
iv_ctrl <= firq_iv;
|
next_state <= int_maskif_state;
|
next_state <= int_maskif_state;
|
--
|
--
|
-- IRQ is level sensitive
|
-- IRQ is level sensitive
|
--
|
--
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
iv_ctrl <= irq_iv;
|
iv_ctrl <= irq_iv;
|
next_state <= int_maski_state;
|
next_state <= int_maski_state;
|
else
|
else
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= int_cwai_state;
|
next_state <= int_cwai_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when int_maski_state =>
|
when int_maski_state =>
|
alu_ctrl <= alu_sei;
|
alu_ctrl <= alu_sei;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
|
|
when int_maskif_state =>
|
when int_maskif_state =>
|
alu_ctrl <= alu_seif;
|
alu_ctrl <= alu_seif;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
|
|
--
|
--
|
-- According to the 6809 programming manual:
|
-- According to the 6809 programming manual:
|
-- If an interrupt is received and is masked
|
-- If an interrupt is received and is masked
|
-- or lasts for less than three cycles, the PC
|
-- or lasts for less than three cycles, the PC
|
-- will advance to the next instruction.
|
-- will advance to the next instruction.
|
-- If an interrupt is unmasked and lasts
|
-- If an interrupt is unmasked and lasts
|
-- for more than three cycles, an interrupt
|
-- for more than three cycles, an interrupt
|
-- will be generated.
|
-- will be generated.
|
-- Note that I don't wait 3 clock cycles.
|
-- Note that I don't wait 3 clock cycles.
|
-- John Kent 11th July 2006
|
-- John Kent 11th July 2006
|
--
|
--
|
when sync_state =>
|
when sync_state =>
|
if (nmi_req = '1') and (nmi_ack='0') then
|
if (nmi_req = '1') and (nmi_ack='0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
next_state <= int_nmiirq_state;
|
next_state <= int_nmiirq_state;
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if (nmi_req = '0') and (nmi_ack='1') then
|
if (nmi_req = '0') and (nmi_ack='1') then
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
end if;
|
end if;
|
--
|
--
|
-- FIRQ is level sensitive
|
-- FIRQ is level sensitive
|
--
|
--
|
if (firq = '1') then
|
if (firq = '1') then
|
if (cc(FBIT) = '0') then
|
if (cc(FBIT) = '0') then
|
iv_ctrl <= firq_iv;
|
iv_ctrl <= firq_iv;
|
next_state <= int_firq_state;
|
next_state <= int_firq_state;
|
else
|
else
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
--
|
--
|
-- IRQ is level sensitive
|
-- IRQ is level sensitive
|
--
|
--
|
elsif (irq = '1') then
|
elsif (irq = '1') then
|
if (cc(IBIT) = '0') then
|
if (cc(IBIT) = '0') then
|
iv_ctrl <= irq_iv;
|
iv_ctrl <= irq_iv;
|
next_state <= int_nmiirq_state;
|
next_state <= int_nmiirq_state;
|
else
|
else
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
else
|
else
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= sync_state;
|
next_state <= sync_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
when halt_state =>
|
when halt_state =>
|
if halt = '1' then
|
if halt = '1' then
|
next_state <= halt_state;
|
next_state <= halt_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when others => -- halt on undefine states
|
when others => -- halt on undefine states
|
next_state <= error_state;
|
next_state <= error_state;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|