--===========================================================================--
|
--===========================================================================--
|
-- --
|
-- --
|
-- Synthesizable Serial Peripheral Interface Master --
|
-- Synthesizable Serial Peripheral Interface Master --
|
-- --
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-- --
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- File name : spi-master.vhd
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-- File name : spi-master.vhd
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--
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--
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-- Entity name : spi-master
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-- Entity name : spi-master
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--
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--
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-- Purpose : Implements a SPI Master Controller
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-- Purpose : Implements a SPI Master Controller
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--
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--
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-- Dependencies : ieee.std_logic_1164
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
|
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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-- ieee.numeric_std
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-- unisim.vcomponents
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--
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--
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-- Author : Hans Huebner
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-- Author : Hans Huebner
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--
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--
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-- Email : hans@huebner.org
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-- Email : hans@huebner.org
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--
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--
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-- Web : http://opencores.org/project,system09
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-- Web : http://opencores.org/project,system09
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--
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--
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-- Description : This core implements a SPI master interface.
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-- Description : This core implements a SPI master interface.
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-- Transfer size is 4, 8, 12 or 16 bits.
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-- Transfer size is 4, 8, 12 or 16 bits.
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-- The SPI clock is 0 when idle, sampled on
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-- The SPI clock is 0 when idle, sampled on
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-- the rising edge of the SPI clock.
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-- the rising edge of the SPI clock.
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-- The SPI clock is derived from the bus clock input
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-- The SPI clock is derived from the bus clock input
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-- divided by 2, 4, 8 or 16.
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-- divided by 2, 4, 8 or 16.
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--
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--
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-- clk, reset, cs, rw, addr, data_in, data_out and irq
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-- clk, reset, cs, rw, addr, data_in, data_out and irq
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-- represent the System09 bus interface.
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-- represent the System09 bus interface.
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-- spi_clk, spi_mosi, spi_miso and spi_cs_n are the
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-- spi_clk, spi_mosi, spi_miso and spi_cs_n are the
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-- standard SPI signals meant to be routed off-chip.
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-- standard SPI signals meant to be routed off-chip.
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--
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--
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-- The SPI core provides for four register addresses
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-- The SPI core provides for four register addresses
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-- that the CPU can read or writen to:
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-- that the CPU can read or writen to:
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--
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--
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-- Base + $00 -> DL: Data Low LSB
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-- Base + $00 -> DL: Data Low LSB
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-- Base + $01 -> DH: Data High MSB
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-- Base + $01 -> DH: Data High MSB
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-- Base + $02 -> CS: Command/Status
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-- Base + $02 -> CS: Command/Status
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-- Base + $03 -> CO: Config
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-- Base + $03 -> CO: Config
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--
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--
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-- CS: Write bits:
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-- CS: Write bits:
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--
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--
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-- CS[0] START : Start transfer
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-- CS[0] START : Start transfer
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-- CS[1] END : Deselect device after transfer
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-- CS[1] END : Deselect device after transfer
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-- (or immediately if START = '0')
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-- (or immediately if START = '0')
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-- CS[2] IRQEN : Generate IRQ at end of transfer
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-- CS[2] IRQEN : Generate IRQ at end of transfer
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-- CS[6:4] SPIAD : SPI device address
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-- CS[6:4] SPIAD : SPI device address
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--
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--
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-- CS: Read bits
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-- CS: Read bits
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--
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--
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-- CS[0] BUSY : Currently transmitting data
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-- CS[0] BUSY : Currently transmitting data
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--
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--
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-- CO: Write bits
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-- CO: Write bits
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--
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--
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-- CO[1:0] DIVIDE: SPI clock divisor,
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-- CO[1:0] DIVIDE: SPI clock divisor,
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-- 00=clk/2,
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-- 00=clk/2,
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-- 01=clk/4,
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-- 01=clk/4,
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-- 10=clk/8,
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-- 10=clk/8,
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-- 11=clk/16
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-- 11=clk/16
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-- CO[3:2] LENGTH: Transfer length,
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-- CO[3:2] LENGTH: Transfer length,
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-- 00= 4 bits,
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-- 00= 4 bits,
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-- 01= 8 bits,
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-- 01= 8 bits,
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-- 10=12 bits,
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-- 10=12 bits,
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-- 11=16 bits
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-- 11=16 bits
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--
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--
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-- Copyright (C) 2009 - 2010 Hans Huebner
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-- Copyright (C) 2009 - 2010 Hans Huebner
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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--
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--
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--===========================================================================--
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--===========================================================================--
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-- --
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-- --
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-- Revision History --
|
-- Revision History --
|
-- --
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-- --
|
--===========================================================================--
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--===========================================================================--
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--
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--
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-- Version Author Date Description
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-- Version Author Date Description
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--
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--
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-- 0.1 Hans Huebner 23 February 2009 SPI bus master for System09
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-- 0.1 Hans Huebner 23 February 2009 SPI bus master for System09
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-- 0.2 John Kent 16 June 2010 Added GPL notice
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-- 0.2 John Kent 16 June 2010 Added GPL notice
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--
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--
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--
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--
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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entity spi_master is
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entity spi_master is
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port (
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port (
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--
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--
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-- CPU Interface Signals
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-- CPU Interface Signals
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--
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--
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector(1 downto 0);
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addr : in std_logic_vector(1 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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irq : out std_logic;
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--
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--
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-- SPI Interface Signals
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-- SPI Interface Signals
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--
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--
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spi_miso : in std_logic;
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spi_miso : in std_logic;
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spi_mosi : out std_logic;
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spi_mosi : out std_logic;
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spi_clk : out std_logic;
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spi_clk : out std_logic;
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spi_cs_n : out std_logic_vector(7 downto 0)
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spi_cs_n : out std_logic_vector(7 downto 0)
|
);
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);
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end;
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end;
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|
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architecture rtl of spi_master is
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architecture rtl of spi_master is
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|
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-- State type of the SPI transfer state machine
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-- State type of the SPI transfer state machine
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type state_type is (s_idle, s_running);
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type state_type is (s_idle, s_running);
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signal state : state_type;
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signal state : state_type;
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-- Shift register
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-- Shift register
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signal shift_reg : std_logic_vector(15 downto 0);
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signal shift_reg : std_logic_vector(15 downto 0);
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-- Buffer to hold data to be sent
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-- Buffer to hold data to be sent
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signal spi_data_buf : std_logic_vector(15 downto 0);
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signal spi_data_buf : std_logic_vector(15 downto 0);
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-- Start transmission flag
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-- Start transmission flag
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signal start : std_logic;
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signal start : std_logic;
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-- Number of bits transfered
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-- Number of bits transfered
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signal count : std_logic_vector(3 downto 0);
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signal count : std_logic_vector(3 downto 0);
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-- Buffered SPI clock
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-- Buffered SPI clock
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signal spi_clk_buf : std_logic;
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signal spi_clk_buf : std_logic;
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-- Buffered SPI clock output
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-- Buffered SPI clock output
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signal spi_clk_out : std_logic;
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signal spi_clk_out : std_logic;
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-- Previous SPI clock state
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-- Previous SPI clock state
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signal prev_spi_clk : std_logic;
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signal prev_spi_clk : std_logic;
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-- Number of clk cycles-1 in this SPI clock period
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-- Number of clk cycles-1 in this SPI clock period
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signal spi_clk_count : std_logic_vector(2 downto 0);
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signal spi_clk_count : std_logic_vector(2 downto 0);
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-- SPI clock divisor
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-- SPI clock divisor
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signal spi_clk_divide : std_logic_vector(1 downto 0);
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signal spi_clk_divide : std_logic_vector(1 downto 0);
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-- SPI transfer length
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-- SPI transfer length
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signal transfer_length : std_logic_vector(1 downto 0);
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signal transfer_length : std_logic_vector(1 downto 0);
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-- Flag to indicate that the SPI slave should be deselected after the current
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-- Flag to indicate that the SPI slave should be deselected after the current
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-- transfer
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-- transfer
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signal deselect : std_logic;
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signal deselect : std_logic;
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-- Flag to indicate that an IRQ should be generated at the end of a transfer
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-- Flag to indicate that an IRQ should be generated at the end of a transfer
|
signal irq_enable : std_logic;
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signal irq_enable : std_logic;
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-- Internal chip select signal, will be demultiplexed through the cs_mux
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-- Internal chip select signal, will be demultiplexed through the cs_mux
|
signal spi_cs : std_logic;
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signal spi_cs : std_logic;
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-- Current SPI device address
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-- Current SPI device address
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signal spi_addr : std_logic_vector(2 downto 0);
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signal spi_addr : std_logic_vector(2 downto 0);
|
begin
|
begin
|
|
|
-- Read CPU bus into internal registers
|
-- Read CPU bus into internal registers
|
cpu_write : process(clk, reset)
|
cpu_write : process(clk, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
deselect <= '0';
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deselect <= '0';
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irq_enable <= '0';
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irq_enable <= '0';
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start <= '0';
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start <= '0';
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spi_clk_divide <= "11";
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spi_clk_divide <= "11";
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transfer_length <= "11";
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transfer_length <= "11";
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spi_data_buf <= (others => '0');
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spi_data_buf <= (others => '0');
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elsif falling_edge(clk) then
|
elsif falling_edge(clk) then
|
start <= '0';
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start <= '0';
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if cs = '1' and rw = '0' then
|
if cs = '1' and rw = '0' then
|
case addr is
|
case addr is
|
when "00" =>
|
when "00" =>
|
spi_data_buf(7 downto 0) <= data_in;
|
spi_data_buf(7 downto 0) <= data_in;
|
when "01" =>
|
when "01" =>
|
spi_data_buf(15 downto 8) <= data_in;
|
spi_data_buf(15 downto 8) <= data_in;
|
when "10" =>
|
when "10" =>
|
start <= data_in(0);
|
start <= data_in(0);
|
deselect <= data_in(1);
|
deselect <= data_in(1);
|
irq_enable <= data_in(2);
|
irq_enable <= data_in(2);
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spi_addr <= data_in(6 downto 4);
|
spi_addr <= data_in(6 downto 4);
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when "11" =>
|
when "11" =>
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spi_clk_divide <= data_in(1 downto 0);
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spi_clk_divide <= data_in(1 downto 0);
|
transfer_length <= data_in(3 downto 2);
|
transfer_length <= data_in(3 downto 2);
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Provide data for the CPU to read
|
-- Provide data for the CPU to read
|
cpu_read : process(shift_reg, addr, state, deselect, start)
|
cpu_read : process(shift_reg, addr, state, deselect, start)
|
begin
|
begin
|
data_out <= (others => '0');
|
data_out <= (others => '0');
|
case addr is
|
case addr is
|
when "00" =>
|
when "00" =>
|
data_out <= shift_reg(7 downto 0);
|
data_out <= shift_reg(7 downto 0);
|
when "01" =>
|
when "01" =>
|
data_out <= shift_reg(15 downto 8);
|
data_out <= shift_reg(15 downto 8);
|
when "10" =>
|
when "10" =>
|
if state = s_idle then
|
if state = s_idle then
|
data_out(0) <= '0';
|
data_out(0) <= '0';
|
else
|
else
|
data_out(0) <= '1';
|
data_out(0) <= '1';
|
end if;
|
end if;
|
data_out(1) <= deselect;
|
data_out(1) <= deselect;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
spi_cs_n <= "11111110" when spi_addr = "000" and spi_cs = '1' else
|
spi_cs_n <= "11111110" when spi_addr = "000" and spi_cs = '1' else
|
"11111101" when spi_addr = "001" and spi_cs = '1' else
|
"11111101" when spi_addr = "001" and spi_cs = '1' else
|
"11111011" when spi_addr = "010" and spi_cs = '1' else
|
"11111011" when spi_addr = "010" and spi_cs = '1' else
|
"11110111" when spi_addr = "011" and spi_cs = '1' else
|
"11110111" when spi_addr = "011" and spi_cs = '1' else
|
"11101111" when spi_addr = "100" and spi_cs = '1' else
|
"11101111" when spi_addr = "100" and spi_cs = '1' else
|
"11011111" when spi_addr = "101" and spi_cs = '1' else
|
"11011111" when spi_addr = "101" and spi_cs = '1' else
|
"10111111" when spi_addr = "110" and spi_cs = '1' else
|
"10111111" when spi_addr = "110" and spi_cs = '1' else
|
"01111111" when spi_addr = "111" and spi_cs = '1' else
|
"01111111" when spi_addr = "111" and spi_cs = '1' else
|
"11111111";
|
"11111111";
|
|
|
-- SPI transfer state machine
|
-- SPI transfer state machine
|
spi_proc : process(clk, reset)
|
spi_proc : process(clk, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
count <= (others => '0');
|
count <= (others => '0');
|
shift_reg <= (others => '0');
|
shift_reg <= (others => '0');
|
prev_spi_clk <= '0';
|
prev_spi_clk <= '0';
|
spi_clk_out <= '0';
|
spi_clk_out <= '0';
|
spi_cs <= '0';
|
spi_cs <= '0';
|
state <= s_idle;
|
state <= s_idle;
|
irq <= 'Z';
|
irq <= 'Z';
|
elsif falling_edge(clk) then
|
elsif falling_edge(clk) then
|
prev_spi_clk <= spi_clk_buf;
|
prev_spi_clk <= spi_clk_buf;
|
irq <= 'Z';
|
irq <= 'Z';
|
case state is
|
case state is
|
when s_idle =>
|
when s_idle =>
|
if start = '1' then
|
if start = '1' then
|
count <= (others => '0');
|
count <= (others => '0');
|
shift_reg <= spi_data_buf;
|
shift_reg <= spi_data_buf;
|
spi_cs <= '1';
|
spi_cs <= '1';
|
state <= s_running;
|
state <= s_running;
|
elsif deselect = '1' then
|
elsif deselect = '1' then
|
spi_cs <= '0';
|
spi_cs <= '0';
|
end if;
|
end if;
|
when s_running =>
|
when s_running =>
|
if prev_spi_clk = '1' and spi_clk_buf = '0' then
|
if prev_spi_clk = '1' and spi_clk_buf = '0' then
|
spi_clk_out <= '0';
|
spi_clk_out <= '0';
|
count <= count + "0001";
|
count <= count + "0001";
|
shift_reg <= shift_reg(14 downto 0) & spi_miso;
|
shift_reg <= shift_reg(14 downto 0) & spi_miso;
|
if ((count = "0011" and transfer_length = "00")
|
if ((count = "0011" and transfer_length = "00")
|
or (count = "0111" and transfer_length = "01")
|
or (count = "0111" and transfer_length = "01")
|
or (count = "1011" and transfer_length = "10")
|
or (count = "1011" and transfer_length = "10")
|
or (count = "1111" and transfer_length = "11")) then
|
or (count = "1111" and transfer_length = "11")) then
|
if deselect = '1' then
|
if deselect = '1' then
|
spi_cs <= '0';
|
spi_cs <= '0';
|
end if;
|
end if;
|
if irq_enable = '1' then
|
if irq_enable = '1' then
|
irq <= '1';
|
irq <= '1';
|
end if;
|
end if;
|
state <= s_idle;
|
state <= s_idle;
|
end if;
|
end if;
|
elsif prev_spi_clk = '0' and spi_clk_buf = '1' then
|
elsif prev_spi_clk = '0' and spi_clk_buf = '1' then
|
spi_clk_out <= '1';
|
spi_clk_out <= '1';
|
end if;
|
end if;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Generate SPI clock
|
-- Generate SPI clock
|
spi_clock_gen : process(clk, reset)
|
spi_clock_gen : process(clk, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
spi_clk_count <= (others => '0');
|
spi_clk_count <= (others => '0');
|
spi_clk_buf <= '0';
|
spi_clk_buf <= '0';
|
elsif falling_edge(clk) then
|
elsif falling_edge(clk) then
|
if state = s_running then
|
if state = s_running then
|
if ((spi_clk_divide = "00")
|
if ((spi_clk_divide = "00")
|
or (spi_clk_divide = "01" and spi_clk_count = "001")
|
or (spi_clk_divide = "01" and spi_clk_count = "001")
|
or (spi_clk_divide = "10" and spi_clk_count = "011")
|
or (spi_clk_divide = "10" and spi_clk_count = "011")
|
or (spi_clk_divide = "11" and spi_clk_count = "111")) then
|
or (spi_clk_divide = "11" and spi_clk_count = "111")) then
|
spi_clk_buf <= not spi_clk_buf;
|
spi_clk_buf <= not spi_clk_buf;
|
spi_clk_count <= (others => '0');
|
spi_clk_count <= (others => '0');
|
else
|
else
|
spi_clk_count <= spi_clk_count + "001";
|
spi_clk_count <= spi_clk_count + "001";
|
end if;
|
end if;
|
else
|
else
|
spi_clk_buf <= '0';
|
spi_clk_buf <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
spi_mosi_mux : process(shift_reg, transfer_length)
|
spi_mosi_mux : process(shift_reg, transfer_length)
|
begin
|
begin
|
case transfer_length is
|
case transfer_length is
|
when "00" =>
|
when "00" =>
|
spi_mosi <= shift_reg(3);
|
spi_mosi <= shift_reg(3);
|
when "01" =>
|
when "01" =>
|
spi_mosi <= shift_reg(7);
|
spi_mosi <= shift_reg(7);
|
when "10" =>
|
when "10" =>
|
spi_mosi <= shift_reg(11);
|
spi_mosi <= shift_reg(11);
|
when "11" =>
|
when "11" =>
|
spi_mosi <= shift_reg(15);
|
spi_mosi <= shift_reg(15);
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
spi_clk <= spi_clk_out;
|
spi_clk <= spi_clk_out;
|
|
|
end rtl;
|
end rtl;
|
|
|
