--===========================================================================----
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--===========================================================================----
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--
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--
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-- S Y N T H E Z I A B L E spp - Simple Parallel Port
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-- S Y N T H E Z I A B L E spp - Simple Parallel Port
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--
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--
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-- www.OpenCores.Org - September 2003
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-- www.OpenCores.Org - September 2003
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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--
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--
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-- File name : spp.vhd
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-- File name : spp.vhd
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--
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--
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-- Purpose : Simple Parallel Port for System09
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-- Purpose : Simple Parallel Port for System09
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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--
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--
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-- Uses : None
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-- Uses : None
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- Revision History:
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-- Revision History:
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- Version 0.1 - 6th Sep 2008
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-- Version 0.1 - 6th Sep 2008
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-- Generated from ioport.vhd
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-- Generated from ioport.vhd
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--
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--
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--===========================================================================
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--===========================================================================
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--
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--
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-- Parallel printer port pin assignment
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-- Parallel printer port pin assignment
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--
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--
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-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
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-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
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-- 1 nStrobe Write_n Out Control-0 Yes
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-- 1 nStrobe Write_n Out Control-0 Yes
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-- 2 Data0 Data0 In/Out Data-0 No
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-- 2 Data0 Data0 In/Out Data-0 No
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-- 3 Data1 Data1 In/Out Data-1 No
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-- 3 Data1 Data1 In/Out Data-1 No
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-- 4 Data2 Data2 In/Out Data-2 No
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-- 4 Data2 Data2 In/Out Data-2 No
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-- 5 Data3 Data3 In/Out Data-3 No
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-- 5 Data3 Data3 In/Out Data-3 No
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-- 6 Data4 Data4 In/Out Data-4 No
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-- 6 Data4 Data4 In/Out Data-4 No
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-- 7 Data5 Data5 In/Out Data-5 No
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-- 7 Data5 Data5 In/Out Data-5 No
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-- 8 Data6 Data6 In/Out Data-6 No
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-- 8 Data6 Data6 In/Out Data-6 No
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-- 9 Data7 Data7 In/Out Data-7 No
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-- 9 Data7 Data7 In/Out Data-7 No
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-- 10 nAck Interrupt In Status-6 No
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-- 10 nAck Interrupt In Status-6 No
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-- 11 Busy Wait In Status-7 Yes
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-- 11 Busy Wait In Status-7 Yes
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-- 12 Paper-Out Spare In Status-5 No
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-- 12 Paper-Out Spare In Status-5 No
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-- 13 Select Spare In Status-4 No
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-- 13 Select Spare In Status-4 No
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--
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--
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-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
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-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
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-- 15 nError Spare In Status-3 No
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-- 15 nError Spare In Status-3 No
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-- 16 nInitialize Reset Out Control-2 No
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-- 16 nInitialize Reset Out Control-2 No
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-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
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-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
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-- 18-25 Ground Ground - - -
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-- 18-25 Ground Ground - - -
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--
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--
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-- Address MSB LSB
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-- Address MSB LSB
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-- Bit: 7 6 5 4 3 2 1 0
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-- Bit: 7 6 5 4 3 2 1 0
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-- Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
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-- Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
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-- Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
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-- Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
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-- Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
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-- Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
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-- Base+3 (EPP Address port) R/W
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-- Base+3 (EPP Address port) R/W
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-- Base+4 (EPP Data port) R/W
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-- Base+4 (EPP Data port) R/W
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--
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--
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-- ~ indicates a hardware inversion of the bit.
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-- ~ indicates a hardware inversion of the bit.
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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entity spp is
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entity spp is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector(2 downto 0);
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addr : in std_logic_vector(2 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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spp_data : out std_logic_vector(7 downto 0);
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spp_data : out std_logic_vector(7 downto 0);
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spp_stat : in std_logic_vector(7 downto 3);
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spp_stat : in std_logic_vector(7 downto 3);
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spp_ctrl : out std_logic_vector(3 downto 0);
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spp_ctrl : out std_logic_vector(3 downto 0);
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hold : out std_logic;
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hold : out std_logic;
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irq : out std_logic
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irq : out std_logic
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);
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);
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end;
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end;
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architecture rtl of spp is
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architecture rtl of spp is
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|
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signal spp_data_reg : std_logic_vector(7 downto 0);
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signal spp_data_reg : std_logic_vector(7 downto 0);
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signal spp_stat_reg : std_logic_vector(7 downto 3);
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signal spp_stat_reg : std_logic_vector(7 downto 3);
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signal spp_ctrl_reg : std_logic_vector(3 downto 0);
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signal spp_ctrl_reg : std_logic_vector(3 downto 0);
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|
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begin
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begin
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--------------------------------
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--------------------------------
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--
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--
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-- read I/O port
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-- read I/O port
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--
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--
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--------------------------------
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--------------------------------
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spp_read : process( addr,
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spp_read : process( addr,
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spp_data_reg, spp_stat_reg, spp_ctrl_reg,
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spp_data_reg, spp_stat_reg, spp_ctrl_reg,
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spp_stat )
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spp_stat )
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begin
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begin
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spp_stat_reg(6 downto 3) <= spp_stat(6 downto 3);
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spp_stat_reg(6 downto 3) <= spp_stat(6 downto 3);
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spp_stat_reg(7) <= not spp_stat(7);
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spp_stat_reg(7) <= not spp_stat(7);
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case addr is
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case addr is
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when "000" =>
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when "000" =>
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data_out <= spp_data_reg;
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data_out <= spp_data_reg;
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|
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when "001" =>
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when "001" =>
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data_out <= spp_stat_reg & "000";
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data_out <= spp_stat_reg & "000";
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|
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when "010" =>
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when "010" =>
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data_out <= "0000" & spp_ctrl_reg;
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data_out <= "0000" & spp_ctrl_reg;
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when others =>
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when others =>
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data_out <= (others=> '0');
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data_out <= (others=> '0');
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end case;
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end case;
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hold <= '0';
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hold <= '0';
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irq <= '0';
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irq <= '0';
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end process;
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end process;
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|
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---------------------------------
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---------------------------------
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--
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--
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-- Write I/O ports
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-- Write I/O ports
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--
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--
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---------------------------------
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---------------------------------
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|
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spp_write : process( clk, rst, addr, cs, rw, data_in,
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spp_write : process( clk, rst, addr, cs, rw, data_in,
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spp_data_reg, spp_ctrl_reg )
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spp_data_reg, spp_ctrl_reg )
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begin
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begin
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if clk'event and clk = '0' then
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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spp_data_reg <= "00000000";
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spp_data_reg <= "00000000";
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spp_ctrl_reg <= "0000";
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spp_ctrl_reg <= "0000";
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elsif cs = '1' and rw = '0' then
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elsif cs = '1' and rw = '0' then
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case addr is
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case addr is
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when "000" =>
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when "000" =>
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spp_data_reg <= data_in;
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spp_data_reg <= data_in;
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when "010" =>
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when "010" =>
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spp_ctrl_reg <= data_in(3 downto 0);
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spp_ctrl_reg <= data_in(3 downto 0);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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spp_data <= spp_data_reg;
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spp_data <= spp_data_reg;
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spp_ctrl(0) <= not spp_ctrl_reg(0);
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spp_ctrl(0) <= not spp_ctrl_reg(0);
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spp_ctrl(1) <= not spp_ctrl_reg(1);
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spp_ctrl(1) <= not spp_ctrl_reg(1);
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spp_ctrl(2) <= spp_ctrl_reg(2);
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spp_ctrl(2) <= spp_ctrl_reg(2);
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spp_ctrl(3) <= not spp_ctrl_reg(3);
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spp_ctrl(3) <= not spp_ctrl_reg(3);
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end process;
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end process;
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end rtl;
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end rtl;
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