//==============================================================
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//==============================================================
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// Test sequencer
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// Test sequencer
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//==============================================================
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//==============================================================
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`timescale 100 ns/ 100 ns
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`timescale 100 ns/ 100 ns
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module test_sequencer;
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module test_sequencer;
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// ----------------- CLOCKS AND RESET -----------------
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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// Define one full T-clock cycle delay
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`define T #2
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`define T #2
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bit clk = 1;
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bit clk = 1;
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initial repeat (100) #1 clk = ~clk;
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initial repeat (100) #1 clk = ~clk;
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logic nreset = 0;
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logic nreset = 0;
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// ----------------- CONTROL ----------------
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// ----------------- CONTROL ----------------
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logic nextM_sig;
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logic nextM_sig;
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logic setM1_sig;
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logic setM1_sig;
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logic hold_clk_iorq_sig=0;
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logic hold_clk_iorq_sig=0;
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logic hold_clk_wait_sig=0;
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logic hold_clk_wait_sig=0;
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logic hold_clk_busrq_sig=0;
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logic hold_clk_busrq_sig=0;
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wire T6_sig;
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wire T6_sig;
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wire M6_sig;
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wire M5_sig;
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assign nextM_sig = T6_sig; // Restart when reaching T6
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assign nextM_sig = T6_sig; // Restart when reaching T6
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assign setM1_sig = M6_sig; // Restart when reaching M6
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assign setM1_sig = M5_sig & T6_sig; // Restart when reaching M5/T6
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// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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initial begin
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initial begin
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// Init / reset
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// Init / reset
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`T nreset = 1;
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`T nreset = 1;
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repeat (100) @(posedge clk); nreset <= 1;
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repeat (100) @(posedge clk); nreset <= 1;
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// This test does not use assert() -- we just check visually
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// This test does not use assert() -- we just check visually
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`T $display("End of test");
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`T $display("End of test");
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end
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end
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Instantiate sequencer
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// Instantiate sequencer
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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sequencer sequencer_inst
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sequencer sequencer_inst
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(
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(
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.clk(clk) , // input clk
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.clk(clk) , // input clk
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.nextM(nextM_sig) , // input nextM_sig
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.nextM(nextM_sig) , // input nextM_sig
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.setM1(setM1_sig) , // input setM1_sig
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.setM1(setM1_sig) , // input setM1_sig
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.nreset(nreset) , // input nreset
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.nreset(nreset) , // input nreset
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.hold_clk_iorq(hold_clk_iorq_sig) , // input hold_clk_iorq_sig
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.hold_clk_iorq(hold_clk_iorq_sig) , // input hold_clk_iorq_sig
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.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
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.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
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.hold_clk_busrq(hold_clk_busrq_sig),// input hold_clk_busrq_sig
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.hold_clk_busrq(hold_clk_busrq_sig),// input hold_clk_busrq_sig
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.M1(M1_sig) , // output M1_sig
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.M1(M1_sig) , // output M1_sig
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.M2(M2_sig) , // output M2_sig
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.M2(M2_sig) , // output M2_sig
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.M3(M3_sig) , // output M3_sig
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.M3(M3_sig) , // output M3_sig
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.M4(M4_sig) , // output M4_sig
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.M4(M4_sig) , // output M4_sig
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.M5(M5_sig) , // output M5_sig
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.M5(M5_sig) , // output M5_sig
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.M6(M6_sig) , // output M6_sig
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.T1(T1_sig) , // output T1_sig
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.T1(T1_sig) , // output T1_sig
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.T2(T2_sig) , // output T2_sig
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.T2(T2_sig) , // output T2_sig
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.T3(T3_sig) , // output T3_sig
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.T3(T3_sig) , // output T3_sig
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.T4(T4_sig) , // output T4_sig
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.T4(T4_sig) , // output T4_sig
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.T5(T5_sig) , // output T5_sig
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.T5(T5_sig) , // output T5_sig
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.T6(T6_sig) , // output T6_sig
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.T6(T6_sig) , // output T6_sig
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.timings_en(timings_en_sig) // output timings_en_sig
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.timings_en(timings_en_sig) // output timings_en_sig
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);
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);
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endmodule
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endmodule
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