//==============================================================
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//==============================================================
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// Test register file block (without reg. control unit)
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// Test register file block (without reg. control unit)
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//==============================================================
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//==============================================================
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`timescale 100 ns/ 100 ns
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`timescale 100 ns/ 100 ns
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module test_regfile;
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module test_regfile;
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// ----------------- CLOCKS AND RESET -----------------
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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// Define one full T-clock cycle delay
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`define T #2
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`define T #2
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bit clk = 1;
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bit clk = 1;
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initial repeat (10) #1 clk = ~clk;
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initial repeat (10) #1 clk = ~clk;
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// ----------------- BUSES -----------------
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// ----------------- BUSES -----------------
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// We have 4 Bi-directional buses that can also be 3-stated:
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// We have 4 Bi-directional buses that can also be 3-stated:
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// On the address-side, there are high and low 8-bit buses
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// On the address-side, there are high and low 8-bit buses
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reg [7:0] db_lo_as; // Drive it using this bus
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reg [7:0] db_lo_as; // Drive it using this bus
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wire [7:0] db_lo_as_sig; // Read it using this bus
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wire [7:0] db_lo_as_sig; // Read it using this bus
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reg [7:0] db_hi_as; // Drive it using this bus
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reg [7:0] db_hi_as; // Drive it using this bus
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wire [7:0] db_hi_as_sig; // Read it using this bus
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wire [7:0] db_hi_as_sig; // Read it using this bus
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// ----------------- BUSES -----------------
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// ----------------- BUSES -----------------
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// On the data-side, there are high and low 8-bit buses
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// On the data-side, there are high and low 8-bit buses
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reg [7:0] db_lo_ds; // Drive it using this bus
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reg [7:0] db_lo_ds; // Drive it using this bus
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wire [7:0] db_lo_ds_sig; // Read it using this bus
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wire [7:0] db_lo_ds_sig; // Read it using this bus
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reg [7:0] db_hi_ds; // Drive it using this bus
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reg [7:0] db_hi_ds; // Drive it using this bus
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wire [7:0] db_hi_ds_sig; // Read it using this bus
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wire [7:0] db_hi_ds_sig; // Read it using this bus
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// ----------------- CONTROL -----------------
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// ----------------- CONTROL -----------------
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reg ctl_sw_4u_sig; // Bus switch #4 upstream gate
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reg ctl_sw_4u_sig; // Bus switch #4 upstream gate
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reg ctl_sw_4d_sig; // Bus switch #4 downstream gate
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reg reg_sw_4d_lo_sig; // Bus switch #4 downstream gate low byte lane
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reg reg_sw_4d_hi_sig; // Bus switch #4 downstream gate high byte lane
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// ----------------- GP REGS -----------------
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// ----------------- GP REGS -----------------
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reg reg_sel_af_sig; // Select AF register
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reg reg_sel_af_sig; // Select AF register
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reg reg_sel_af2_sig; // ...
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reg reg_sel_af2_sig; // ...
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reg reg_sel_bc_sig;
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reg reg_sel_bc_sig;
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reg reg_sel_bc2_sig;
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reg reg_sel_bc2_sig;
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reg reg_sel_de_sig;
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reg reg_sel_de_sig;
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reg reg_sel_de2_sig;
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reg reg_sel_de2_sig;
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reg reg_sel_hl_sig;
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reg reg_sel_hl_sig;
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reg reg_sel_hl2_sig;
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reg reg_sel_hl2_sig;
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reg reg_sel_ix_sig;
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reg reg_sel_ix_sig;
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reg reg_sel_iy_sig;
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reg reg_sel_iy_sig;
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reg reg_sel_wz_sig;
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reg reg_sel_wz_sig;
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reg reg_sel_sp_sig;
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reg reg_sel_sp_sig;
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reg reg_sel_gp_hi_sig; // Select high byte of a GP register
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reg reg_sel_gp_hi_sig; // Select high byte of a GP register
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reg reg_sel_gp_lo_sig; // Select low byte of a GP register
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reg reg_sel_gp_lo_sig; // Select low byte of a GP register
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reg reg_gp_oe_sig; // Write selected GP register to the data bus
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reg reg_gp_oe_sig; // Write selected GP register to the data bus
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// ----------------- SYSTEM REGS -----------------
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// ----------------- SYSTEM REGS -----------------
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reg reg_sel_pc_sig; // Select PC register
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reg reg_sel_pc_sig; // Select PC register
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reg reg_sel_ir_sig; // Select IR register
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reg reg_sel_ir_sig; // Select IR register
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reg reg_sel_sys_hi_sig; // Select high byte of a system register
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reg reg_sel_sys_hi_sig; // Select high byte of a system register
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reg reg_sel_sys_lo_sig; // Select low byte of a system register
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reg reg_sel_sys_lo_sig; // Select low byte of a system register
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reg reg_sys_oe_sig; // Write selected system register to the data bus
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reg reg_sys_oe_sig; // Write selected system register to the data bus
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// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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`define CHECK(arg) \
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`define CHECK(arg) \
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assert(db_sig===arg);
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assert(db_sig===arg);
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initial begin
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initial begin
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ctl_sw_4d_sig = 0;
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reg_sw_4d_lo_sig = 0;
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reg_sw_4d_hi_sig = 0;
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ctl_sw_4u_sig = 0;
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ctl_sw_4u_sig = 0;
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reg_sel_af_sig = 0; // Select AF register
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reg_sel_af_sig = 0; // Select AF register
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reg_sel_af2_sig = 0; // ...
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reg_sel_af2_sig = 0; // ...
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reg_sel_bc_sig = 0;
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reg_sel_bc_sig = 0;
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reg_sel_bc2_sig = 0;
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reg_sel_bc2_sig = 0;
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reg_sel_de_sig = 0;
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reg_sel_de_sig = 0;
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reg_sel_de2_sig = 0;
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reg_sel_de2_sig = 0;
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reg_sel_hl_sig = 0;
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reg_sel_hl_sig = 0;
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reg_sel_hl2_sig = 0;
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reg_sel_hl2_sig = 0;
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reg_sel_ix_sig = 0;
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reg_sel_ix_sig = 0;
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reg_sel_iy_sig = 0;
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reg_sel_iy_sig = 0;
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reg_sel_wz_sig = 0;
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reg_sel_wz_sig = 0;
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reg_sel_sp_sig = 0;
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reg_sel_sp_sig = 0;
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reg_sel_gp_hi_sig = 0; // Select high byte of a GP register
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reg_sel_gp_hi_sig = 0; // Select high byte of a GP register
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reg_sel_gp_lo_sig = 0; // Select low byte of a GP register
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reg_sel_gp_lo_sig = 0; // Select low byte of a GP register
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reg_gp_oe_sig = 0; // Write selected GP register to the data bus
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reg_gp_oe_sig = 0; // Write selected GP register to the data bus
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reg_sel_pc_sig = 0; // Select PC register
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reg_sel_pc_sig = 0; // Select PC register
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reg_sel_ir_sig = 0; // Select IR register
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reg_sel_ir_sig = 0; // Select IR register
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reg_sel_sys_hi_sig = 0; // Select high byte of a system register
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reg_sel_sys_hi_sig = 0; // Select high byte of a system register
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reg_sel_sys_lo_sig = 0; // Select low byte of a system register
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reg_sel_sys_lo_sig = 0; // Select low byte of a system register
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reg_sys_oe_sig = 0; // Write selected system register to the data bus
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reg_sys_oe_sig = 0; // Write selected system register to the data bus
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// Test bidirectional data buses and leave them at Z
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// Test bidirectional data buses and leave them at Z
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`T db_lo_as = 8'hAA;
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`T db_lo_as = 8'hAA;
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db_hi_as = 8'h55;
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db_hi_as = 8'h55;
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db_lo_ds = 8'hCA;
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db_lo_ds = 8'hCA;
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db_hi_ds = 8'hFE;
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db_hi_ds = 8'hFE;
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`T db_lo_as = 'z;
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`T db_lo_as = 'z;
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db_hi_as = 'z;
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db_hi_as = 'z;
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db_lo_ds = 'z;
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db_lo_ds = 'z;
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db_hi_ds = 'z;
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db_hi_ds = 'z;
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// Store a value in a GP register and read it back
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// Store a value in a GP register and read it back
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`T db_lo_ds = 8'h12;
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`T db_lo_ds = 8'h12;
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db_hi_ds = 8'h34;
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db_hi_ds = 8'h34;
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reg_sel_gp_hi_sig = 1;
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reg_sel_gp_hi_sig = 1;
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reg_sel_gp_lo_sig = 1;
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reg_sel_gp_lo_sig = 1;
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reg_sel_af_sig = 1;
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reg_sel_af_sig = 1;
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`T db_lo_ds = 'z;
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`T db_lo_ds = 'z;
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db_hi_ds = 'z;
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db_hi_ds = 'z;
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reg_sel_af_sig = 0;
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reg_sel_af_sig = 0;
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`T
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`T
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`T reg_sel_gp_hi_sig = 1;
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`T reg_sel_gp_hi_sig = 1;
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reg_sel_gp_lo_sig = 1;
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reg_sel_gp_lo_sig = 1;
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reg_sel_af_sig = 1;
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reg_sel_af_sig = 1;
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reg_gp_oe_sig = 1;
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reg_gp_oe_sig = 1;
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`T
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`T
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`T $display("End of test");
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`T $display("End of test");
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end
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end
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// Drive 3-state bidirectional buses with these statements
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// Drive 3-state bidirectional buses with these statements
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assign db_lo_as_sig = db_lo_as;
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assign db_lo_as_sig = db_lo_as;
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assign db_hi_as_sig = db_hi_as;
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assign db_hi_as_sig = db_hi_as;
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assign db_lo_ds_sig = db_lo_ds;
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assign db_lo_ds_sig = db_lo_ds;
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assign db_hi_ds_sig = db_hi_ds;
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assign db_hi_ds_sig = db_hi_ds;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Instantiate register file block
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// Instantiate register file block
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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reg_file reg_file_inst
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reg_file reg_file_inst
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(
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(
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.reg_sel_sys_lo(reg_sel_sys_lo_sig) , // input reg_sel_sys_lo_sig
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.reg_sel_sys_lo(reg_sel_sys_lo_sig) , // input reg_sel_sys_lo_sig
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.reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig
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.reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig
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.reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig
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.reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig
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.reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig
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.reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig
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.reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig
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.reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig
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.reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig
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.reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig
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.ctl_sw_4d(ctl_sw_4d_sig) , // input ctl_sw_4d_sig
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.reg_sw_4d_lo(reg_sw_4d_lo_sig) , // input reg_sw_4d_lo_sig
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.reg_sw_4d_hi(reg_sw_4d_hi_sig) , // input reg_sw_4d_hi_sig
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.ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig
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.ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig
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.reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig
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.reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig
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.reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig
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.reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig
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.reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig
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.reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig
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.reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig
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.reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig
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.reg_sel_hl2(reg_sel_hl2_sig) , // input reg_sel_hl2_sig
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.reg_sel_hl2(reg_sel_hl2_sig) , // input reg_sel_hl2_sig
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.reg_sel_hl(reg_sel_hl_sig) , // input reg_sel_hl_sig
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.reg_sel_hl(reg_sel_hl_sig) , // input reg_sel_hl_sig
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.reg_sel_de2(reg_sel_de2_sig) , // input reg_sel_de2_sig
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.reg_sel_de2(reg_sel_de2_sig) , // input reg_sel_de2_sig
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.reg_sel_de(reg_sel_de_sig) , // input reg_sel_de_sig
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.reg_sel_de(reg_sel_de_sig) , // input reg_sel_de_sig
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.reg_sel_bc2(reg_sel_bc2_sig) , // input reg_sel_bc2_sig
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.reg_sel_bc2(reg_sel_bc2_sig) , // input reg_sel_bc2_sig
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.reg_sel_bc(reg_sel_bc_sig) , // input reg_sel_bc_sig
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.reg_sel_bc(reg_sel_bc_sig) , // input reg_sel_bc_sig
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.reg_sel_af2(reg_sel_af2_sig) , // input reg_sel_af2_sig
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.reg_sel_af2(reg_sel_af2_sig) , // input reg_sel_af2_sig
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.reg_sel_af(reg_sel_af_sig) , // input reg_sel_af_sig
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.reg_sel_af(reg_sel_af_sig) , // input reg_sel_af_sig
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.reg_gp_we(reg_gp_we_sig) , // input reg_gp_we_sig
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.reg_gp_we(reg_gp_we_sig) , // input reg_gp_we_sig
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.reg_sys_we_lo(reg_sys_we_lo_sig) , // input reg_sys_we_lo_sig
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.reg_sys_we_lo(reg_sys_we_lo_sig) , // input reg_sys_we_lo_sig
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.reg_sys_we_hi(reg_sys_we_hi_sig) , // input reg_sys_we_hi_sig
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.reg_sys_we_hi(reg_sys_we_hi_sig) , // input reg_sys_we_hi_sig
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.ctl_reg_in_hi(ctl_reg_in_hi_sig) , // input ctl_reg_in_hi_sig
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.ctl_reg_in_hi(ctl_reg_in_hi_sig) , // input ctl_reg_in_hi_sig
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.ctl_reg_in_lo(ctl_reg_in_lo_sig) , // input ctl_reg_in_lo_sig
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.ctl_reg_in_lo(ctl_reg_in_lo_sig) , // input ctl_reg_in_lo_sig
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.ctl_reg_out_lo(ctl_reg_out_lo_sig) , // input ctl_reg_out_lo_sig
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.ctl_reg_out_lo(ctl_reg_out_lo_sig) , // input ctl_reg_out_lo_sig
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.ctl_reg_out_hi(ctl_reg_out_hi_sig) , // input ctl_reg_out_hi_sig
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.ctl_reg_out_hi(ctl_reg_out_hi_sig) , // input ctl_reg_out_hi_sig
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.clk(clk) , // input clk_sig
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.clk(clk) , // input clk_sig
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.db_lo_ds(db_lo_ds_sig) , // inout [7:0] db_lo_ds_sig
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.db_lo_ds(db_lo_ds_sig) , // inout [7:0] db_lo_ds_sig
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.db_hi_ds(db_hi_ds_sig) , // inout [7:0] db_hi_ds_sig
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.db_hi_ds(db_hi_ds_sig) , // inout [7:0] db_hi_ds_sig
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.db_lo_as(db_lo_as_sig) , // inout [7:0] db_lo_as_sig
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.db_lo_as(db_lo_as_sig) , // inout [7:0] db_lo_as_sig
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.db_hi_as(db_hi_as_sig) // inout [7:0] db_hi_as_sig
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.db_hi_as(db_hi_as_sig) // inout [7:0] db_hi_as_sig
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);
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);
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endmodule
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endmodule
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