; Copyright 1991-2009 Mentor Graphics Corporation
|
; Copyright 1991-2009 Mentor Graphics Corporation
|
;
|
;
|
; All Rights Reserved.
|
; All Rights Reserved.
|
;
|
;
|
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
;
|
;
|
|
|
[Library]
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[Library]
|
std = $MODEL_TECH/../std
|
std = $MODEL_TECH/../std
|
ieee = $MODEL_TECH/../ieee
|
ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
|
verilog = $MODEL_TECH/../verilog
|
vital2000 = $MODEL_TECH/../vital2000
|
vital2000 = $MODEL_TECH/../vital2000
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
synopsys = $MODEL_TECH/../synopsys
|
synopsys = $MODEL_TECH/../synopsys
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
sv_std = $MODEL_TECH/../sv_std
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sv_std = $MODEL_TECH/../sv_std
|
|
|
; Altera Primitive libraries
|
; Altera Primitive libraries
|
;
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;
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; VHDL Section
|
; VHDL Section
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;
|
;
|
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
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altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
altera = $MODEL_TECH/../altera/vhdl/altera
|
altera = $MODEL_TECH/../altera/vhdl/altera
|
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
lpm = $MODEL_TECH/../altera/vhdl/220model
|
lpm = $MODEL_TECH/../altera/vhdl/220model
|
220model = $MODEL_TECH/../altera/vhdl/220model
|
220model = $MODEL_TECH/../altera/vhdl/220model
|
max = $MODEL_TECH/../altera/vhdl/max
|
max = $MODEL_TECH/../altera/vhdl/max
|
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
;
|
;
|
; Verilog Section
|
; Verilog Section
|
;
|
;
|
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
max_ver = $MODEL_TECH/../altera/verilog/max
|
max_ver = $MODEL_TECH/../altera/verilog/max
|
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
|
|
[vcom]
|
[vcom]
|
; VHDL93 variable selects language version as the default.
|
; VHDL93 variable selects language version as the default.
|
; Default is VHDL-2002.
|
; Default is VHDL-2002.
|
; Value of 0 or 1987 for VHDL-1987.
|
; Value of 0 or 1987 for VHDL-1987.
|
; Value of 1 or 1993 for VHDL-1993.
|
; Value of 1 or 1993 for VHDL-1993.
|
; Default or value of 2 or 2002 for VHDL-2002.
|
; Default or value of 2 or 2002 for VHDL-2002.
|
; Default or value of 3 or 2008 for VHDL-2008.
|
; Default or value of 3 or 2008 for VHDL-2008.
|
VHDL93 = 2002
|
VHDL93 = 2002
|
|
|
; Show source line containing error. Default is off.
|
; Show source line containing error. Default is off.
|
; Show_source = 1
|
; Show_source = 1
|
|
|
; Turn off unbound-component warnings. Default is on.
|
; Turn off unbound-component warnings. Default is on.
|
; Show_Warning1 = 0
|
; Show_Warning1 = 0
|
|
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Show_Warning2 = 0
|
; Show_Warning2 = 0
|
|
|
; Turn off null-range warnings. Default is on.
|
; Turn off null-range warnings. Default is on.
|
; Show_Warning3 = 0
|
; Show_Warning3 = 0
|
|
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Show_Warning4 = 0
|
; Show_Warning4 = 0
|
|
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Show_Warning5 = 0
|
; Show_Warning5 = 0
|
|
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Optimize_1164 = 0
|
; Optimize_1164 = 0
|
|
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; "explicit" function declaration (not the one automatically created by
|
; "explicit" function declaration (not the one automatically created by
|
; the compiler for each type declaration). Default is off.
|
; the compiler for each type declaration). Default is off.
|
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
; will match the behavior of synthesis tools.
|
; will match the behavior of synthesis tools.
|
Explicit = 1
|
Explicit = 1
|
|
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; NoVital = 1
|
; NoVital = 1
|
|
|
; Turn off VITAL compliance checking. Default is checking on.
|
; Turn off VITAL compliance checking. Default is checking on.
|
; NoVitalCheck = 1
|
; NoVitalCheck = 1
|
|
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; IgnoreVitalErrors = 1
|
; IgnoreVitalErrors = 1
|
|
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Show_VitalChecksWarnings = 0
|
; Show_VitalChecksWarnings = 0
|
|
|
; Keep silent about case statement static warnings.
|
; Keep silent about case statement static warnings.
|
; Default is to give a warning.
|
; Default is to give a warning.
|
; NoCaseStaticError = 1
|
; NoCaseStaticError = 1
|
|
|
; Keep silent about warnings caused by aggregates that are not locally static.
|
; Keep silent about warnings caused by aggregates that are not locally static.
|
; Default is to give a warning.
|
; Default is to give a warning.
|
; NoOthersStaticError = 1
|
; NoOthersStaticError = 1
|
|
|
; Turn off inclusion of debugging info within design units.
|
; Turn off inclusion of debugging info within design units.
|
; Default is to include debugging info.
|
; Default is to include debugging info.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "Loading..." messages. Default is messages on.
|
; Turn off "Loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; -- signals used (read) by a process must be in the sensitivity list
|
; -- signals used (read) by a process must be in the sensitivity list
|
; CheckSynthesis = 1
|
; CheckSynthesis = 1
|
|
|
; Activate optimizations on expressions that do not involve signals,
|
; Activate optimizations on expressions that do not involve signals,
|
; waits, or function/procedure/task invocations. Default is off.
|
; waits, or function/procedure/task invocations. Default is off.
|
; ScalarOpts = 1
|
; ScalarOpts = 1
|
|
|
; Require the user to specify a configuration for all bindings,
|
; Require the user to specify a configuration for all bindings,
|
; and do not generate a compile time default binding for the
|
; and do not generate a compile time default binding for the
|
; component. This will result in an elaboration error of
|
; component. This will result in an elaboration error of
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; issue of a false dependency upon the unused default binding.
|
; issue of a false dependency upon the unused default binding.
|
; RequireConfigForAllDefaultBinding = 1
|
; RequireConfigForAllDefaultBinding = 1
|
|
|
; Inhibit range checking on subscripts of arrays. Range checking on
|
; Inhibit range checking on subscripts of arrays. Range checking on
|
; scalars defined with subtypes is inhibited by default.
|
; scalars defined with subtypes is inhibited by default.
|
; NoIndexCheck = 1
|
; NoIndexCheck = 1
|
|
|
; Inhibit range checks on all (implicit and explicit) assignments to
|
; Inhibit range checks on all (implicit and explicit) assignments to
|
; scalar objects defined with subtypes.
|
; scalar objects defined with subtypes.
|
; NoRangeCheck = 1
|
; NoRangeCheck = 1
|
|
|
[vlog]
|
[vlog]
|
|
|
; Turn off inclusion of debugging info within design units.
|
; Turn off inclusion of debugging info within design units.
|
; Default is to include debugging info.
|
; Default is to include debugging info.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "loading..." messages. Default is messages on.
|
; Turn off "loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Default is off.
|
; Default is off.
|
; Hazard = 1
|
; Hazard = 1
|
|
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; insensitivity for module names. Default is no conversion.
|
; insensitivity for module names. Default is no conversion.
|
; UpCase = 1
|
; UpCase = 1
|
|
|
; Turn on incremental compilation of modules. Default is off.
|
; Turn on incremental compilation of modules. Default is off.
|
; Incremental = 1
|
; Incremental = 1
|
|
|
; Turns on lint-style checking.
|
; Turns on lint-style checking.
|
; Show_Lint = 1
|
; Show_Lint = 1
|
|
|
[vsim]
|
[vsim]
|
; Simulator resolution
|
; Simulator resolution
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
Resolution = ps
|
Resolution = ps
|
|
|
; User time unit for run commands
|
; User time unit for run commands
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; then UserTimeUnit defaults to ps.
|
; then UserTimeUnit defaults to ps.
|
; Should generally be set to default.
|
; Should generally be set to default.
|
UserTimeUnit = default
|
UserTimeUnit = default
|
|
|
; Default run length
|
; Default run length
|
RunLength = 1 us
|
RunLength = 1 us
|
|
|
; Maximum iterations that can be run without advancing simulation time
|
; Maximum iterations that can be run without advancing simulation time
|
IterationLimit = 5000
|
IterationLimit = 5000
|
|
|
; Directive to license manager:
|
; Directive to license manager:
|
; vhdl Immediately reserve a VHDL license
|
; vhdl Immediately reserve a VHDL license
|
; vlog Immediately reserve a Verilog license
|
; vlog Immediately reserve a Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomti Do not look for Model Technology Licenses
|
; nomti Do not look for Model Technology Licenses
|
; noqueue Do not wait in the license queue when a license isn't available
|
; noqueue Do not wait in the license queue when a license isn't available
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
; of queuing for viewer license
|
; of queuing for viewer license
|
; License = plus
|
; License = plus
|
|
|
; Stop the simulator after a VHDL/Verilog assertion message
|
; Stop the simulator after a VHDL/Verilog assertion message
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
BreakOnAssertion = 3
|
BreakOnAssertion = 3
|
|
|
; Assertion Message Format
|
; Assertion Message Format
|
; %S - Severity Level
|
; %S - Severity Level
|
; %R - Report Message
|
; %R - Report Message
|
; %T - Time of assertion
|
; %T - Time of assertion
|
; %D - Delta
|
; %D - Delta
|
; %I - Instance or Region pathname (if available)
|
; %I - Instance or Region pathname (if available)
|
; %% - print '%' character
|
; %% - print '%' character
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
|
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
; AssertFile = assert.log
|
; AssertFile = assert.log
|
|
|
; Default radix for all windows and commands...
|
; Default radix for all windows and commands...
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
DefaultRadix = hexadecimal
|
DefaultRadix = hexadecimal
|
|
|
; VSIM Startup command
|
; VSIM Startup command
|
; Startup = do startup.do
|
; Startup = do startup.do
|
|
|
; File for saving command transcript
|
; File for saving command transcript
|
TranscriptFile = transcript
|
TranscriptFile = transcript
|
|
|
; File for saving command history
|
; File for saving command history
|
; CommandHistory = cmdhist.log
|
; CommandHistory = cmdhist.log
|
|
|
; Specify whether paths in simulator commands should be described
|
; Specify whether paths in simulator commands should be described
|
; in VHDL or Verilog format.
|
; in VHDL or Verilog format.
|
; For VHDL, PathSeparator = /
|
; For VHDL, PathSeparator = /
|
; For Verilog, PathSeparator = .
|
; For Verilog, PathSeparator = .
|
; Must not be the same character as DatasetSeparator.
|
; Must not be the same character as DatasetSeparator.
|
PathSeparator = /
|
PathSeparator = /
|
|
|
; Specify the dataset separator for fully rooted contexts.
|
; Specify the dataset separator for fully rooted contexts.
|
; The default is ':'. For example, sim:/top
|
; The default is ':'. For example, sim:/top
|
; Must not be the same character as PathSeparator.
|
; Must not be the same character as PathSeparator.
|
DatasetSeparator = :
|
DatasetSeparator = :
|
|
|
; Disable VHDL assertion messages
|
; Disable VHDL assertion messages
|
; IgnoreNote = 1
|
; IgnoreNote = 1
|
; IgnoreWarning = 1
|
; IgnoreWarning = 1
|
; IgnoreError = 1
|
; IgnoreError = 1
|
; IgnoreFailure = 1
|
; IgnoreFailure = 1
|
|
|
; Default force kind. May be freeze, drive, deposit, or default
|
; Default force kind. May be freeze, drive, deposit, or default
|
; or in other terms, fixed, wired, or charged.
|
; or in other terms, fixed, wired, or charged.
|
; A value of "default" will use the signal kind to determine the
|
; A value of "default" will use the signal kind to determine the
|
; force kind, drive for resolved signals, freeze for unresolved signals
|
; force kind, drive for resolved signals, freeze for unresolved signals
|
; DefaultForceKind = freeze
|
; DefaultForceKind = freeze
|
|
|
; If zero, open files when elaborated; otherwise, open files on
|
; If zero, open files when elaborated; otherwise, open files on
|
; first read or write. Default is 0.
|
; first read or write. Default is 0.
|
; DelayFileOpen = 1
|
; DelayFileOpen = 1
|
|
|
; Control VHDL files opened for write.
|
; Control VHDL files opened for write.
|
; 0 = Buffered, 1 = Unbuffered
|
; 0 = Buffered, 1 = Unbuffered
|
UnbufferedOutput = 0
|
UnbufferedOutput = 0
|
|
|
; Control the number of VHDL files open concurrently.
|
; Control the number of VHDL files open concurrently.
|
; This number should always be less than the current ulimit
|
; This number should always be less than the current ulimit
|
; setting for max file descriptors.
|
; setting for max file descriptors.
|
; 0 = unlimited
|
; 0 = unlimited
|
ConcurrentFileLimit = 40
|
ConcurrentFileLimit = 40
|
|
|
; Control the number of hierarchical regions displayed as
|
; Control the number of hierarchical regions displayed as
|
; part of a signal name shown in the Wave window.
|
; part of a signal name shown in the Wave window.
|
; A value of zero tells VSIM to display the full name.
|
; A value of zero tells VSIM to display the full name.
|
; The default is 0.
|
; The default is 0.
|
; WaveSignalNameWidth = 0
|
; WaveSignalNameWidth = 0
|
|
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; and std_logic_signed packages.
|
; and std_logic_signed packages.
|
; StdArithNoWarnings = 1
|
; StdArithNoWarnings = 1
|
|
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
; NumericStdNoWarnings = 1
|
; NumericStdNoWarnings = 1
|
|
|
; Control the format of the (VHDL) FOR generate statement label
|
; Control the format of the (VHDL) FOR generate statement label
|
; for each iteration. Do not quote it.
|
; for each iteration. Do not quote it.
|
; The format string here must contain the conversion codes %s and %d,
|
; The format string here must contain the conversion codes %s and %d,
|
; in that order, and no other conversion codes. The %s represents
|
; in that order, and no other conversion codes. The %s represents
|
; the generate_label; the %d represents the generate parameter value
|
; the generate_label; the %d represents the generate parameter value
|
; at a particular generate iteration (this is the position number if
|
; at a particular generate iteration (this is the position number if
|
; the generate parameter is of an enumeration type). Embedded whitespace
|
; the generate parameter is of an enumeration type). Embedded whitespace
|
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
; Application of the format must result in a unique scope name over all
|
; Application of the format must result in a unique scope name over all
|
; such names in the design so that name lookup can function properly.
|
; such names in the design so that name lookup can function properly.
|
; GenerateFormat = %s__%d
|
; GenerateFormat = %s__%d
|
|
|
; Specify whether checkpoint files should be compressed.
|
; Specify whether checkpoint files should be compressed.
|
; The default is 1 (compressed).
|
; The default is 1 (compressed).
|
; CheckpointCompressMode = 0
|
; CheckpointCompressMode = 0
|
|
|
; List of dynamically loaded objects for Verilog PLI applications
|
; List of dynamically loaded objects for Verilog PLI applications
|
; Veriuser = veriuser.sl
|
; Veriuser = veriuser.sl
|
|
|
; Specify default options for the restart command. Options can be one
|
; Specify default options for the restart command. Options can be one
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
; DefaultRestartOptions = -force
|
; DefaultRestartOptions = -force
|
|
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
; (> 500 megabyte memory footprint). Default is disabled.
|
; (> 500 megabyte memory footprint). Default is disabled.
|
; Specify number of megabytes to lock.
|
; Specify number of megabytes to lock.
|
; LockedMemory = 1000
|
; LockedMemory = 1000
|
|
|
; Turn on (1) or off (0) WLF file compression.
|
; Turn on (1) or off (0) WLF file compression.
|
; The default is 1 (compress WLF file).
|
; The default is 1 (compress WLF file).
|
; WLFCompress = 0
|
; WLFCompress = 0
|
|
|
; Specify whether to save all design hierarchy (1) in the WLF file
|
; Specify whether to save all design hierarchy (1) in the WLF file
|
; or only regions containing logged signals (0).
|
; or only regions containing logged signals (0).
|
; The default is 0 (save only regions with logged signals).
|
; The default is 0 (save only regions with logged signals).
|
; WLFSaveAllRegions = 1
|
; WLFSaveAllRegions = 1
|
|
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
; to the specified amount of simulation time. When the limit is exceeded
|
; to the specified amount of simulation time. When the limit is exceeded
|
; the earliest times get truncated from the file.
|
; the earliest times get truncated from the file.
|
; If both time and size limits are specified the most restrictive is used.
|
; If both time and size limits are specified the most restrictive is used.
|
; UserTimeUnits are used if time units are not specified.
|
; UserTimeUnits are used if time units are not specified.
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
; WLFTimeLimit = 0
|
; WLFTimeLimit = 0
|
|
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
; to the specified number of megabytes. If both time and size limits
|
; to the specified number of megabytes. If both time and size limits
|
; are specified then the most restrictive is used.
|
; are specified then the most restrictive is used.
|
; The default is 0 (no limit).
|
; The default is 0 (no limit).
|
; WLFSizeLimit = 1000
|
; WLFSizeLimit = 1000
|
|
|
; Specify whether or not a WLF file should be deleted when the
|
; Specify whether or not a WLF file should be deleted when the
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
; The default is 0 (do not delete WLF file when simulation ends).
|
; The default is 0 (do not delete WLF file when simulation ends).
|
; WLFDeleteOnQuit = 1
|
; WLFDeleteOnQuit = 1
|
|
|
; Automatic SDF compilation
|
; Automatic SDF compilation
|
; Disables automatic compilation of SDF files in flows that support it.
|
; Disables automatic compilation of SDF files in flows that support it.
|
; Default is on, uncomment to turn off.
|
; Default is on, uncomment to turn off.
|
; NoAutoSDFCompile = 1
|
; NoAutoSDFCompile = 1
|
|
|
[lmc]
|
[lmc]
|
|
|
[msg_system]
|
[msg_system]
|
; Change a message severity or suppress a message.
|
; Change a message severity or suppress a message.
|
; The format is: = [,...]
|
; The format is: = [,...]
|
; Examples:
|
; Examples:
|
; note = 3009
|
; note = 3009
|
; warning = 3033
|
; warning = 3033
|
; error = 3010,3016
|
; error = 3010,3016
|
; fatal = 3016,3033
|
; fatal = 3016,3033
|
; suppress = 3009,3016,3043
|
; suppress = 3009,3016,3043
|
; The command verror can be used to get the complete
|
; The command verror can be used to get the complete
|
; description of a message.
|
; description of a message.
|
|
|
; Control transcripting of elaboration/runtime messages.
|
; Control transcripting of elaboration/runtime messages.
|
; The default is to have messages appear in the transcript and
|
; The default is to have messages appear in the transcript and
|
; recorded in the wlf file (messages that are recorded in the
|
; recorded in the wlf file (messages that are recorded in the
|
; wlf file can be viewed in the MsgViewer). The other settings
|
; wlf file can be viewed in the MsgViewer). The other settings
|
; are to send messages only to the transcript or only to the
|
; are to send messages only to the transcript or only to the
|
; wlf file. The valid values are
|
; wlf file. The valid values are
|
; both {default}
|
; both {default}
|
; tran {transcript only}
|
; tran {transcript only}
|
; wlf {wlf file only}
|
; wlf {wlf file only}
|
; msgmode = both
|
; msgmode = both
|
[Project]
|
[Project]
|
; Warning -- Do not edit the project properties directly.
|
; Warning -- Do not edit the project properties directly.
|
; Property names are dynamic in nature and property
|
; Property names are dynamic in nature and property
|
; values have special syntax. Changing property data directly
|
; values have special syntax. Changing property data directly
|
; can result in a corrupt MPF file. All project properties
|
; can result in a corrupt MPF file. All project properties
|
; can be modified through project window dialogs.
|
; can be modified through project window dialogs.
|
Project_Version = 6
|
Project_Version = 6
|
Project_DefaultLib = work
|
Project_DefaultLib = work
|
Project_SortMethod = unused
|
Project_SortMethod = unused
|
Project_Files_Count = 45
|
Project_Files_Count = 45
|
Project_File_0 = $ROOT/cpu/alu/alu.v
|
Project_File_0 = $ROOT/cpu/alu/alu.v
|
Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
|
Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v
|
Project_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_2 = $ROOT/cpu/alu/alu_control.v
|
Project_File_2 = $ROOT/cpu/alu/alu_control.v
|
Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_3 = $ROOT/cpu/alu/alu_core.v
|
Project_File_3 = $ROOT/cpu/alu/alu_core.v
|
Project_File_P_3 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_3 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_4 = $ROOT/cpu/alu/alu_flags.v
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Project_File_4 = $ROOT/cpu/alu/alu_flags.v
|
Project_File_P_4 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_4 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_5 = $ROOT/cpu/alu/alu_mux_2.v
|
Project_File_5 = $ROOT/cpu/alu/alu_mux_2.v
|
Project_File_P_5 = compile_order 40 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_5 = compile_order 40 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_6 = $ROOT/cpu/alu/alu_mux_2z.v
|
Project_File_6 = $ROOT/cpu/alu/alu_mux_2z.v
|
Project_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_7 = $ROOT/cpu/alu/alu_mux_3z.v
|
Project_File_7 = $ROOT/cpu/alu/alu_mux_3z.v
|
Project_File_P_7 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_7 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_8 = $ROOT/cpu/alu/alu_mux_4.v
|
Project_File_8 = $ROOT/cpu/alu/alu_mux_4.v
|
Project_File_P_8 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_8 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_9 = $ROOT/cpu/alu/alu_mux_8.v
|
Project_File_9 = $ROOT/cpu/alu/alu_mux_8.v
|
Project_File_P_9 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_9 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_10 = $ROOT/cpu/alu/alu_prep_daa.v
|
Project_File_10 = $ROOT/cpu/alu/alu_prep_daa.v
|
Project_File_P_10 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_10 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_11 = $ROOT/cpu/alu/alu_select.v
|
Project_File_11 = $ROOT/cpu/alu/alu_select.v
|
Project_File_P_11 = compile_order 26 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_11 = compile_order 26 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_12 = $ROOT/cpu/alu/alu_shifter_core.v
|
Project_File_12 = $ROOT/cpu/alu/alu_shifter_core.v
|
Project_File_P_12 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_12 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_13 = $ROOT/cpu/alu/alu_slice.v
|
Project_File_13 = $ROOT/cpu/alu/alu_slice.v
|
Project_File_P_13 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_13 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_14 = $ROOT/cpu/bus/address_latch.v
|
Project_File_14 = $ROOT/cpu/bus/address_latch.v
|
Project_File_P_14 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_14 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_15 = $ROOT/cpu/bus/address_mux.v
|
Project_File_15 = $ROOT/cpu/bus/address_mux.v
|
Project_File_P_15 = compile_order 39 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_15 = compile_order 39 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_16 = $ROOT/cpu/bus/address_pins.v
|
Project_File_16 = $ROOT/cpu/bus/address_pins.v
|
Project_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_17 = $ROOT/cpu/bus/bus_control.v
|
Project_File_17 = $ROOT/cpu/bus/bus_control.v
|
Project_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_18 = $ROOT/cpu/bus/bus_switch.sv
|
Project_File_18 = $ROOT/cpu/bus/bus_switch.v
|
Project_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_19 = $ROOT/cpu/bus/control_pins_n.v
|
Project_File_19 = $ROOT/cpu/bus/control_pins_n.v
|
Project_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_20 = $ROOT/cpu/bus/data_pins.v
|
Project_File_20 = $ROOT/cpu/bus/data_pins.v
|
Project_File_P_20 = compile_order 14 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_20 = compile_order 14 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_21 = $ROOT/cpu/bus/data_switch.v
|
Project_File_21 = $ROOT/cpu/bus/data_switch.v
|
Project_File_P_21 = compile_order 15 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_21 = compile_order 15 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_22 = $ROOT/cpu/bus/data_switch_mask.v
|
Project_File_22 = $ROOT/cpu/bus/data_switch_mask.v
|
Project_File_P_22 = compile_order 34 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_22 = compile_order 34 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_23 = $ROOT/cpu/bus/inc_dec.v
|
Project_File_23 = $ROOT/cpu/bus/inc_dec.v
|
Project_File_P_23 = compile_order 16 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_23 = compile_order 16 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_24 = $ROOT/cpu/bus/inc_dec_2bit.v
|
Project_File_24 = $ROOT/cpu/bus/inc_dec_2bit.v
|
Project_File_P_24 = compile_order 17 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_24 = compile_order 17 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_25 = $ROOT/cpu/control/clk_delay.v
|
Project_File_25 = $ROOT/cpu/control/clk_delay.v
|
Project_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_26 = $ROOT/cpu/control/decode_state.v
|
Project_File_26 = $ROOT/cpu/control/decode_state.v
|
Project_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_27 = $ROOT/cpu/control/execute.sv
|
Project_File_27 = $ROOT/cpu/control/execute.v
|
Project_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1
|
Project_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1
|
Project_File_28 = $ROOT/cpu/control/interrupts.v
|
Project_File_28 = $ROOT/cpu/control/interrupts.v
|
Project_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_29 = $ROOT/cpu/control/ir.v
|
Project_File_29 = $ROOT/cpu/control/ir.v
|
Project_File_P_29 = compile_order 19 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_29 = compile_order 19 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_30 = $ROOT/cpu/control/memory_ifc.v
|
Project_File_30 = $ROOT/cpu/control/memory_ifc.v
|
Project_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_31 = $ROOT/cpu/control/pin_control.v
|
Project_File_31 = $ROOT/cpu/control/pin_control.v
|
Project_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_32 = $ROOT/cpu/control/pla_decode.sv
|
Project_File_32 = $ROOT/cpu/control/pla_decode.v
|
Project_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_33 = $ROOT/cpu/control/resets.v
|
Project_File_33 = $ROOT/cpu/control/resets.v
|
Project_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_34 = $ROOT/cpu/control/sequencer.v
|
Project_File_34 = $ROOT/cpu/control/sequencer.v
|
Project_File_P_34 = compile_order 21 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_34 = compile_order 21 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_35 = $ROOT/cpu/registers/reg_control.v
|
Project_File_35 = $ROOT/cpu/registers/reg_control.v
|
Project_File_P_35 = compile_order 22 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_35 = compile_order 22 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_36 = $ROOT/cpu/registers/reg_file.v
|
Project_File_36 = $ROOT/cpu/registers/reg_file.v
|
Project_File_P_36 = compile_order 23 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_36 = compile_order 23 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_37 = $ROOT/cpu/registers/reg_latch.v
|
Project_File_37 = $ROOT/cpu/registers/reg_latch.v
|
Project_File_P_37 = compile_order 24 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_37 = compile_order 24 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_38 = $ROOT/cpu/toplevel/tb_io.sv
|
Project_File_38 = $ROOT/cpu/toplevel/tb_io.sv
|
Project_File_P_38 = compile_order 35 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_38 = compile_order 35 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_39 = $ROOT/cpu/toplevel/tb_iorq.sv
|
Project_File_39 = $ROOT/cpu/toplevel/tb_iorq.sv
|
Project_File_P_39 = compile_order 36 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_39 = compile_order 36 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_40 = $ROOT/cpu/toplevel/tb_ram.sv
|
Project_File_40 = $ROOT/cpu/toplevel/tb_ram.sv
|
Project_File_P_40 = compile_order 31 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_40 = compile_order 31 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_41 = $ROOT/cpu/toplevel/test_fuse.sv
|
Project_File_41 = $ROOT/cpu/toplevel/test_fuse.sv
|
Project_File_P_41 = compile_order 33 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_P_41 = compile_order 33 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
|
Project_File_42 = $ROOT/cpu/toplevel/test_top.sv
|
Project_File_42 = $ROOT/cpu/toplevel/test_top.sv
|
Project_File_P_42 = compile_order 25 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_42 = compile_order 25 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_43 = $ROOT/cpu/toplevel/z80.svh
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Project_File_43 = $ROOT/cpu/toplevel/z80.svh
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Project_File_P_43 = compile_order -1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 1 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_43 = compile_order -1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 1 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_44 = $ROOT/cpu/toplevel/z80_top_ifc_n.sv
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Project_File_44 = $ROOT/cpu/toplevel/z80_top_ifc_n.sv
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Project_File_P_44 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../ vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_File_P_44 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../ vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
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Project_Sim_Count = 2
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Project_Sim_Count = 2
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Project_Sim_0 = test_top
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Project_Sim_0 = test_top
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Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_top -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
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Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_top -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
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Project_Sim_1 = test_fuse
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Project_Sim_1 = test_fuse
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Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_fuse -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
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Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_fuse -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
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Project_Folder_Count = 5
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Project_Folder_Count = 5
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Project_Folder_0 = registers
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Project_Folder_0 = registers
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Project_Folder_P_0 = folder {Top Level}
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Project_Folder_P_0 = folder {Top Level}
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Project_Folder_1 = control
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Project_Folder_1 = control
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Project_Folder_P_1 = folder {Top Level}
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Project_Folder_P_1 = folder {Top Level}
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Project_Folder_2 = alu
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Project_Folder_2 = alu
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Project_Folder_P_2 = folder {Top Level}
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Project_Folder_P_2 = folder {Top Level}
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Project_Folder_3 = bus
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Project_Folder_3 = bus
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Project_Folder_P_3 = folder {Top Level}
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Project_Folder_P_3 = folder {Top Level}
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Project_Folder_4 = toplevel
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Project_Folder_4 = toplevel
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Project_Folder_P_4 = folder {Top Level}
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Project_Folder_P_4 = folder {Top Level}
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Echo_Compile_Output = 0
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Echo_Compile_Output = 0
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Save_Compile_Report = 1
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Save_Compile_Report = 1
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Project_Opt_Count = 0
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Project_Opt_Count = 0
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ForceSoftPaths = 1
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ForceSoftPaths = 1
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ProjectStatusDelay = 5000
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ProjectStatusDelay = 5000
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VERILOG_DoubleClick = Edit
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VERILOG_DoubleClick = Edit
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VERILOG_CustomDoubleClick =
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VERILOG_CustomDoubleClick =
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SYSTEMVERILOG_DoubleClick = Compile
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SYSTEMVERILOG_DoubleClick = Compile
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SYSTEMVERILOG_CustomDoubleClick =
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SYSTEMVERILOG_CustomDoubleClick =
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VHDL_DoubleClick = Edit
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VHDL_DoubleClick = Edit
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VHDL_CustomDoubleClick =
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VHDL_CustomDoubleClick =
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PSL_DoubleClick = Edit
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PSL_DoubleClick = Edit
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PSL_CustomDoubleClick =
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PSL_CustomDoubleClick =
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TEXT_DoubleClick = Edit
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TEXT_DoubleClick = Edit
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TEXT_CustomDoubleClick =
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TEXT_CustomDoubleClick =
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SYSTEMC_DoubleClick = Edit
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SYSTEMC_DoubleClick = Edit
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SYSTEMC_CustomDoubleClick =
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SYSTEMC_CustomDoubleClick =
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TCL_DoubleClick = Edit
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TCL_DoubleClick = Edit
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TCL_CustomDoubleClick =
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TCL_CustomDoubleClick =
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MACRO_DoubleClick = Edit
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MACRO_DoubleClick = Edit
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MACRO_CustomDoubleClick =
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MACRO_CustomDoubleClick =
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VCD_DoubleClick = Edit
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VCD_DoubleClick = Edit
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VCD_CustomDoubleClick =
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VCD_CustomDoubleClick =
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SDF_DoubleClick = Edit
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SDF_DoubleClick = Edit
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SDF_CustomDoubleClick =
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SDF_CustomDoubleClick =
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XML_DoubleClick = Edit
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XML_DoubleClick = Edit
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XML_CustomDoubleClick =
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XML_CustomDoubleClick =
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LOGFILE_DoubleClick = Edit
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LOGFILE_DoubleClick = Edit
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LOGFILE_CustomDoubleClick =
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LOGFILE_CustomDoubleClick =
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UCDB_DoubleClick = Edit
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UCDB_DoubleClick = Edit
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UCDB_CustomDoubleClick =
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UCDB_CustomDoubleClick =
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UPF_DoubleClick = Edit
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UPF_DoubleClick = Edit
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UPF_CustomDoubleClick =
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UPF_CustomDoubleClick =
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PCF_DoubleClick = Edit
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PCF_DoubleClick = Edit
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PCF_CustomDoubleClick =
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PCF_CustomDoubleClick =
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PROJECT_DoubleClick = Edit
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PROJECT_DoubleClick = Edit
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PROJECT_CustomDoubleClick =
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PROJECT_CustomDoubleClick =
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VRM_DoubleClick = Edit
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VRM_DoubleClick = Edit
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VRM_CustomDoubleClick =
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VRM_CustomDoubleClick =
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DEBUGDATABASE_DoubleClick = Edit
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DEBUGDATABASE_DoubleClick = Edit
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DEBUGDATABASE_CustomDoubleClick =
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DEBUGDATABASE_CustomDoubleClick =
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DEBUGARCHIVE_DoubleClick = Edit
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DEBUGARCHIVE_DoubleClick = Edit
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DEBUGARCHIVE_CustomDoubleClick =
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DEBUGARCHIVE_CustomDoubleClick =
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Project_Major_Version = 10
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Project_Major_Version = 10
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Project_Minor_Version = 1
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Project_Minor_Version = 1
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