//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Testbench for the top level design
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// Testbench for the top level design
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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`include "z80.svh"
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`include "z80.svh"
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module test_bench_top(z80_if.tb z);
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module test_bench_top(z80_if.tb z);
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assign clk = z.CLK;
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assign clk = z.CLK;
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initial begin : init
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initial begin : init
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$display("Test: Start of test at %d", $time);
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$display("Test: Start of test at %d", $time);
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z.nWAIT <= `CLR;
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z.nWAIT <= `CLR;
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z.nINT <= `CLR;
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z.nINT <= `CLR;
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z.nNMI <= `CLR;
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z.nNMI <= `CLR;
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z.nBUSRQ <= `CLR;
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z.nBUSRQ <= `CLR;
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force dut.z80_top_ifc_n.fpga_reset=1;
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z.nRESET <= `SET;
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z.nRESET <= `SET;
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#2 force dut.z80_top_ifc_n.fpga_reset=0;
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#2 repeat (3) @(posedge clk);
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repeat (3) @(posedge clk);
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z.nRESET <= `CLR;
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z.nRESET <= `CLR;
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end : init
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end : init
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Testbench for interrupt testing
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// Testbench for interrupt testing
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// Enable one or more interrupt generators and run them with the
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// Enable one or more interrupt generators and run them with the
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// 'hello world' code
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// 'hello world' code
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Infuse a NMI at a certain clock
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// Infuse a NMI at a certain clock
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initial begin : nmi_once
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initial begin : nmi_once
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repeat (500) @(posedge clk);
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repeat (500) @(posedge clk);
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// z.nNMI <= `SET;
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// z.nNMI <= `SET;
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repeat (1) @(posedge clk);
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repeat (1) @(posedge clk);
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z.nNMI <= `CLR;
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z.nNMI <= `CLR;
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end : nmi_once
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end : nmi_once
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// Test sending a *periodic* NMI
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// Test sending a *periodic* NMI
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always begin : nmi_rep
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always begin : nmi_rep
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repeat (3000) @(posedge clk);
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repeat (3000) @(posedge clk);
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// z.nNMI <= `SET;
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// z.nNMI <= `SET;
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repeat (1) @(posedge clk);
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repeat (1) @(posedge clk);
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z.nNMI <= `CLR;
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z.nNMI <= `CLR;
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end : nmi_rep
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end : nmi_rep
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// Infuse an INT at a certain clock
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// Infuse an INT at a certain clock
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initial begin : int_once
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initial begin : int_once
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repeat (1000) @(posedge clk);
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repeat (1000) @(posedge clk);
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// z.nINT <= `SET;
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// z.nINT <= `SET;
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repeat (300) @(posedge clk);
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repeat (300) @(posedge clk);
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z.nINT <= `CLR;
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z.nINT <= `CLR;
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end : int_once
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end : int_once
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// Test sending a *periodic* INT
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// Test sending a *periodic* INT
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always begin : int_rep
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always begin : int_rep
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repeat (5000) @(posedge clk);
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repeat (5000) @(posedge clk);
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// z.nINT <= `SET;
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// z.nINT <= `SET;
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repeat (300) @(posedge clk);
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repeat (300) @(posedge clk);
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z.nINT <= `CLR;
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z.nINT <= `CLR;
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end : int_rep
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end : int_rep
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// Test WAIT.. inject at will
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// Test WAIT.. inject at will
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initial begin : wait_once
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initial begin : wait_once
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repeat (1008) @(posedge clk);
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repeat (1008) @(posedge clk);
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// z.nWAIT <= `SET;
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// z.nWAIT <= `SET;
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repeat (2) @(posedge clk);
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repeat (2) @(posedge clk);
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z.nWAIT <= `CLR;
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z.nWAIT <= `CLR;
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end : wait_once
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end : wait_once
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// Test BUSRQ / BUSACK
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// Test BUSRQ / BUSACK
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initial begin : busrq_once
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initial begin : busrq_once
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repeat (10) @(posedge clk);
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repeat (10) @(posedge clk);
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// z.nBUSRQ <= `SET;
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// z.nBUSRQ <= `SET;
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repeat (10) @(posedge clk);
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repeat (10) @(posedge clk);
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z.nBUSRQ <= `CLR;
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z.nBUSRQ <= `CLR;
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end : busrq_once
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end : busrq_once
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// Test special RESET
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// Test special RESET
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initial begin : spc_reset
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initial begin : spc_reset
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repeat (40) @(posedge clk);
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repeat (40) @(posedge clk);
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// z.nRESET <= `SET;
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// z.nRESET <= `SET;
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repeat (1) @(posedge clk);
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repeat (1) @(posedge clk);
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z.nRESET <= `CLR;
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z.nRESET <= `CLR;
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end : spc_reset
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end : spc_reset
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endmodule
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endmodule
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module test_top();
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module test_top();
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// Although the clock is going forever, we will stop simulation at some point
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// Although the clock is going forever, we will stop simulation at some point
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bit clk = 1;
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bit clk = 1;
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initial forever #1 clk = ~clk;
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initial forever #1 clk = ~clk;
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// Stop after printing "Hello, World!"
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// Stop after printing "Hello, World!"
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initial begin : stopme
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initial begin : stopme
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#70000 $stop();
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#70000 $stop();
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end : stopme
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end : stopme
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z80_if z80(clk); // Instantiate the Z80 bus interface
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z80_if z80(clk); // Instantiate the Z80 bus interface
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z80_top_ifc_n dut(z80); // Create an instance of our Z80 design
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z80_top_ifc_n dut(z80); // Create an instance of our Z80 design
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test_bench_top tb(z80); // Create an instance of the test bench
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test_bench_top tb(z80); // Create an instance of the test bench
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ram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );
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ram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );
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io io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );
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io io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );
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iorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );
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iorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );
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endmodule
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endmodule
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