/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE AC 97 Codec ////
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//// WISHBONE AC 97 Codec ////
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//// Serial Output Block ////
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//// Serial Output Block ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_codec_sout.v,v 1.2 2002-09-19 06:36:19 rudi Exp $
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// $Id: ac97_codec_sout.v,v 1.2 2002-09-19 06:36:19 rudi Exp $
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//
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//
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// $Date: 2002-09-19 06:36:19 $
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// $Date: 2002-09-19 06:36:19 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/13 08:22:32 rudi
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// Revision 1.1 2002/02/13 08:22:32 rudi
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//
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//
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// Added test bench for public release
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// Added test bench for public release
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//
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//
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//
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//
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//
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//
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//
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//
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`include "ac97_defines.v"
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`include "ac97_defines.v"
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module ac97_codec_sout(clk, rst,
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module ac97_codec_sout(clk, rst,
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sync, slt0, slt1, slt2, slt3, slt4, slt5,
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sync, slt0, slt1, slt2, slt3, slt4, slt5,
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slt6, slt7, slt8, slt9, slt10, slt11, slt12,
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slt6, slt7, slt8, slt9, slt10, slt11, slt12,
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sdata_out
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sdata_out
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);
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);
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input clk, rst;
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input clk, rst;
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// --------------------------------------
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// --------------------------------------
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// Misc Signals
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// Misc Signals
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input sync;
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input sync;
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input [15:0] slt0;
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input [15:0] slt0;
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input [19:0] slt1;
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input [19:0] slt1;
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input [19:0] slt2;
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input [19:0] slt2;
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input [19:0] slt3;
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input [19:0] slt3;
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input [19:0] slt4;
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input [19:0] slt4;
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input [19:0] slt5;
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input [19:0] slt5;
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input [19:0] slt6;
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input [19:0] slt6;
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input [19:0] slt7;
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input [19:0] slt7;
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input [19:0] slt8;
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input [19:0] slt8;
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input [19:0] slt9;
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input [19:0] slt9;
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input [19:0] slt10;
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input [19:0] slt10;
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input [19:0] slt11;
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input [19:0] slt11;
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input [19:0] slt12;
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input [19:0] slt12;
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// --------------------------------------
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// --------------------------------------
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// AC97 Codec Interface
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// AC97 Codec Interface
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output sdata_out;
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output sdata_out;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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reg sdata_out_r;
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reg sdata_out_r;
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reg [15:0] slt0_r;
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reg [15:0] slt0_r;
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reg [19:0] slt1_r;
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reg [19:0] slt1_r;
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reg [19:0] slt2_r;
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reg [19:0] slt2_r;
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reg [19:0] slt3_r;
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reg [19:0] slt3_r;
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reg [19:0] slt4_r;
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reg [19:0] slt4_r;
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reg [19:0] slt5_r;
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reg [19:0] slt5_r;
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reg [19:0] slt6_r;
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reg [19:0] slt6_r;
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reg [19:0] slt7_r;
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reg [19:0] slt7_r;
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reg [19:0] slt8_r;
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reg [19:0] slt8_r;
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reg [19:0] slt9_r;
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reg [19:0] slt9_r;
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reg [19:0] slt10_r;
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reg [19:0] slt10_r;
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reg [19:0] slt11_r;
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reg [19:0] slt11_r;
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reg [19:0] slt12_r;
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reg [19:0] slt12_r;
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reg sync_r;
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reg sync_r;
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wire sync_e;
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wire sync_e;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Misc Logic
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// Misc Logic
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//
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//
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// Sync Edge detector
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// Sync Edge detector
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always @(posedge clk)
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always @(posedge clk)
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sync_r <= #1 sync;
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sync_r <= #1 sync;
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assign sync_e = sync & !sync_r;
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assign sync_e = sync & !sync_r;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Serial Shift Register
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// Serial Shift Register
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//
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//
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/*
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/*
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always @(negedge clk)
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always @(negedge clk)
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sdata_out_r <= #1 slt0_r[15];
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sdata_out_r <= #1 slt0_r[15];
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//assign sdata_out = sdata_out_r;
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//assign sdata_out = sdata_out_r;
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*/
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*/
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assign sdata_out = slt0_r[15];
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assign sdata_out = slt0_r[15];
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt0_r <= #1 slt0;
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if(sync_e) slt0_r <= #1 slt0;
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else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
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else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt1_r <= #1 slt1;
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if(sync_e) slt1_r <= #1 slt1;
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else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
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else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt2_r <= #1 slt2;
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if(sync_e) slt2_r <= #1 slt2;
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else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
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else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt3_r <= #1 slt3;
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if(sync_e) slt3_r <= #1 slt3;
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else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
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else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt4_r <= #1 slt4;
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if(sync_e) slt4_r <= #1 slt4;
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else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
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else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt5_r <= #1 slt5;
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if(sync_e) slt5_r <= #1 slt5;
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else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
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else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt6_r <= #1 slt6;
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if(sync_e) slt6_r <= #1 slt6;
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else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
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else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt7_r <= #1 slt7;
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if(sync_e) slt7_r <= #1 slt7;
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else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
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else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt8_r <= #1 slt8;
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if(sync_e) slt8_r <= #1 slt8;
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else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
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else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt9_r <= #1 slt9;
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if(sync_e) slt9_r <= #1 slt9;
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else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
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else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt10_r <= #1 slt10;
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if(sync_e) slt10_r <= #1 slt10;
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else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
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else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt11_r <= #1 slt11;
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if(sync_e) slt11_r <= #1 slt11;
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else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
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else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
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always @(posedge clk)
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always @(posedge clk)
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if(sync_e) slt12_r <= #1 slt12;
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if(sync_e) slt12_r <= #1 slt12;
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else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
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else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
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endmodule
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endmodule
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