/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// WISHBONE Master Model ////
|
//// WISHBONE Master Model ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author: Rudolf Usselmann ////
|
//// Author: Rudolf Usselmann ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
|
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: wb_mast_model.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
|
// $Id: wb_mast_model.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
|
//
|
//
|
// $Date: 2002-02-13 08:22:32 $
|
// $Date: 2002-02-13 08:22:32 $
|
// $Revision: 1.1 $
|
// $Revision: 1.1 $
|
// $Author: rudi $
|
// $Author: rudi $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
//
|
//
|
//
|
//
|
//
|
//
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//
|
//
|
|
|
`include "wb_model_defines.v"
|
`include "wb_model_defines.v"
|
|
|
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
|
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
|
|
|
input clk, rst;
|
input clk, rst;
|
output [31:0] adr;
|
output [31:0] adr;
|
input [31:0] din;
|
input [31:0] din;
|
output [31:0] dout;
|
output [31:0] dout;
|
output cyc, stb;
|
output cyc, stb;
|
output [3:0] sel;
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output [3:0] sel;
|
output we;
|
output we;
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input ack, err, rty;
|
input ack, err, rty;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Local Wires
|
// Local Wires
|
//
|
//
|
|
|
parameter mem_size = 4096;
|
parameter mem_size = 4096;
|
|
|
reg [31:0] adr;
|
reg [31:0] adr;
|
reg [31:0] dout;
|
reg [31:0] dout;
|
reg cyc, stb;
|
reg cyc, stb;
|
reg [3:0] sel;
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reg [3:0] sel;
|
reg we;
|
reg we;
|
|
|
reg [31:0] rd_mem[mem_size:0];
|
reg [31:0] rd_mem[mem_size:0];
|
reg [31:0] wr_mem[mem_size:0];
|
reg [31:0] wr_mem[mem_size:0];
|
integer rd_cnt;
|
integer rd_cnt;
|
integer wr_cnt;
|
integer wr_cnt;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Memory Logic
|
// Memory Logic
|
//
|
//
|
|
|
initial
|
initial
|
begin
|
begin
|
//adr = 32'hxxxx_xxxx;
|
//adr = 32'hxxxx_xxxx;
|
//adr = 0;
|
//adr = 0;
|
adr = 32'hffff_ffff;
|
adr = 32'hffff_ffff;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
cyc = 0;
|
cyc = 0;
|
stb = 0;
|
stb = 0;
|
sel = 4'hx;
|
sel = 4'hx;
|
we = 1'hx;
|
we = 1'hx;
|
rd_cnt = 0;
|
rd_cnt = 0;
|
wr_cnt = 0;
|
wr_cnt = 0;
|
#1;
|
#1;
|
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
|
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
|
end
|
end
|
|
|
|
|
|
|
task mem_fill;
|
task mem_fill;
|
|
|
integer n;
|
integer n;
|
begin
|
begin
|
rd_cnt = 0;
|
rd_cnt = 0;
|
wr_cnt = 0;
|
wr_cnt = 0;
|
for(n=0;n<mem_size;n=n+1)
|
for(n=0;n<mem_size;n=n+1)
|
begin
|
begin
|
rd_mem[n] = $random;
|
rd_mem[n] = $random;
|
wr_mem[n] = $random;
|
wr_mem[n] = $random;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Write 1 Word Task
|
// Write 1 Word Task
|
//
|
//
|
|
|
task wb_wr1;
|
task wb_wr1;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input [31:0] d;
|
input [31:0] d;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
adr = a;
|
adr = a;
|
dout = d;
|
dout = d;
|
cyc = 1;
|
cyc = 1;
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
sel = s;
|
sel = s;
|
|
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#1;
|
#1;
|
cyc=0;
|
cyc=0;
|
stb=0;
|
stb=0;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
//adr = 32'hffff_ffff;
|
//adr = 32'hffff_ffff;
|
//adr = 0;
|
//adr = 0;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Write 4 Words Task
|
// Write 4 Words Task
|
//
|
//
|
|
|
task wb_wr4;
|
task wb_wr4;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input [31:0] d1;
|
input [31:0] d1;
|
input [31:0] d2;
|
input [31:0] d2;
|
input [31:0] d3;
|
input [31:0] d3;
|
input [31:0] d4;
|
input [31:0] d4;
|
|
|
integer delay;
|
integer delay;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
sel = s;
|
sel = s;
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
adr = a;
|
adr = a;
|
dout = d1;
|
dout = d1;
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
|
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
stb=1;
|
stb=1;
|
//adr = a+4;
|
//adr = a+4;
|
dout = d2;
|
dout = d2;
|
we=1;
|
we=1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
stb=1;
|
stb=1;
|
//adr = a+8;
|
//adr = a+8;
|
dout = d3;
|
dout = d3;
|
we=1;
|
we=1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
stb=1;
|
stb=1;
|
//adr = a+12;
|
//adr = a+12;
|
dout = d4;
|
dout = d4;
|
we=1;
|
we=1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
|
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
//adr = 0;
|
//adr = 0;
|
//adr = 32'hffff_ffff;
|
//adr = 32'hffff_ffff;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task wb_wr_mult;
|
task wb_wr_mult;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input count;
|
input count;
|
|
|
integer delay;
|
integer delay;
|
integer count;
|
integer count;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
|
|
for(n=0;n<count;n=n+1)
|
for(n=0;n<count;n=n+1)
|
begin
|
begin
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
adr = a + (n*4);
|
adr = a + (n*4);
|
dout = wr_mem[n + wr_cnt];
|
dout = wr_mem[n + wr_cnt];
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
sel = s;
|
sel = s;
|
if(n!=0) @(posedge clk);
|
if(n!=0) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
sel = 4'hx;
|
sel = 4'hx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
end
|
end
|
|
|
cyc=0;
|
cyc=0;
|
|
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
//adr = 32'hffff_ffff;
|
//adr = 32'hffff_ffff;
|
|
|
wr_cnt = wr_cnt + count;
|
wr_cnt = wr_cnt + count;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task wb_rmw;
|
task wb_rmw;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input rcount;
|
input rcount;
|
input wcount;
|
input wcount;
|
|
|
integer delay;
|
integer delay;
|
integer rcount;
|
integer rcount;
|
integer wcount;
|
integer wcount;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
for(n=0;n<rcount-1;n=n+1)
|
for(n=0;n<rcount-1;n=n+1)
|
begin
|
begin
|
adr = a + (n*4);
|
adr = a + (n*4);
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
end
|
end
|
|
|
adr = a+(n*4);
|
adr = a+(n*4);
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
rd_cnt = rd_cnt + rcount;
|
rd_cnt = rd_cnt + rcount;
|
|
|
//@(posedge clk);
|
//@(posedge clk);
|
|
|
|
|
for(n=0;n<wcount;n=n+1)
|
for(n=0;n<wcount;n=n+1)
|
begin
|
begin
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
adr = a + (n*4);
|
adr = a + (n*4);
|
dout = wr_mem[n + wr_cnt];
|
dout = wr_mem[n + wr_cnt];
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
sel = s;
|
sel = s;
|
// if(n!=0)
|
// if(n!=0)
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
sel = 4'hx;
|
sel = 4'hx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
end
|
end
|
|
|
cyc=0;
|
cyc=0;
|
|
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
//adr = 32'hffff_ffff;
|
//adr = 32'hffff_ffff;
|
|
|
wr_cnt = wr_cnt + wcount;
|
wr_cnt = wr_cnt + wcount;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Read 1 Word Task
|
// Read 1 Word Task
|
//
|
//
|
|
|
task wb_rd1;
|
task wb_rd1;
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input [31:0] a;
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input [31:0] a;
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input [3:0] s;
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input [3:0] s;
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output [31:0] d;
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output [31:0] d;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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adr = a;
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adr = a;
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cyc = 1;
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cyc = 1;
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stb = 1;
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stb = 1;
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we = 0;
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we = 0;
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sel = s;
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sel = s;
|
|
|
//@(posedge clk);
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//@(posedge clk);
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while(~ack & ~err) @(posedge clk);
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while(~ack & ~err) @(posedge clk);
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d = din;
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d = din;
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#1;
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#1;
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cyc=0;
|
cyc=0;
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stb=0;
|
stb=0;
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//adr = 32'hxxxx_xxxx;
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//adr = 32'hxxxx_xxxx;
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//adr = 0;
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//adr = 0;
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adr = 32'hffff_ffff;
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adr = 32'hffff_ffff;
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dout = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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we = 1'hx;
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we = 1'hx;
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sel = 4'hx;
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sel = 4'hx;
|
|
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end
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end
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endtask
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endtask
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
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//
|
//
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// Read 4 Words Task
|
// Read 4 Words Task
|
//
|
//
|
|
|
|
|
task wb_rd4;
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task wb_rd4;
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input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
output [31:0] d1;
|
output [31:0] d1;
|
output [31:0] d2;
|
output [31:0] d2;
|
output [31:0] d3;
|
output [31:0] d3;
|
output [31:0] d4;
|
output [31:0] d4;
|
|
|
integer delay;
|
integer delay;
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
adr = a;
|
adr = a;
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d1 = din;
|
d1 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
//adr = a+4;
|
//adr = a+4;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d2 = din;
|
d2 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
|
|
//adr = a+8;
|
//adr = a+8;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d3 = din;
|
d3 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
//adr = a+12;
|
//adr = a+12;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d4 = din;
|
d4 = din;
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hffff_ffff;
|
adr = 32'hffff_ffff;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
task wb_rd_mult;
|
task wb_rd_mult;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input count;
|
input count;
|
|
|
integer delay;
|
integer delay;
|
integer count;
|
integer count;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
for(n=0;n<count-1;n=n+1)
|
for(n=0;n<count-1;n=n+1)
|
begin
|
begin
|
adr = a + (n*4);
|
adr = a + (n*4);
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
end
|
end
|
|
|
adr = a+(n*4);
|
adr = a+(n*4);
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hffff_ffff;
|
adr = 32'hffff_ffff;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
rd_cnt = rd_cnt + count;
|
rd_cnt = rd_cnt + count;
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
