/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE AC 97 Controller ////
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//// WISHBONE AC 97 Controller ////
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//// DMA Interface ////
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//// DMA Interface ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_dma_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
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// $Id: ac97_dma_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
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//
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//
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// $Date: 2002-09-19 06:30:56 $
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// $Date: 2002-09-19 06:30:56 $
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// $Revision: 1.4 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/03/05 04:44:05 rudi
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// Revision 1.3 2002/03/05 04:44:05 rudi
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//
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//
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Many minor synthesis cleanup items ...
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// - Many minor synthesis cleanup items ...
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//
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//
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// Revision 1.2 2001/08/10 08:09:42 rudi
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// Revision 1.2 2001/08/10 08:09:42 rudi
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//
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//
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// - Removed RTY_O output.
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// - Removed RTY_O output.
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// - Added Clock and Reset Inputs to documentation.
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// - Added Clock and Reset Inputs to documentation.
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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//
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//
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// Revision 1.1 2001/08/03 06:54:49 rudi
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// Revision 1.1 2001/08/03 06:54:49 rudi
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//
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//
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//
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//
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// - Changed to new directory structure
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// - Changed to new directory structure
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//
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//
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// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
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// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
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// Initial Checkin
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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`include "ac97_defines.v"
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`include "ac97_defines.v"
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module ac97_dma_if(clk, rst,
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module ac97_dma_if(clk, rst,
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o3_status, o4_status, o6_status, o7_status, o8_status, o9_status,
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o3_status, o4_status, o6_status, o7_status, o8_status, o9_status,
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o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty,
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o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty,
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i3_status, i4_status, i6_status,
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i3_status, i4_status, i6_status,
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i3_full, i4_full, i6_full,
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i3_full, i4_full, i6_full,
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oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
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oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
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ic0_cfg, ic1_cfg, ic2_cfg,
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ic0_cfg, ic1_cfg, ic2_cfg,
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dma_req, dma_ack);
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dma_req, dma_ack);
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input clk, rst;
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input clk, rst;
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input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
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input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
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input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
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input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
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input [1:0] i3_status, i4_status, i6_status;
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input [1:0] i3_status, i4_status, i6_status;
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input i3_full, i4_full, i6_full;
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input i3_full, i4_full, i6_full;
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input [7:0] oc0_cfg;
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input [7:0] oc0_cfg;
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input [7:0] oc1_cfg;
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input [7:0] oc1_cfg;
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input [7:0] oc2_cfg;
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input [7:0] oc2_cfg;
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input [7:0] oc3_cfg;
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input [7:0] oc3_cfg;
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input [7:0] oc4_cfg;
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input [7:0] oc4_cfg;
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input [7:0] oc5_cfg;
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input [7:0] oc5_cfg;
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input [7:0] ic0_cfg;
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input [7:0] ic0_cfg;
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input [7:0] ic1_cfg;
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input [7:0] ic1_cfg;
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input [7:0] ic2_cfg;
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input [7:0] ic2_cfg;
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output [8:0] dma_req;
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output [8:0] dma_req;
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input [8:0] dma_ack;
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input [8:0] dma_ack;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// DMA Request Modules
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// DMA Request Modules
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//
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//
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ac97_dma_req u0(.clk( clk ),
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ac97_dma_req u0(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc0_cfg ),
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.cfg( oc0_cfg ),
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.status( o3_status ),
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.status( o3_status ),
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.full_empty( o3_empty ),
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.full_empty( o3_empty ),
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.dma_req( dma_req[0] ),
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.dma_req( dma_req[0] ),
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.dma_ack( dma_ack[0] )
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.dma_ack( dma_ack[0] )
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);
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);
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ac97_dma_req u1(.clk( clk ),
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ac97_dma_req u1(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc1_cfg ),
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.cfg( oc1_cfg ),
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.status( o4_status ),
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.status( o4_status ),
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.full_empty( o4_empty ),
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.full_empty( o4_empty ),
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.dma_req( dma_req[1] ),
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.dma_req( dma_req[1] ),
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.dma_ack( dma_ack[1] )
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.dma_ack( dma_ack[1] )
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);
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);
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`ifdef AC97_CENTER
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`ifdef AC97_CENTER
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ac97_dma_req u2(.clk( clk ),
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ac97_dma_req u2(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc2_cfg ),
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.cfg( oc2_cfg ),
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.status( o6_status ),
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.status( o6_status ),
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.full_empty( o6_empty ),
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.full_empty( o6_empty ),
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.dma_req( dma_req[2] ),
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.dma_req( dma_req[2] ),
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.dma_ack( dma_ack[2] )
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.dma_ack( dma_ack[2] )
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);
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);
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`else
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`else
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assign dma_req[2] = 1'b0;
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assign dma_req[2] = 1'b0;
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`endif
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`endif
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`ifdef AC97_SURROUND
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`ifdef AC97_SURROUND
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ac97_dma_req u3(.clk( clk ),
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ac97_dma_req u3(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc3_cfg ),
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.cfg( oc3_cfg ),
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.status( o7_status ),
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.status( o7_status ),
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.full_empty( o7_empty ),
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.full_empty( o7_empty ),
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.dma_req( dma_req[3] ),
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.dma_req( dma_req[3] ),
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.dma_ack( dma_ack[3] )
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.dma_ack( dma_ack[3] )
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);
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);
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ac97_dma_req u4(.clk( clk ),
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ac97_dma_req u4(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc4_cfg ),
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.cfg( oc4_cfg ),
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.status( o8_status ),
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.status( o8_status ),
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.full_empty( o8_empty ),
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.full_empty( o8_empty ),
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.dma_req( dma_req[4] ),
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.dma_req( dma_req[4] ),
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.dma_ack( dma_ack[4] )
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.dma_ack( dma_ack[4] )
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);
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);
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`else
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`else
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assign dma_req[3] = 1'b0;
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assign dma_req[3] = 1'b0;
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assign dma_req[4] = 1'b0;
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assign dma_req[4] = 1'b0;
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`endif
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`endif
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`ifdef AC97_LFE
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`ifdef AC97_LFE
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ac97_dma_req u5(.clk( clk ),
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ac97_dma_req u5(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( oc5_cfg ),
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.cfg( oc5_cfg ),
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.status( o9_status ),
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.status( o9_status ),
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.full_empty( o9_empty ),
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.full_empty( o9_empty ),
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.dma_req( dma_req[5] ),
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.dma_req( dma_req[5] ),
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.dma_ack( dma_ack[5] )
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.dma_ack( dma_ack[5] )
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);
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);
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`else
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`else
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assign dma_req[5] = 1'b0;
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assign dma_req[5] = 1'b0;
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`endif
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`endif
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`ifdef AC97_SIN
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`ifdef AC97_SIN
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ac97_dma_req u6(.clk( clk ),
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ac97_dma_req u6(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( ic0_cfg ),
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.cfg( ic0_cfg ),
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.status( i3_status ),
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.status( i3_status ),
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.full_empty( i3_full ),
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.full_empty( i3_full ),
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.dma_req( dma_req[6] ),
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.dma_req( dma_req[6] ),
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.dma_ack( dma_ack[6] )
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.dma_ack( dma_ack[6] )
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);
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);
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|
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ac97_dma_req u7(.clk( clk ),
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ac97_dma_req u7(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( ic1_cfg ),
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.cfg( ic1_cfg ),
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.status( i4_status ),
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.status( i4_status ),
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.full_empty( i4_full ),
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.full_empty( i4_full ),
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.dma_req( dma_req[7] ),
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.dma_req( dma_req[7] ),
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.dma_ack( dma_ack[7] )
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.dma_ack( dma_ack[7] )
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);
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);
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`else
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`else
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assign dma_req[6] = 1'b0;
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assign dma_req[6] = 1'b0;
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assign dma_req[7] = 1'b0;
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assign dma_req[7] = 1'b0;
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`endif
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`endif
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`ifdef AC97_MICIN
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`ifdef AC97_MICIN
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ac97_dma_req u8(.clk( clk ),
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ac97_dma_req u8(.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.cfg( ic2_cfg ),
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.cfg( ic2_cfg ),
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.status( i6_status ),
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.status( i6_status ),
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.full_empty( i6_full ),
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.full_empty( i6_full ),
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.dma_req( dma_req[8] ),
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.dma_req( dma_req[8] ),
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.dma_ack( dma_ack[8] )
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.dma_ack( dma_ack[8] )
|
);
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);
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`else
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`else
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assign dma_req[8] = 1'b0;
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assign dma_req[8] = 1'b0;
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`endif
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`endif
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endmodule
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endmodule
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