/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE AC 97 Controller Reset Module ////
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//// WISHBONE AC 97 Controller Reset Module ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_rst.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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// $Id: ac97_rst.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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//
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//
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// $Date: 2001-08-03 06:54:50 $
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// $Date: 2001-08-03 06:54:50 $
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// $Revision: 1.1 $
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// $Revision: 1.1 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/05/19 02:29:19 rudi
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// Revision 1.1.1.1 2001/05/19 02:29:19 rudi
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// Initial Checkin
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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`include "ac97_defines.v"
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`include "ac97_defines.v"
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module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
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module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
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input clk, rst;
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input clk, rst;
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input rst_force;
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input rst_force;
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output ps_ce;
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output ps_ce;
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output ac97_rst_;
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output ac97_rst_;
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reg ac97_rst_;
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reg ac97_rst_;
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reg [2:0] cnt;
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reg [2:0] cnt;
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wire ce;
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wire ce;
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wire to;
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wire to;
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reg [5:0] ps_cnt;
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reg [5:0] ps_cnt;
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wire ps_ce;
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wire ps_ce;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ac97_rst_ <= #1 0;
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if(!rst) ac97_rst_ <= #1 0;
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else
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else
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if(rst_force) ac97_rst_ <= #1 0;
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if(rst_force) ac97_rst_ <= #1 0;
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else
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else
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if(to) ac97_rst_ <= #1 1;
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if(to) ac97_rst_ <= #1 1;
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assign to = (cnt == `AC97_RST_DEL);
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assign to = (cnt == `AC97_RST_DEL);
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) cnt <= #1 0;
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if(!rst) cnt <= #1 0;
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else
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else
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if(rst_force) cnt <= #1 0;
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if(rst_force) cnt <= #1 0;
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else
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else
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if(ce) cnt <= #1 cnt + 1;
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if(ce) cnt <= #1 cnt + 1;
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assign ce = ps_ce & (cnt != `AC97_RST_DEL);
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assign ce = ps_ce & (cnt != `AC97_RST_DEL);
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ps_cnt <= #1 0;
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if(!rst) ps_cnt <= #1 0;
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else
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else
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if(ps_ce | rst_force) ps_cnt <= #1 0;
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if(ps_ce | rst_force) ps_cnt <= #1 0;
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else ps_cnt <= #1 ps_cnt + 1;
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else ps_cnt <= #1 ps_cnt + 1;
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assign ps_ce = (ps_cnt == `AC97_250_PS);
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assign ps_ce = (ps_cnt == `AC97_250_PS);
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endmodule
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endmodule
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