OpenCores

Rev 17	Rev 20
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// WISHBONE AC 97 Controller ////`	`//// WISHBONE AC 97 Controller ////`
`//// Serial Output Controller ////`	`//// Serial Output Controller ////`
`//// ////`	`//// ////`
`//// ////`	`//// ////`
`//// Author: Rudolf Usselmann ////`	`//// Author: Rudolf Usselmann ////`
`//// rudi@asics.ws ////`	`//// rudi@asics.ws ////`
`//// ////`	`//// ////`
`//// ////`	`//// ////`
`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`	`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
`//// www.asics.ws ////`	`//// www.asics.ws ////`
`//// rudi@asics.ws ////`	`//// rudi@asics.ws ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
`//// removed from the file and that any derivative work contains ////`	`//// removed from the file and that any derivative work contains ////`
`//// the original copyright notice and the associated disclaimer.////`	`//// the original copyright notice and the associated disclaimer.////`
`//// ////`	`//// ////`
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////	//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`	`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`	`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`	`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`	`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`	`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`	`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`	`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`	`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`	`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`	`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`	`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
`//// POSSIBILITY OF SUCH DAMAGE. ////`	`//// POSSIBILITY OF SUCH DAMAGE. ////`
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $`	`// $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $`
`//`	`//`
`// $Date: 2002-09-19 06:30:56 $`	`// $Date: 2002-09-19 06:30:56 $`
`// $Revision: 1.3 $`	`// $Revision: 1.3 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
`// Revision 1.2 2002/03/05 04:44:05 rudi`	`// Revision 1.2 2002/03/05 04:44:05 rudi`
`//`	`//`
`// - Fixed the order of the thrash hold bits to match the spec.`	`// - Fixed the order of the thrash hold bits to match the spec.`
`// - Many minor synthesis cleanup items ...`	`// - Many minor synthesis cleanup items ...`
`//`	`//`
`// Revision 1.1 2001/08/03 06:54:50 rudi`	`// Revision 1.1 2001/08/03 06:54:50 rudi`
`//`	`//`
`//`	`//`
`// - Changed to new directory structure`	`// - Changed to new directory structure`
`//`	`//`
`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`	`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`
`// Initial Checkin`	`// Initial Checkin`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

`include "ac97_defines.v"	`include "ac97_defines.v"

`module ac97_soc(clk, wclk, rst,`	`module ac97_soc(clk, wclk, rst,`
`ps_ce, resume, suspended,`	`ps_ce, resume, suspended,`
`sync, out_le, in_valid, ld, valid`	`sync, out_le, in_valid, ld, valid`
`);`	`);`

`input clk, wclk, rst;`	`input clk, wclk, rst;`
`input ps_ce;`	`input ps_ce;`
`input resume;`	`input resume;`
`output suspended;`	`output suspended;`
`output sync;`	`output sync;`
`output [5:0] out_le;`	`output [5:0] out_le;`
`output [2:0] in_valid;`	`output [2:0] in_valid;`
`output ld;`	`output ld;`
`output valid;`	`output valid;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Local Wires`	`// Local Wires`
`//`	`//`

`reg [7:0] cnt;`	`reg [7:0] cnt;`
`reg sync_beat;`	`reg sync_beat;`
`reg sync_resume;`	`reg sync_resume;`
`reg [5:0] out_le;`	`reg [5:0] out_le;`
`reg ld;`	`reg ld;`
`reg valid;`	`reg valid;`
`reg [2:0] in_valid;`	`reg [2:0] in_valid;`
`reg bit_clk_r;`	`reg bit_clk_r;`
`reg bit_clk_r1;`	`reg bit_clk_r1;`
`reg bit_clk_e;`	`reg bit_clk_e;`
`reg suspended;`	`reg suspended;`
`wire to;`	`wire to;`
`reg [5:0] to_cnt;`	`reg [5:0] to_cnt;`
`reg [3:0] res_cnt;`	`reg [3:0] res_cnt;`
`wire resume_done;`	`wire resume_done;`

`assign sync = sync_beat \| sync_resume;`	`assign sync = sync_beat \| sync_resume;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Misc Logic`	`// Misc Logic`
`//`	`//`

`always @(posedge clk or negedge rst)`	`always @(posedge clk or negedge rst)`
`if(!rst) cnt <= #1 8'hff;`	`if(!rst) cnt <= #1 8'hff;`
`else`	`else`
`if(suspended) cnt <= #1 8'hff;`	`if(suspended) cnt <= #1 8'hff;`
`else cnt <= #1 cnt + 8'h1;`	`else cnt <= #1 cnt + 8'h1;`

`always @(posedge clk)`	`always @(posedge clk)`
`ld <= #1 (cnt == 8'h00);`	`ld <= #1 (cnt == 8'h00);`

`always @(posedge clk)`	`always @(posedge clk)`
`sync_beat <= #1 (cnt == 8'h00) \| ((cnt > 8'h00) & (cnt < 8'h10));`	`sync_beat <= #1 (cnt == 8'h00) \| ((cnt > 8'h00) & (cnt < 8'h10));`

`always @(posedge clk)`	`always @(posedge clk)`
`valid <= #1 (cnt > 8'h39);`	`valid <= #1 (cnt > 8'h39);`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable`	`out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable`	`out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable`	`out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable`	`out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable`	`out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable`	`out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable`

`always @(posedge clk)`	`always @(posedge clk)`
`in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid`	`in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid`

`always @(posedge clk)`	`always @(posedge clk)`
`in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid`	`in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid`

`always @(posedge clk)`	`always @(posedge clk)`
`in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid`	`in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Suspend Detect`	`// Suspend Detect`
`//`	`//`

`always @(posedge wclk)`	`always @(posedge wclk)`
`bit_clk_r <= #1 clk;`	`bit_clk_r <= #1 clk;`

`always @(posedge wclk)`	`always @(posedge wclk)`
`bit_clk_r1 <= #1 bit_clk_r;`	`bit_clk_r1 <= #1 bit_clk_r;`

`always @(posedge wclk)`	`always @(posedge wclk)`
`bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) \| (!bit_clk_r & bit_clk_r1);`	`bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) \| (!bit_clk_r & bit_clk_r1);`

`always @(posedge wclk)`	`always @(posedge wclk)`
`suspended <= #1 to;`	`suspended <= #1 to;`

assign to = (to_cnt == `AC97_SUSP_DET);	assign to = (to_cnt == `AC97_SUSP_DET);

`always @(posedge wclk or negedge rst)`	`always @(posedge wclk or negedge rst)`
`if(!rst) to_cnt <= #1 6'h0;`	`if(!rst) to_cnt <= #1 6'h0;`
`else`	`else`
`if(bit_clk_e) to_cnt <= #1 6'h0;`	`if(bit_clk_e) to_cnt <= #1 6'h0;`
`else`	`else`
`if(!to) to_cnt <= #1 to_cnt + 6'h1;`	`if(!to) to_cnt <= #1 to_cnt + 6'h1;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Resume Signaling`	`// Resume Signaling`
`//`	`//`

`always @(posedge wclk or negedge rst)`	`always @(posedge wclk or negedge rst)`
`if(!rst) sync_resume <= #1 1'b0;`	`if(!rst) sync_resume <= #1 1'b0;`
`else`	`else`
`if(resume_done) sync_resume <= #1 1'b0;`	`if(resume_done) sync_resume <= #1 1'b0;`
`else`	`else`
`if(suspended & resume) sync_resume <= #1 1'b1;`	`if(suspended & resume) sync_resume <= #1 1'b1;`

assign resume_done = (res_cnt == `AC97_RES_SIG);	assign resume_done = (res_cnt == `AC97_RES_SIG);

`always @(posedge wclk)`	`always @(posedge wclk)`
`if(!sync_resume) res_cnt <= #1 4'h0;`	`if(!sync_resume) res_cnt <= #1 4'h0;`
`else`	`else`
`if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;`	`if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;`

`endmodule`	`endmodule`

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

////                                                             ////

////                                                             ////

////  WISHBONE AC 97 Controller                                  ////

////  WISHBONE AC 97 Controller                                  ////

////  Serial Output Controller                                   ////

////  Serial Output Controller                                   ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////

////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

////                                                             ////

////                                                             ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

////                         www.asics.ws                        ////

////                         www.asics.ws                        ////

////                         rudi@asics.ws                       ////

////                         rudi@asics.ws                       ////

////                                                             ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $

//  $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $

//

//

//  $Date: 2002-09-19 06:30:56 $

//  $Date: 2002-09-19 06:30:56 $

//  $Revision: 1.3 $

//  $Revision: 1.3 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.2  2002/03/05 04:44:05  rudi

//               Revision 1.2  2002/03/05 04:44:05  rudi

//

//

//               - Fixed the order of the thrash hold bits to match the spec.

//               - Fixed the order of the thrash hold bits to match the spec.

//               - Many minor synthesis cleanup items ...

//               - Many minor synthesis cleanup items ...

//

//

//               Revision 1.1  2001/08/03 06:54:50  rudi

//               Revision 1.1  2001/08/03 06:54:50  rudi

//

//

//

//

//               - Changed to new directory structure

//               - Changed to new directory structure

//

//

//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi

//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi

//               Initial Checkin

//               Initial Checkin

//

//

//

//

//

//

//

//

`include "ac97_defines.v"

`include "ac97_defines.v"

module ac97_soc(clk, wclk, rst,

module ac97_soc(clk, wclk, rst,

                ps_ce, resume, suspended,

                ps_ce, resume, suspended,

                sync, out_le, in_valid, ld, valid

                sync, out_le, in_valid, ld, valid

);

);

input           clk, wclk, rst;

input           clk, wclk, rst;

input           ps_ce;

input           ps_ce;

input           resume;

input           resume;

output          suspended;

output          suspended;

output          sync;

output          sync;

output  [5:0]    out_le;

output  [5:0]    out_le;

output  [2:0]    in_valid;

output  [2:0]    in_valid;

output          ld;

output          ld;

output          valid;

output          valid;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Local Wires

// Local Wires

//

//

reg     [7:0]    cnt;

reg     [7:0]    cnt;

reg             sync_beat;

reg             sync_beat;

reg             sync_resume;

reg             sync_resume;

reg     [5:0]    out_le;

reg     [5:0]    out_le;

reg             ld;

reg             ld;

reg             valid;

reg             valid;

reg     [2:0]    in_valid;

reg     [2:0]    in_valid;

reg             bit_clk_r;

reg             bit_clk_r;

reg             bit_clk_r1;

reg             bit_clk_r1;

reg             bit_clk_e;

reg             bit_clk_e;

reg             suspended;

reg             suspended;

wire            to;

wire            to;

reg     [5:0]    to_cnt;

reg     [5:0]    to_cnt;

reg     [3:0]    res_cnt;

reg     [3:0]    res_cnt;

wire            resume_done;

wire            resume_done;

assign sync = sync_beat | sync_resume;

assign sync = sync_beat | sync_resume;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Misc Logic

// Misc Logic

//

//

always @(posedge clk or negedge rst)

always @(posedge clk or negedge rst)

        if(!rst)                cnt <= #1 8'hff;

        if(!rst)                cnt <= #1 8'hff;

        else

        else

        if(suspended)           cnt <= #1 8'hff;

        if(suspended)           cnt <= #1 8'hff;

        else                    cnt <= #1 cnt + 8'h1;

        else                    cnt <= #1 cnt + 8'h1;

always @(posedge clk)

always @(posedge clk)

        ld <= #1 (cnt == 8'h00);

        ld <= #1 (cnt == 8'h00);

always @(posedge clk)

always @(posedge clk)

        sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));

        sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));

always @(posedge clk)

always @(posedge clk)

        valid <= #1 (cnt > 8'h39);

        valid <= #1 (cnt > 8'h39);

always @(posedge clk)

always @(posedge clk)

        out_le[0] <= #1 (cnt == 8'h11);          // Slot 0 Latch Enable

        out_le[0] <= #1 (cnt == 8'h11);          // Slot 0 Latch Enable

always @(posedge clk)

always @(posedge clk)

        out_le[1] <= #1 (cnt == 8'h25);         // Slot 1 Latch Enable

        out_le[1] <= #1 (cnt == 8'h25);         // Slot 1 Latch Enable

always @(posedge clk)

always @(posedge clk)

        out_le[2] <= #1 (cnt == 8'h39);         // Slot 2 Latch Enable

        out_le[2] <= #1 (cnt == 8'h39);         // Slot 2 Latch Enable

always @(posedge clk)

always @(posedge clk)

        out_le[3] <= #1 (cnt == 8'h4d);         // Slot 3 Latch Enable

        out_le[3] <= #1 (cnt == 8'h4d);         // Slot 3 Latch Enable

always @(posedge clk)

always @(posedge clk)

        out_le[4] <= #1 (cnt == 8'h61);         // Slot 4 Latch Enable

        out_le[4] <= #1 (cnt == 8'h61);         // Slot 4 Latch Enable

always @(posedge clk)

always @(posedge clk)

        out_le[5] <= #1 (cnt == 8'h89);         // Slot 6 Latch Enable

        out_le[5] <= #1 (cnt == 8'h89);         // Slot 6 Latch Enable

always @(posedge clk)

always @(posedge clk)

        in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid

        in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid

always @(posedge clk)

always @(posedge clk)

        in_valid[1] <= #1 (cnt > 8'h61);        // Input Slot 3 Valid

        in_valid[1] <= #1 (cnt > 8'h61);        // Input Slot 3 Valid

always @(posedge clk)

always @(posedge clk)

        in_valid[2] <= #1 (cnt > 8'h89);        // Input Slot 3 Valid

        in_valid[2] <= #1 (cnt > 8'h89);        // Input Slot 3 Valid

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Suspend Detect

// Suspend Detect

//

//

always @(posedge wclk)

always @(posedge wclk)

        bit_clk_r <= #1 clk;

        bit_clk_r <= #1 clk;

always @(posedge wclk)

always @(posedge wclk)

        bit_clk_r1 <= #1 bit_clk_r;

        bit_clk_r1 <= #1 bit_clk_r;

always @(posedge wclk)

always @(posedge wclk)

        bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);

        bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);

always @(posedge wclk)

always @(posedge wclk)

        suspended <= #1 to;

        suspended <= #1 to;

assign to = (to_cnt == `AC97_SUSP_DET);

assign to = (to_cnt == `AC97_SUSP_DET);

always @(posedge wclk or negedge rst)

always @(posedge wclk or negedge rst)

        if(!rst)                to_cnt <= #1 6'h0;

        if(!rst)                to_cnt <= #1 6'h0;

        else

        else

        if(bit_clk_e)           to_cnt <= #1 6'h0;

        if(bit_clk_e)           to_cnt <= #1 6'h0;

        else

        else

        if(!to)                 to_cnt <= #1 to_cnt + 6'h1;

        if(!to)                 to_cnt <= #1 to_cnt + 6'h1;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Resume Signaling

// Resume Signaling

//

//

always @(posedge wclk or negedge rst)

always @(posedge wclk or negedge rst)

        if(!rst)                        sync_resume <= #1 1'b0;

        if(!rst)                        sync_resume <= #1 1'b0;

        else

        else

        if(resume_done)                 sync_resume <= #1 1'b0;

        if(resume_done)                 sync_resume <= #1 1'b0;

        else

        else

        if(suspended & resume)          sync_resume <= #1 1'b1;

        if(suspended & resume)          sync_resume <= #1 1'b1;

assign resume_done = (res_cnt == `AC97_RES_SIG);

assign resume_done = (res_cnt == `AC97_RES_SIG);

always @(posedge wclk)

always @(posedge wclk)

        if(!sync_resume)        res_cnt <= #1 4'h0;

        if(!sync_resume)        res_cnt <= #1 4'h0;

        else

        else

        if(ps_ce)               res_cnt <= #1 res_cnt + 4'h1;

        if(ps_ce)               res_cnt <= #1 res_cnt + 4'h1;

endmodule

endmodule

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Diff between revs 17 and 20