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https://opencores.org/ocsvn/ac97/ac97/trunk
[/] [ac97/] [trunk/] [syn/] [bin/] [design_spec.dc] - Diff between revs 17 and 20
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Rev 20 |
###############################################################################
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###############################################################################
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# Design Specification
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# Design Specification
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# Author: Rudolf Usselmann
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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# rudi@asics.ws
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#
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#
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# Revision:
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# Revision:
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# 3/7/01 RU Initial Sript
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# 3/7/01 RU Initial Sript
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#
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###############################################################################
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###############################################################################
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# ==============================================
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# ==============================================
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# Setup Design Parameters
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# Setup Design Parameters
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set design_files {ac97_fifo_ctrl ac97_dma_req ac97_cra ac97_prc ac97_soc ac97_in_fifo ac97_rf ac97_sout ac97_dma_if ac97_int ac97_rst ac97_out_fifo ac97_sin ac97_wb_if ac97_top}
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set design_files {ac97_fifo_ctrl ac97_dma_req ac97_cra ac97_prc ac97_soc ac97_in_fifo ac97_rf ac97_sout ac97_dma_if ac97_int ac97_rst ac97_out_fifo ac97_sin ac97_wb_if ac97_top}
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set design_name ac97_top
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set design_name ac97_top
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set active_design ac97_top
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set active_design ac97_top
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# Next Statement defines all clocks and resets in the design
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# Next Statement defines all clocks and resets in the design
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set special_net {rst clk bit_clk}
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set special_net {rst clk bit_clk}
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set hdl_src_dir ../../rtl/verilog/
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set hdl_src_dir ../../rtl/verilog/
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