--
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--
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-- confppa.vhd
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-- confppa.vhd
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--
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--
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-- configuration ACEX from ROM in PPA mode
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-- configuration ACEX from ROM in PPA mode
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-- Pinout for BB KFL board
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-- Pinout for BB KFL board
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--
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--
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-- resources on MAX7032
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-- resources on MAX7032
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--
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--
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-- 32 LCs !!!
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-- 32 LCs !!!
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--
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--
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-- timing for ACEX:
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-- timing for ACEX:
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-- nConfig low min 2 us
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-- nConfig low min 2 us
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-- nConfig high to nStatus high max 4 us
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-- nConfig high to nStatus high max 4 us
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-- nConfig high to nWS rising edge max 5 us
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-- nConfig high to nWS rising edge max 5 us
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-- nWS pulse width min 200 ns
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-- nWS pulse width min 200 ns
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-- nStatus high to first rising DCLK min 1 us
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-- nStatus high to first rising DCLK min 1 us
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-- DCLK clk max 33.3 MHz
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-- DCLK clk max 33.3 MHz
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--
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--
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-- for simpler config wait tbusy+trdy2ws+tws2b befor next byte
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-- for simpler config wait tbusy+trdy2ws+tws2b befor next byte
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-- 1.6 us + 50 ns + 50 ns
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-- 1.6 us + 50 ns + 50 ns
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--
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--
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--
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--
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-- todo:
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-- todo:
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--
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--
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--
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--
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-- 2001-10-26 creation
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-- 2001-10-26 creation
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-- 2002-01-11 changed clock div to 32 for 7.3 MHz
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-- 2002-01-11 changed clock div to 32 for 7.3 MHz
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--
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--
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library ieee ;
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity confppa is
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entity confppa is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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nreset : in std_logic;
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nreset : in std_logic;
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a : out std_logic_vector(16 downto 0); -- FLASH adr
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a : out std_logic_vector(16 downto 0); -- FLASH adr
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noe_in : in std_logic; -- input from ACEX
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noe_in : in std_logic; -- input from ACEX
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nce_in : in std_logic; -- input from ACEX
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nce_in : in std_logic; -- input from ACEX
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noe : out std_logic; -- output to FLASH
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noe : out std_logic; -- output to FLASH
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nce : out std_logic; -- output to FLASH
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nce : out std_logic; -- output to FLASH
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d0in : in std_logic; -- D0 from FLASH
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d0in : in std_logic; -- D0 from FLASH
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d0out : out std_logic; -- reseved DATA0 to ACEX
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d0out : out std_logic; -- reseved DATA0 to ACEX
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nconf : out std_logic; -- ACEX nConfig
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nconf : out std_logic; -- ACEX nConfig
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nstatus : in std_logic; -- ACEX nStatus -- not used
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nstatus : in std_logic; -- ACEX nStatus -- not used
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conf_done : in std_logic; -- ACEX conf_done
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conf_done : in std_logic; -- ACEX conf_done
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csacx : out std_logic; -- ACEX CS ???
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csacx : out std_logic; -- ACEX CS ???
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nws : out std_logic; -- ACEX nWS
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nws : out std_logic; -- ACEX nWS
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nbsy : in std_logic; -- ACEX RDYnBSY -- not used
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nbsy : in std_logic; -- ACEX RDYnBSY -- not used
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resacx : out std_logic -- ACEX reset line
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resacx : out std_logic -- ACEX reset line
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);
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);
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end confppa ;
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end confppa ;
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architecture rtl of confppa is
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architecture rtl of confppa is
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signal slowclk : std_logic;
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signal slowclk : std_logic;
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signal div : std_logic_vector(6 downto 0);
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signal div : std_logic_vector(6 downto 0);
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signal state : std_logic_vector(4 downto 0);
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signal state : std_logic_vector(4 downto 0);
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signal ar : std_logic_vector(16 downto 0); -- adress register
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signal ar : std_logic_vector(16 downto 0); -- adress register
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--
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--
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-- special encoding to use as output!
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-- special encoding to use as output!
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--
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--
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constant start :std_logic_vector(4 downto 0) := "00110";
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constant start :std_logic_vector(4 downto 0) := "00110";
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constant wait_nCfg_2us :std_logic_vector(4 downto 0) := "10110";
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constant wait_nCfg_2us :std_logic_vector(4 downto 0) := "10110";
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constant wait_5us :std_logic_vector(4 downto 0) := "01111";
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constant wait_5us :std_logic_vector(4 downto 0) := "01111";
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constant wslow :std_logic_vector(4 downto 0) := "01101";
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constant wslow :std_logic_vector(4 downto 0) := "01101";
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constant wshigh :std_logic_vector(4 downto 0) := "11111";
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constant wshigh :std_logic_vector(4 downto 0) := "11111";
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constant resacex :std_logic_vector(4 downto 0) := "00111";
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constant resacex :std_logic_vector(4 downto 0) := "00111";
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constant running :std_logic_vector(4 downto 0) := "00011";
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constant running :std_logic_vector(4 downto 0) := "00011";
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begin
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begin
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--
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--
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-- divide clock to max 250 kHz (4us for nstatus)
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-- divide clock to max 250 kHz (4us for nstatus)
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--
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--
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process(clk, nreset)
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process(clk, nreset)
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begin
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begin
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if nreset='0' then
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if nreset='0' then
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div <= (others => '0');
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div <= (others => '0');
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else
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else
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if rising_edge(clk) then
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if rising_edge(clk) then
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div <= div + 1;
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div <= div + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- slowclk <= div(6); for 24 MHz
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-- slowclk <= div(6); for 24 MHz
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slowclk <= div(4); -- for 7.3 MHz
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slowclk <= div(4); -- for 7.3 MHz
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nconf <= state(0);
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nconf <= state(0);
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nws <= state(1);
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nws <= state(1);
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resacx <= state(2);
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resacx <= state(2);
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csacx <= state(3);
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csacx <= state(3);
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--
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--
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-- state machine
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-- state machine
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--
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--
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process(slowclk, nreset)
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process(slowclk, nreset)
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begin
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begin
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if nreset='0' then
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if nreset='0' then
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state <= start;
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state <= start;
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ar <= (others => '0');
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ar <= (others => '0');
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else
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else
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if rising_edge(slowclk) then
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if rising_edge(slowclk) then
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case state is
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case state is
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when start =>
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when start =>
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ar <= (others => '0');
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ar <= (others => '0');
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state <= wait_nCfg_2us;
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state <= wait_nCfg_2us;
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when wait_nCfg_2us =>
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when wait_nCfg_2us =>
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state <= wait_5us;
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state <= wait_5us;
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when wait_5us =>
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when wait_5us =>
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state <= wslow;
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state <= wslow;
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when wslow =>
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when wslow =>
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state <= wshigh;
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state <= wshigh;
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when wshigh =>
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when wshigh =>
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ar <= ar + 1;
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ar <= ar + 1;
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if conf_done='1' then
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if conf_done='1' then
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state <= resacex;
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state <= resacex;
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else
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else
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state <= wslow;
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state <= wslow;
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end if;
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end if;
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when resacex =>
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when resacex =>
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state <= running;
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state <= running;
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when running =>
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when running =>
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process (state(2), ar, d0in, noe_in, nce_in)
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process (state(2), ar, d0in, noe_in, nce_in)
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begin
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begin
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|
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if state(2)='0' then -- is resacx
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if state(2)='0' then -- is resacx
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a <= (others => 'Z');
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a <= (others => 'Z');
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d0out <= '1';
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d0out <= '1';
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noe <= noe_in;
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noe <= noe_in;
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nce <= nce_in;
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nce <= nce_in;
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else
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else
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a <= ar;
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a <= ar;
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d0out <= d0in;
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d0out <= d0in;
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noe <= '0';
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noe <= '0';
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nce <= '0';
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nce <= '0';
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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