-- Copyright (C) 2004-2005 Digish Pandya <digish.pandya@gmail.com>
|
-- Copyright (C) 2004-2005 Digish Pandya <digish.pandya@gmail.com>
|
|
|
-- This program is free software; you can redistribute it and/or modify
|
-- This program is free software; you can redistribute it and/or modify
|
-- it under the terms of the GNU General Public License as published by
|
-- it under the terms of the GNU General Public License as published by
|
-- the Free Software Foundation; either version 2 of the License, or
|
-- the Free Software Foundation; either version 2 of the License, or
|
-- (at your option) any later version.
|
-- (at your option) any later version.
|
--
|
--
|
-- This program is distributed in the hope that it will be useful,
|
-- This program is distributed in the hope that it will be useful,
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
--
|
--
|
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
-- along with this program; if not, write to the Free Software
|
-- along with this program; if not, write to the Free Software
|
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
|
|
|
-- A.6 tf_lms.vhd
|
-- A.6 tf_lms.vhd
|
-- Adaptive equalizer routine
|
-- Adaptive equalizer routine
|
--
|
--
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_SIGNED.ALL;
|
use IEEE.STD_LOGIC_SIGNED.ALL;
|
|
|
|
|
entity tf_lms is
|
entity tf_lms is
|
Port (
|
Port (
|
xin : in std_logic_vector(7 downto 0); -- data input
|
xin : in std_logic_vector(7 downto 0); -- data input
|
dxin : in std_logic_vector(7 downto 0); -- desired response input
|
dxin : in std_logic_vector(7 downto 0); -- desired response input
|
clock : in std_logic; -- clock
|
clock : in std_logic; -- clock
|
err:out std_logic_vector(7 downto 0); -- error output
|
err:out std_logic_vector(7 downto 0); -- error output
|
yout : out std_logic_vector(7 downto 0); -- output data
|
yout : out std_logic_vector(7 downto 0); -- output data
|
adapt_en: in std_logic -- enable adaption
|
adapt_en: in std_logic -- enable adaption
|
);
|
);
|
end tf_lms;
|
end tf_lms;
|
|
|
architecture structural of tf_lms is
|
architecture structural of tf_lms is
|
|
|
-- filter core
|
-- filter core
|
component core_filt
|
component core_filt
|
Port (
|
Port (
|
x_in : in std_logic_vector(7 downto 0);
|
x_in : in std_logic_vector(7 downto 0);
|
x_N_in : in std_logic_vector(7 downto 0);
|
x_N_in : in std_logic_vector(7 downto 0);
|
ue_in : in std_logic_vector(7 downto 0);
|
ue_in : in std_logic_vector(7 downto 0);
|
clock : in std_logic;
|
clock : in std_logic;
|
y_out : out std_logic_vector(7 downto 0));
|
y_out : out std_logic_vector(7 downto 0));
|
end component ;
|
end component ;
|
|
|
-- shift regesters
|
-- shift regesters
|
component shift_21d
|
component shift_21d
|
Port ( xin : in std_logic_vector(7 downto 0);
|
Port ( xin : in std_logic_vector(7 downto 0);
|
x_N_out : out std_logic_vector(7 downto 0);
|
x_N_out : out std_logic_vector(7 downto 0);
|
x_1_out : out std_logic_vector(7 downto 0);
|
x_1_out : out std_logic_vector(7 downto 0);
|
clock : in std_logic);
|
clock : in std_logic);
|
end component;
|
end component;
|
|
|
component shift_20d
|
component shift_20d
|
Port ( xin : in std_logic_vector(7 downto 0);
|
Port ( xin : in std_logic_vector(7 downto 0);
|
xout : out std_logic_vector(7 downto 0);
|
xout : out std_logic_vector(7 downto 0);
|
clock : in std_logic);
|
clock : in std_logic);
|
end component;
|
end component;
|
|
|
signal e,e_t,y_o,x_1,x_N:std_logic_vector(7 downto 0);
|
signal e,e_t,y_o,x_1,x_N:std_logic_vector(7 downto 0);
|
|
|
begin
|
begin
|
|
|
-- if Adaption is not enabled then ERROR signal is ZERO
|
-- if Adaption is not enabled then ERROR signal is ZERO
|
with adapt_en select
|
with adapt_en select
|
e <= y_o - e_t when '1',
|
e <= y_o - e_t when '1',
|
"00000000" when others;
|
"00000000" when others;
|
|
|
err <= e;
|
err <= e;
|
|
|
shift_1:shift_20d
|
shift_1:shift_20d
|
port map (
|
port map (
|
xin => dxin,
|
xin => dxin,
|
xout => e_t,
|
xout => e_t,
|
clock => clock
|
clock => clock
|
);
|
);
|
|
|
shift_2:shift_21d
|
shift_2:shift_21d
|
port map (
|
port map (
|
xin => xin,
|
xin => xin,
|
x_N_out =>x_N,
|
x_N_out =>x_N,
|
x_1_out =>x_1,
|
x_1_out =>x_1,
|
clock => clock
|
clock => clock
|
);
|
);
|
|
|
cflt: core_filt
|
cflt: core_filt
|
port map (
|
port map (
|
x_in => x_1,
|
x_in => x_1,
|
x_N_in => x_N,
|
x_N_in => x_N,
|
ue_in => e,
|
ue_in => e,
|
y_out => y_o,
|
y_out => y_o,
|
clock => clock
|
clock => clock
|
);
|
);
|
|
|
yout <= y_o;
|
yout <= y_o;
|
end structural;
|
end structural;
|
|
|
