//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// adbg_top.v ////
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//// adbg_top.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// Copyright (C) 2008 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
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//// ////
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//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
|
// CVS Revision History
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//
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//
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// $Log: adbg_top.v,v $
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// $Log: adbg_top.v,v $
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/22 20:28:32 Nathan
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// Revision 1.1 2008/07/22 20:28:32 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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//
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// Revision 1.10 2008/07/11 08:13:29 Nathan
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// Revision 1.10 2008/07/11 08:13:29 Nathan
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// Latch opcode on posedge, like other signals. This fixes a problem
|
// Latch opcode on posedge, like other signals. This fixes a problem
|
// when the module is used with a Xilinx BSCAN TAP. Added signals to
|
// when the module is used with a Xilinx BSCAN TAP. Added signals to
|
// allow modules to inhibit latching of a new active module by the top
|
// allow modules to inhibit latching of a new active module by the top
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// module. This allows the sub-modules to force the top level module
|
// module. This allows the sub-modules to force the top level module
|
// to ignore the command present in the input shift register after e.g.
|
// to ignore the command present in the input shift register after e.g.
|
// a burst read.
|
// a burst read.
|
//
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//
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// Revision 1.7 2008/06/30 20:09:20 Nathan
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// Revision 1.7 2008/06/30 20:09:20 Nathan
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// Removed code to select top-level module as active (it served no
|
// Removed code to select top-level module as active (it served no
|
// purpose). Re-numbered modules, requiring changes to testbench and
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// purpose). Re-numbered modules, requiring changes to testbench and
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// software driver.
|
// software driver.
|
//
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//
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|
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`include "adbg_defines.v"
|
`include "adbg_defines.v"
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|
|
|
|
// Top module
|
// Top module
|
module adbg_top(
|
module adbg_top(
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// JTAG signals
|
// JTAG signals
|
tck_i,
|
tck_i,
|
tdi_i,
|
tdi_i,
|
tdo_o,
|
tdo_o,
|
rst_i,
|
rst_i,
|
|
|
|
|
// TAP states
|
// TAP states
|
shift_dr_i,
|
shift_dr_i,
|
pause_dr_i,
|
pause_dr_i,
|
update_dr_i,
|
update_dr_i,
|
capture_dr_i,
|
capture_dr_i,
|
|
|
// Instructions
|
// Instructions
|
debug_select_i
|
debug_select_i
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// WISHBONE common signals
|
// WISHBONE common signals
|
,
|
,
|
wb_clk_i,
|
wb_clk_i,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
wb_adr_o,
|
wb_adr_o,
|
wb_dat_o,
|
wb_dat_o,
|
wb_dat_i,
|
wb_dat_i,
|
wb_cyc_o,
|
wb_cyc_o,
|
wb_stb_o,
|
wb_stb_o,
|
wb_sel_o,
|
wb_sel_o,
|
wb_we_o,
|
wb_we_o,
|
wb_ack_i,
|
wb_ack_i,
|
wb_cab_o,
|
wb_cab_o,
|
wb_err_i,
|
wb_err_i,
|
wb_cti_o,
|
wb_cti_o,
|
wb_bte_o
|
wb_bte_o
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
// CPU signals
|
// CPU signals
|
,
|
,
|
cpu0_clk_i,
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cpu0_clk_i,
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cpu0_addr_o,
|
cpu0_addr_o,
|
cpu0_data_i,
|
cpu0_data_i,
|
cpu0_data_o,
|
cpu0_data_o,
|
cpu0_bp_i,
|
cpu0_bp_i,
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cpu0_stall_o,
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cpu0_stall_o,
|
cpu0_stb_o,
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cpu0_stb_o,
|
cpu0_we_o,
|
cpu0_we_o,
|
cpu0_ack_i,
|
cpu0_ack_i,
|
cpu0_rst_o
|
cpu0_rst_o
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
`ifdef DBG_CPU1_SUPPORTED
|
// CPU signals
|
// CPU signals
|
,
|
,
|
cpu1_clk_i,
|
cpu1_clk_i,
|
cpu1_addr_o,
|
cpu1_addr_o,
|
cpu1_data_i,
|
cpu1_data_i,
|
cpu1_data_o,
|
cpu1_data_o,
|
cpu1_bp_i,
|
cpu1_bp_i,
|
cpu1_stall_o,
|
cpu1_stall_o,
|
cpu1_stb_o,
|
cpu1_stb_o,
|
cpu1_we_o,
|
cpu1_we_o,
|
cpu1_ack_i,
|
cpu1_ack_i,
|
cpu1_rst_o
|
cpu1_rst_o
|
`endif
|
`endif
|
|
|
);
|
);
|
|
|
|
|
// JTAG signals
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// JTAG signals
|
input tck_i;
|
input tck_i;
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input tdi_i;
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input tdi_i;
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output tdo_o;
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output tdo_o;
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input rst_i;
|
input rst_i;
|
|
|
// TAP states
|
// TAP states
|
input shift_dr_i;
|
input shift_dr_i;
|
input pause_dr_i;
|
input pause_dr_i;
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input update_dr_i;
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input update_dr_i;
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input capture_dr_i;
|
input capture_dr_i;
|
|
|
// Module select from TAP
|
// Module select from TAP
|
input debug_select_i;
|
input debug_select_i;
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
input wb_clk_i;
|
input wb_clk_i;
|
output [31:0] wb_adr_o;
|
output [31:0] wb_adr_o;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
input [31:0] wb_dat_i;
|
input [31:0] wb_dat_i;
|
output wb_cyc_o;
|
output wb_cyc_o;
|
output wb_stb_o;
|
output wb_stb_o;
|
output [3:0] wb_sel_o;
|
output [3:0] wb_sel_o;
|
output wb_we_o;
|
output wb_we_o;
|
input wb_ack_i;
|
input wb_ack_i;
|
output wb_cab_o;
|
output wb_cab_o;
|
input wb_err_i;
|
input wb_err_i;
|
output [2:0] wb_cti_o;
|
output [2:0] wb_cti_o;
|
output [1:0] wb_bte_o;
|
output [1:0] wb_bte_o;
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
// CPU signals
|
// CPU signals
|
input cpu0_clk_i;
|
input cpu0_clk_i;
|
output [31:0] cpu0_addr_o;
|
output [31:0] cpu0_addr_o;
|
input [31:0] cpu0_data_i;
|
input [31:0] cpu0_data_i;
|
output [31:0] cpu0_data_o;
|
output [31:0] cpu0_data_o;
|
input cpu0_bp_i;
|
input cpu0_bp_i;
|
output cpu0_stall_o;
|
output cpu0_stall_o;
|
output cpu0_stb_o;
|
output cpu0_stb_o;
|
output cpu0_we_o;
|
output cpu0_we_o;
|
input cpu0_ack_i;
|
input cpu0_ack_i;
|
output cpu0_rst_o;
|
output cpu0_rst_o;
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
`ifdef DBG_CPU1_SUPPORTED
|
input cpu1_clk_i;
|
input cpu1_clk_i;
|
output [31:0] cpu1_addr_o;
|
output [31:0] cpu1_addr_o;
|
input [31:0] cpu1_data_i;
|
input [31:0] cpu1_data_i;
|
output [31:0] cpu1_data_o;
|
output [31:0] cpu1_data_o;
|
input cpu1_bp_i;
|
input cpu1_bp_i;
|
output cpu1_stall_o;
|
output cpu1_stall_o;
|
output cpu1_stb_o;
|
output cpu1_stb_o;
|
output cpu1_we_o;
|
output cpu1_we_o;
|
input cpu1_ack_i;
|
input cpu1_ack_i;
|
output cpu1_rst_o;
|
output cpu1_rst_o;
|
`endif
|
`endif
|
|
|
|
|
reg tdo_o;
|
reg tdo_o;
|
wire tdo_wb;
|
wire tdo_wb;
|
wire tdo_cpu0;
|
wire tdo_cpu0;
|
wire tdo_cpu1;
|
wire tdo_cpu1;
|
|
|
|
|
// Registers
|
// Registers
|
reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
|
reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
|
//reg output_shift_reg; // Just 1 bit for status (valid module selected)
|
//reg output_shift_reg; // Just 1 bit for status (valid module selected)
|
reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
|
reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
|
|
|
|
|
// Control signals
|
// Control signals
|
wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection
|
wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection
|
wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
|
wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
|
reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
|
reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
|
wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID
|
wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID
|
wire [2:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
|
wire [2:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
|
|
|
///////////////////////////////////////
|
///////////////////////////////////////
|
// Combinatorial assignments
|
// Combinatorial assignments
|
|
|
assign select_cmd = input_shift_reg[52];
|
assign select_cmd = input_shift_reg[52];
|
assign module_id_in = input_shift_reg[51:50];
|
assign module_id_in = input_shift_reg[51:50];
|
|
|
//////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////
|
// Module select register and select signals
|
// Module select register and select signals
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
module_id_reg <= 2'b0;
|
module_id_reg <= 2'b0;
|
else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit) // Chain select
|
else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit) // Chain select
|
module_id_reg <= module_id_in;
|
module_id_reg <= module_id_in;
|
end
|
end
|
|
|
|
|
always @ (module_id_reg)
|
always @ (module_id_reg)
|
begin
|
begin
|
module_selects <= `DBG_TOP_MODULE_ID_LENGTH'h0;
|
module_selects <= `DBG_TOP_MODULE_ID_LENGTH'h0;
|
module_selects[module_id_reg] <= 1'b1;
|
module_selects[module_id_reg] <= 1'b1;
|
end
|
end
|
|
|
///////////////////////////////////////////////
|
///////////////////////////////////////////////
|
// Data input shift register
|
// Data input shift register
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
input_shift_reg <= 53'h0;
|
input_shift_reg <= 53'h0;
|
else if(debug_select_i && shift_dr_i)
|
else if(debug_select_i && shift_dr_i)
|
input_shift_reg <= {tdi_i, input_shift_reg[52:1]};
|
input_shift_reg <= {tdi_i, input_shift_reg[52:1]};
|
end
|
end
|
|
|
|
|
//////////////////////////////////////////////
|
//////////////////////////////////////////////
|
// Debug module instantiations
|
// Debug module instantiations
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// Connecting wishbone module
|
// Connecting wishbone module
|
adbg_wb_module i_dbg_wb (
|
adbg_wb_module i_dbg_wb (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.module_tdo_o (tdo_wb),
|
.module_tdo_o (tdo_wb),
|
.tdi_i (tdi_i),
|
.tdi_i (tdi_i),
|
|
|
// TAP states
|
// TAP states
|
.capture_dr_i (capture_dr_i),
|
.capture_dr_i (capture_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.update_dr_i (update_dr_i),
|
.update_dr_i (update_dr_i),
|
|
|
.data_register_i (input_shift_reg),
|
.data_register_i (input_shift_reg),
|
.module_select_i (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
|
.module_select_i (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
|
.rst_i (rst_i),
|
.rst_i (rst_i),
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
.wb_clk_i (wb_clk_i),
|
.wb_clk_i (wb_clk_i),
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
.wb_adr_o (wb_adr_o),
|
.wb_adr_o (wb_adr_o),
|
.wb_dat_o (wb_dat_o),
|
.wb_dat_o (wb_dat_o),
|
.wb_dat_i (wb_dat_i),
|
.wb_dat_i (wb_dat_i),
|
.wb_cyc_o (wb_cyc_o),
|
.wb_cyc_o (wb_cyc_o),
|
.wb_stb_o (wb_stb_o),
|
.wb_stb_o (wb_stb_o),
|
.wb_sel_o (wb_sel_o),
|
.wb_sel_o (wb_sel_o),
|
.wb_we_o (wb_we_o),
|
.wb_we_o (wb_we_o),
|
.wb_ack_i (wb_ack_i),
|
.wb_ack_i (wb_ack_i),
|
.wb_cab_o (wb_cab_o),
|
.wb_cab_o (wb_cab_o),
|
.wb_err_i (wb_err_i),
|
.wb_err_i (wb_err_i),
|
.wb_cti_o (wb_cti_o),
|
.wb_cti_o (wb_cti_o),
|
.wb_bte_o (wb_bte_o)
|
.wb_bte_o (wb_bte_o)
|
);
|
);
|
`else
|
`else
|
assign tdo_wb = 1'b0;
|
assign tdo_wb = 1'b0;
|
assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
|
assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
adbg_or1k_module i_dbg_cpu_or1k (
|
adbg_or1k_module i_dbg_cpu_or1k (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.module_tdo_o (tdo_cpu0),
|
.module_tdo_o (tdo_cpu0),
|
.tdi_i (tdi_i),
|
.tdi_i (tdi_i),
|
|
|
// TAP states
|
// TAP states
|
.capture_dr_i (capture_dr_i),
|
.capture_dr_i (capture_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.update_dr_i (update_dr_i),
|
.update_dr_i (update_dr_i),
|
|
|
.data_register_i (input_shift_reg),
|
.data_register_i (input_shift_reg),
|
.module_select_i (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
|
.module_select_i (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
|
.rst_i (rst_i),
|
.rst_i (rst_i),
|
|
|
// CPU signals
|
// CPU signals
|
.cpu_clk_i (cpu0_clk_i),
|
.cpu_clk_i (cpu0_clk_i),
|
.cpu_addr_o (cpu0_addr_o),
|
.cpu_addr_o (cpu0_addr_o),
|
.cpu_data_i (cpu0_data_i),
|
.cpu_data_i (cpu0_data_i),
|
.cpu_data_o (cpu0_data_o),
|
.cpu_data_o (cpu0_data_o),
|
.cpu_bp_i (cpu0_bp_i),
|
.cpu_bp_i (cpu0_bp_i),
|
.cpu_stall_o (cpu0_stall_o),
|
.cpu_stall_o (cpu0_stall_o),
|
.cpu_stb_o (cpu0_stb_o),
|
.cpu_stb_o (cpu0_stb_o),
|
.cpu_we_o (cpu0_we_o),
|
.cpu_we_o (cpu0_we_o),
|
.cpu_ack_i (cpu0_ack_i),
|
.cpu_ack_i (cpu0_ack_i),
|
.cpu_rst_o (cpu0_rst_o)
|
.cpu_rst_o (cpu0_rst_o)
|
);
|
);
|
`else
|
`else
|
assign tdo_cpu0 = 1'b0;
|
assign tdo_cpu0 = 1'b0;
|
assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
|
assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
|
`endif // DBG_CPU0_SUPPORTED
|
`endif // DBG_CPU0_SUPPORTED
|
|
|
|
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
`ifdef DBG_CPU1_SUPPORTED
|
// Connecting cpu module
|
// Connecting cpu module
|
adbg_or1k_module i_dbg_cpu_8051 (
|
adbg_or1k_module i_dbg_cpu_8051 (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.module_tdo_o (tdo_cpu1),
|
.module_tdo_o (tdo_cpu1),
|
.tdi_i (tdi_i),
|
.tdi_i (tdi_i),
|
|
|
// TAP states
|
// TAP states
|
.capture_dr_i (capture_dr_i),
|
.capture_dr_i (capture_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.update_dr_i (update_dr_i),
|
.update_dr_i (update_dr_i),
|
|
|
.data_register_i (input_shift_reg),
|
.data_register_i (input_shift_reg),
|
.module_select_i (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
|
.module_select_i (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
|
.top_inhibit_o (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
|
.rst_i (rst_i),
|
.rst_i (rst_i),
|
|
|
// CPU signals
|
// CPU signals
|
.cpu_clk_i (cpu1_clk_i),
|
.cpu_clk_i (cpu1_clk_i),
|
.cpu_addr_o (cpu1_addr_o),
|
.cpu_addr_o (cpu1_addr_o),
|
.cpu_data_i (cpu1_data_i),
|
.cpu_data_i (cpu1_data_i),
|
.cpu_data_o (cpu1_data_o),
|
.cpu_data_o (cpu1_data_o),
|
.cpu_bp_i (cpu1_bp_i),
|
.cpu_bp_i (cpu1_bp_i),
|
.cpu_stall_o (cpu1_stall_o),
|
.cpu_stall_o (cpu1_stall_o),
|
.cpu_stb_o (cpu1_stb_o),
|
.cpu_stb_o (cpu1_stb_o),
|
.cpu_we_o (cpu1_we_o),
|
.cpu_we_o (cpu1_we_o),
|
.cpu_ack_i (cpu1_ack_i),
|
.cpu_ack_i (cpu1_ack_i),
|
.cpu_rst_o (cpu1_rst_o)
|
.cpu_rst_o (cpu1_rst_o)
|
);
|
);
|
`else
|
`else
|
assign tdo_cpu1 = 1'b0;
|
assign tdo_cpu1 = 1'b0;
|
assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
|
assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
|
`endif
|
`endif
|
|
|
assign select_inhibit = |module_inhibit;
|
assign select_inhibit = |module_inhibit;
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
// TDO output MUX
|
// TDO output MUX
|
|
|
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1)
|
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1)
|
begin
|
begin
|
case (module_id_reg)
|
case (module_id_reg)
|
`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
|
`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
|
`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
|
`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
|
`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
|
`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
|
default: tdo_o <= 1'b0;
|
default: tdo_o <= 1'b0;
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|