//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// altera_virtual_jtag.vhd ////
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//// altera_virtual_jtag.vhd ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2003-2008 Authors ////
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//// Copyright (C) 2003-2008 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// //
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// //
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// This file is a wrapper for the Altera Virtual JTAG device. //
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// This file is a wrapper for the Altera Virtual JTAG device. //
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// It is designed to take the place of a separate TAP //
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// It is designed to take the place of a separate TAP //
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// controller in Altera systems, to allow a user to access a CPU //
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// controller in Altera systems, to allow a user to access a CPU //
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// debug module (such as that of the OR1200) through the FPGA's //
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// debug module (such as that of the OR1200) through the FPGA's //
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// dedicated JTAG / configuration port. //
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// dedicated JTAG / configuration port. //
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// //
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// //
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: altera_virtual_jtag.vhd,v $
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// $Log: altera_virtual_jtag.vhd,v $
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// Revision 1.3 2009/06/16 02:53:19 Nathan
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// Revision 1.3 2009/06/16 02:53:19 Nathan
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// Changed some signal names for better consistency between different hardware modules.
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// Changed some signal names for better consistency between different hardware modules.
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//
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//
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// Revision 1.2 2009/05/17 20:54:47 Nathan
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// Revision 1.2 2009/05/17 20:54:47 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/18 20:09:31 Nathan
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// Revision 1.1 2008/07/18 20:09:31 Nathan
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// Changed directory structure to match existing projects.
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// Changed directory structure to match existing projects.
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//
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//
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// Revision 1.2 2008/05/22 19:55:20 Nathan
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// Revision 1.2 2008/05/22 19:55:20 Nathan
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// Added added copyright, CVS log, and brief description.
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// Added added copyright, CVS log, and brief description.
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//
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//
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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LIBRARY altera_mf;
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USE altera_mf.all;
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USE altera_mf.all;
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ENTITY altera_virtual_jtag IS
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ENTITY altera_virtual_jtag IS
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PORT
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PORT
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(
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(
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tck_o : OUT STD_LOGIC;
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tck_o : OUT STD_LOGIC;
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debug_tdo_o : IN STD_LOGIC;
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debug_tdo_o : IN STD_LOGIC;
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tdi_o : OUT STD_LOGIC;
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tdi_o : OUT STD_LOGIC;
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test_logic_reset_o : OUT STD_LOGIC;
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test_logic_reset_o : OUT STD_LOGIC;
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run_test_idle_o : OUT STD_LOGIC;
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run_test_idle_o : OUT STD_LOGIC;
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shift_dr_o : OUT STD_LOGIC;
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shift_dr_o : OUT STD_LOGIC;
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capture_dr_o : OUT STD_LOGIC;
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capture_dr_o : OUT STD_LOGIC;
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pause_dr_o : OUT STD_LOGIC;
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pause_dr_o : OUT STD_LOGIC;
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update_dr_o : OUT STD_LOGIC;
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update_dr_o : OUT STD_LOGIC;
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debug_select_o : OUT STD_LOGIC
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debug_select_o : OUT STD_LOGIC
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);
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);
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END altera_virtual_jtag;
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END altera_virtual_jtag;
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ARCHITECTURE OC OF altera_virtual_jtag IS
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ARCHITECTURE OC OF altera_virtual_jtag IS
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CONSTANT CMD_DEBUG : STD_LOGIC_VECTOR (3 downto 0) := "1000";
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CONSTANT CMD_DEBUG : STD_LOGIC_VECTOR (3 downto 0) := "1000";
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SIGNAL ir_value : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL ir_value : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL exit1_dr : STD_LOGIC;
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SIGNAL exit1_dr : STD_LOGIC;
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SIGNAL exit2_dr : STD_LOGIC;
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SIGNAL exit2_dr : STD_LOGIC;
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SIGNAL capture_ir : STD_LOGIC;
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SIGNAL capture_ir : STD_LOGIC;
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SIGNAL update_ir : STD_LOGIC;
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SIGNAL update_ir : STD_LOGIC;
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COMPONENT sld_virtual_jtag
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COMPONENT sld_virtual_jtag
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GENERIC (
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GENERIC (
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sld_auto_instance_index : STRING;
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sld_auto_instance_index : STRING;
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sld_instance_index : NATURAL;
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sld_instance_index : NATURAL;
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sld_ir_width : NATURAL;
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sld_ir_width : NATURAL;
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sld_sim_action : STRING;
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sld_sim_action : STRING;
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sld_sim_n_scan : NATURAL;
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sld_sim_n_scan : NATURAL;
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sld_sim_total_length : NATURAL;
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sld_sim_total_length : NATURAL;
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lpm_type : STRING
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lpm_type : STRING
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);
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);
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PORT (
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PORT (
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tdi : OUT STD_LOGIC ;
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tdi : OUT STD_LOGIC ;
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jtag_state_rti : OUT STD_LOGIC ;
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jtag_state_rti : OUT STD_LOGIC ;
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jtag_state_e1dr : OUT STD_LOGIC ;
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jtag_state_e1dr : OUT STD_LOGIC ;
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jtag_state_e2dr : OUT STD_LOGIC ;
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jtag_state_e2dr : OUT STD_LOGIC ;
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tms : OUT STD_LOGIC ;
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tms : OUT STD_LOGIC ;
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jtag_state_pir : OUT STD_LOGIC ;
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jtag_state_pir : OUT STD_LOGIC ;
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jtag_state_tlr : OUT STD_LOGIC ;
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jtag_state_tlr : OUT STD_LOGIC ;
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tck : OUT STD_LOGIC ;
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tck : OUT STD_LOGIC ;
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jtag_state_sir : OUT STD_LOGIC ;
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jtag_state_sir : OUT STD_LOGIC ;
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ir_in : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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ir_in : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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virtual_state_cir : OUT STD_LOGIC ;
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virtual_state_cir : OUT STD_LOGIC ;
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virtual_state_pdr : OUT STD_LOGIC ;
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virtual_state_pdr : OUT STD_LOGIC ;
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ir_out : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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ir_out : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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virtual_state_uir : OUT STD_LOGIC ;
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virtual_state_uir : OUT STD_LOGIC ;
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jtag_state_cir : OUT STD_LOGIC ;
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jtag_state_cir : OUT STD_LOGIC ;
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jtag_state_uir : OUT STD_LOGIC ;
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jtag_state_uir : OUT STD_LOGIC ;
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jtag_state_pdr : OUT STD_LOGIC ;
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jtag_state_pdr : OUT STD_LOGIC ;
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tdo : IN STD_LOGIC ;
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tdo : IN STD_LOGIC ;
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jtag_state_sdrs : OUT STD_LOGIC ;
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jtag_state_sdrs : OUT STD_LOGIC ;
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virtual_state_sdr : OUT STD_LOGIC ;
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virtual_state_sdr : OUT STD_LOGIC ;
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virtual_state_cdr : OUT STD_LOGIC ;
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virtual_state_cdr : OUT STD_LOGIC ;
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jtag_state_sdr : OUT STD_LOGIC ;
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jtag_state_sdr : OUT STD_LOGIC ;
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jtag_state_cdr : OUT STD_LOGIC ;
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jtag_state_cdr : OUT STD_LOGIC ;
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virtual_state_udr : OUT STD_LOGIC ;
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virtual_state_udr : OUT STD_LOGIC ;
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jtag_state_udr : OUT STD_LOGIC ;
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jtag_state_udr : OUT STD_LOGIC ;
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jtag_state_sirs : OUT STD_LOGIC ;
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jtag_state_sirs : OUT STD_LOGIC ;
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jtag_state_e1ir : OUT STD_LOGIC ;
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jtag_state_e1ir : OUT STD_LOGIC ;
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jtag_state_e2ir : OUT STD_LOGIC ;
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jtag_state_e2ir : OUT STD_LOGIC ;
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virtual_state_e1dr : OUT STD_LOGIC ;
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virtual_state_e1dr : OUT STD_LOGIC ;
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virtual_state_e2dr : OUT STD_LOGIC
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virtual_state_e2dr : OUT STD_LOGIC
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);
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);
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END COMPONENT;
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END COMPONENT;
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BEGIN
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BEGIN
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sld_virtual_jtag_component : sld_virtual_jtag
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sld_virtual_jtag_component : sld_virtual_jtag
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GENERIC MAP (
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GENERIC MAP (
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sld_auto_instance_index => "YES",
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sld_auto_instance_index => "YES",
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sld_instance_index => 0,
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sld_instance_index => 0,
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sld_ir_width => 4,
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sld_ir_width => 4,
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sld_sim_action => "",
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sld_sim_action => "",
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sld_sim_n_scan => 0,
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sld_sim_n_scan => 0,
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sld_sim_total_length => 0,
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sld_sim_total_length => 0,
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lpm_type => "sld_virtual_jtag"
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lpm_type => "sld_virtual_jtag"
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)
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)
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PORT MAP (
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PORT MAP (
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ir_out => ir_value,
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ir_out => ir_value,
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tdo => debug_tdo_o,
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tdo => debug_tdo_o,
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tdi => tdi_o,
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tdi => tdi_o,
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jtag_state_rti => run_test_idle_o,
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jtag_state_rti => run_test_idle_o,
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tck => tck_o,
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tck => tck_o,
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ir_in => ir_value,
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ir_in => ir_value,
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jtag_state_tlr => test_logic_reset_o,
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jtag_state_tlr => test_logic_reset_o,
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virtual_state_cir => capture_ir,
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virtual_state_cir => capture_ir,
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virtual_state_pdr => pause_dr_o,
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virtual_state_pdr => pause_dr_o,
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virtual_state_uir => update_ir,
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virtual_state_uir => update_ir,
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virtual_state_sdr => shift_dr_o,
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virtual_state_sdr => shift_dr_o,
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virtual_state_cdr => capture_dr_o,
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virtual_state_cdr => capture_dr_o,
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virtual_state_udr => update_dr_o,
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virtual_state_udr => update_dr_o,
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virtual_state_e1dr => exit1_dr,
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virtual_state_e1dr => exit1_dr,
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virtual_state_e2dr => exit2_dr
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virtual_state_e2dr => exit2_dr
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);
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);
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debug_select_o <= '1' when (ir_value = CMD_DEBUG) else '0';
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debug_select_o <= '1' when (ir_value = CMD_DEBUG) else '0';
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END OC;
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END OC;
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