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#ifndef _ADV_DBG_COMMANDS_H_
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#ifndef _ADV_DBG_COMMANDS_H_
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#define _ADV_DBG_COMMANDS_H_
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#define _ADV_DBG_COMMANDS_H_
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// Definitions for the top-level debug unit. This really just consists
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// Definitions for the top-level debug unit. This really just consists
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// of a single register, used to select the active debug module ("chain").
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// of a single register, used to select the active debug module ("chain").
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#define DBG_MODULE_SELECT_REG_SIZE 2
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#define DBG_MODULE_SELECT_REG_SIZE 2
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#define DBG_MAX_MODULES 4 // used to size an array
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#define DBG_MAX_MODULES 4 // used to size an array
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#define DC_WISHBONE 0
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#define DC_WISHBONE 0
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#define DC_CPU0 1
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#define DC_CPU0 1
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#define DC_CPU1 2
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#define DC_CPU1 2
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// Polynomial for the CRC calculation
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// Polynomial for the CRC calculation
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// Yes, it's backwards. Yes, this is on purpose.
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// Yes, it's backwards. Yes, this is on purpose.
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// The hardware is designed this way to save on logic and routing,
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// The hardware is designed this way to save on logic and routing,
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// and it's really all the same to us here.
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// and it's really all the same to us here.
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#define ADBG_CRC_POLY 0xedb88320
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#define ADBG_CRC_POLY 0xedb88320
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// These are for the internal registers in the Wishbone module
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// These are for the internal registers in the Wishbone module
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// The first is the length of the index register,
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// The first is the length of the index register,
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// the indexes of the various registers are defined after that
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// the indexes of the various registers are defined after that
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#define DBG_WB_REG_SEL_LEN 1
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#define DBG_WB_REG_SEL_LEN 1
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#define DBG_WB_REG_ERROR 0
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#define DBG_WB_REG_ERROR 0
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// Opcode definitions for the Wishbone module
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// Opcode definitions for the Wishbone module
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#define DBG_WB_OPCODE_LEN 4
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#define DBG_WB_OPCODE_LEN 4
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#define DBG_WB_CMD_NOP 0x0
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#define DBG_WB_CMD_NOP 0x0
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#define DBG_WB_CMD_BWRITE8 0x1
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#define DBG_WB_CMD_BWRITE8 0x1
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#define DBG_WB_CMD_BWRITE16 0x2
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#define DBG_WB_CMD_BWRITE16 0x2
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#define DBG_WB_CMD_BWRITE32 0x3
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#define DBG_WB_CMD_BWRITE32 0x3
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#define DBG_WB_CMD_BREAD8 0x5
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#define DBG_WB_CMD_BREAD8 0x5
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#define DBG_WB_CMD_BREAD16 0x6
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#define DBG_WB_CMD_BREAD16 0x6
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#define DBG_WB_CMD_BREAD32 0x7
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#define DBG_WB_CMD_BREAD32 0x7
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#define DBG_WB_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_WB_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_WB_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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#define DBG_WB_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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// Internal register definitions for the CPU0 module
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// Internal register definitions for the CPU0 module
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#define DBG_CPU0_REG_SEL_LEN 1
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#define DBG_CPU0_REG_SEL_LEN 1
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#define DBG_CPU0_REG_STATUS 0
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#define DBG_CPU0_REG_STATUS 0
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// Opcode definitions for the first CPU module
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// Opcode definitions for the first CPU module
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#define DBG_CPU0_OPCODE_LEN 4
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#define DBG_CPU0_OPCODE_LEN 4
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#define DBG_CPU0_CMD_NOP 0x0
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#define DBG_CPU0_CMD_NOP 0x0
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#define DBG_CPU0_CMD_BWRITE32 0x3
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#define DBG_CPU0_CMD_BWRITE32 0x3
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#define DBG_CPU0_CMD_BREAD32 0x7
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#define DBG_CPU0_CMD_BREAD32 0x7
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#define DBG_CPU0_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_CPU0_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_CPU0_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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#define DBG_CPU0_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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// Internal register definitions for the CPU1 module
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// Internal register definitions for the CPU1 module
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#define DBG_CPU1_REG_SEL_LEN 1
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#define DBG_CPU1_REG_SEL_LEN 1
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#define DBG_CPU1_REG_STATUS 0
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#define DBG_CPU1_REG_STATUS 0
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// Opcode definitions for the second CPU module
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// Opcode definitions for the second CPU module
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#define DBG_CPU1_OPCODE_LEN 4
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#define DBG_CPU1_OPCODE_LEN 4
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#define DBG_CPU1_CMD_NOP 0x0
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#define DBG_CPU1_CMD_NOP 0x0
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#define DBG_CPU1_CMD_BWRITE32 0x3
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#define DBG_CPU1_CMD_BWRITE32 0x3
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#define DBG_CPU1_CMD_BREAD32 0x7
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#define DBG_CPU1_CMD_BREAD32 0x7
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#define DBG_CPU1_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_CPU1_CMD_IREG_WR 0x9 // This is both a select and a write
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#define DBG_CPU1_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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#define DBG_CPU1_CMD_IREG_SEL 0xd // There is no 'read', the current register is always read. Use a NOP to read.
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// API to do transactions on the advanced debug interface
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// API to do transactions on the advanced debug interface
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int adbg_select_module(int chain);
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int adbg_select_module(int chain);
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int adbg_select_ctrl_reg(unsigned long regidx);
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int adbg_select_ctrl_reg(unsigned long regidx);
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int adbg_ctrl_write(unsigned long regidx, uint32_t *cmd_data, int length_bits);
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int adbg_ctrl_write(unsigned long regidx, uint32_t *cmd_data, int length_bits);
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int adbg_ctrl_read(unsigned long regidx, uint32_t *data, int databits);
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int adbg_ctrl_read(unsigned long regidx, uint32_t *data, int databits);
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int adbg_burst_command(unsigned int opcode, unsigned long address, int length_words);
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int adbg_burst_command(unsigned int opcode, unsigned long address, int length_words);
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int adbg_wb_burst_read(int word_size_bytes, int word_count, unsigned long start_address, void *data);
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int adbg_wb_burst_read(int word_size_bytes, int word_count, unsigned long start_address, void *data);
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int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address);
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int adbg_wb_burst_write(void *data, int word_size_bytes, int word_count, unsigned long start_address);
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#endif
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#endif
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