//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// adv_dbg_tb.v ////
|
//// adv_dbg_tb.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Testbench for the SoC Advanced Debug Interface. ////
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//// Testbench for the SoC Advanced Debug Interface. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencored.org) ////
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//// Nathan Yawn (nathan.yawn@opencored.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// Copyright (C) 2008 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
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//// ////
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//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adv_dbg_tb.v,v $
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// $Log: adv_dbg_tb.v,v $
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// Revision 1.2 2009/05/17 20:54:55 Nathan
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// Revision 1.2 2009/05/17 20:54:55 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
|
//
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//
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// Revision 1.11 2008/07/08 18:53:47 Nathan
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// Revision 1.11 2008/07/08 18:53:47 Nathan
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// Fixed wrong include name.
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// Fixed wrong include name.
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//
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//
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// Revision 1.10 2008/06/30 20:09:19 Nathan
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// Revision 1.10 2008/06/30 20:09:19 Nathan
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// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
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// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
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//
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//
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`include "tap_defines.v"
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`include "tap_defines.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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`include "dbg_wb_defines.v"
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`include "dbg_wb_defines.v"
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`include "wb_model_defines.v"
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`include "wb_model_defines.v"
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|
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// Polynomial for the CRC calculation
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// Polynomial for the CRC calculation
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// Yes, it's backwards. Yes, this is on purpose.
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// Yes, it's backwards. Yes, this is on purpose.
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// To decrease logic + routing, we want to shift the CRC calculation
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// To decrease logic + routing, we want to shift the CRC calculation
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// in the same direction we use to shift the data out, LSB first.
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// in the same direction we use to shift the data out, LSB first.
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`define DBG_CRC_POLY 32'hedb88320
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`define DBG_CRC_POLY 32'hedb88320
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|
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// These are indicies into an array which hold values for the JTAG outputs
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// These are indicies into an array which hold values for the JTAG outputs
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`define JTAG_TMS 0
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`define JTAG_TMS 0
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`define JTAG_TCK 1
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`define JTAG_TCK 1
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`define JTAG_TDO 2
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`define JTAG_TDO 2
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|
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`define JTAG_TMS_bit 3'h1
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`define JTAG_TMS_bit 3'h1
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`define JTAG_TCK_bit 3'h2
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`define JTAG_TCK_bit 3'h2
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`define JTAG_TDO_bit 3'h4
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`define JTAG_TDO_bit 3'h4
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|
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`define wait_jtag_period #50
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`define wait_jtag_period #50
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module adv_debug_tb;
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module adv_debug_tb;
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// Connections to the JTAG TAP
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// Connections to the JTAG TAP
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reg jtag_tck_o;
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reg jtag_tck_o;
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reg jtag_tms_o;
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reg jtag_tms_o;
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reg jtag_tdo_o;
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reg jtag_tdo_o;
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wire jtag_tdi_i;
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wire jtag_tdi_i;
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|
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// Connections between TAP and debug module
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// Connections between TAP and debug module
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wire capture_dr;
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wire capture_dr;
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wire shift_dr;
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wire shift_dr;
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wire pause_dr;
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wire pause_dr;
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wire update_dr;
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wire update_dr;
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wire dbg_rst;
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wire dbg_rst;
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wire dbg_tdi;
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wire dbg_tdi;
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wire dbg_tdo;
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wire dbg_tdo;
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wire dbg_sel;
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wire dbg_sel;
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// Connections between the debug module and the wishbone
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// Connections between the debug module and the wishbone
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`ifdef DBG_WISHBONE_SUPPORTED
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`ifdef DBG_WISHBONE_SUPPORTED
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wire [31:0] wb_adr;
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wire [31:0] wb_adr;
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wire [31:0] wb_dat_m;
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wire [31:0] wb_dat_m;
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wire [31:0] wb_dat_s;
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wire [31:0] wb_dat_s;
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wire wb_cyc;
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wire wb_cyc;
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wire wb_stb;
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wire wb_stb;
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wire [3:0] wb_sel;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_we;
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wire wb_ack;
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wire wb_ack;
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wire wb_err;
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wire wb_err;
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reg wb_clk_i; // the wishbone clock
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reg wb_clk_i; // the wishbone clock
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reg wb_rst_i;
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reg wb_rst_i;
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`endif
|
`endif
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`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
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wire cpu0_clk;
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wire cpu0_clk;
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wire [31:0]cpu0_addr;
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wire [31:0]cpu0_addr;
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wire [31:0] cpu0_data_c;
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wire [31:0] cpu0_data_c;
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wire [31:0] cpu0_data_d;
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wire [31:0] cpu0_data_d;
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wire cpu0_bp;
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wire cpu0_bp;
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wire cpu0_stall;
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wire cpu0_stall;
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wire cpu0_stb;
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wire cpu0_stb;
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wire cpu0_we;
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wire cpu0_we;
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wire cpu0_ack;
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wire cpu0_ack;
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wire cpu0_rst;
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wire cpu0_rst;
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`endif
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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`ifdef DBG_CPU1_SUPPORTED
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reg cpu1_clk;
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reg cpu1_clk;
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wire [31:0]cpu1_addr;
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wire [31:0]cpu1_addr;
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wire [31:0] cpu1_data_c;
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wire [31:0] cpu1_data_c;
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wire [31:0] cpu1_data_d;
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wire [31:0] cpu1_data_d;
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wire cpu1_bp;
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wire cpu1_bp;
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wire cpu1_stall;
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wire cpu1_stall;
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wire cpu1_stb;
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wire cpu1_stb;
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wire cpu1_we;
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wire cpu1_we;
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wire cpu1_ack;
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wire cpu1_ack;
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wire cpu1_rst;
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wire cpu1_rst;
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`endif // `ifdef DBG_CPU1_SUPPORTED
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`endif // `ifdef DBG_CPU1_SUPPORTED
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|
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reg test_enabled;
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reg test_enabled;
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// Data which will be written to the WB interface
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// Data which will be written to the WB interface
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reg [31:0] static_data32 [0:15];
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reg [31:0] static_data32 [0:15];
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reg [15:0] static_data16 [0:15];
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reg [15:0] static_data16 [0:15];
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reg [7:0] static_data8 [0:15];
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reg [7:0] static_data8 [0:15];
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// Arrays to hold data read back from the WB interface, for comparison
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// Arrays to hold data read back from the WB interface, for comparison
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reg [31:0] input_data32 [0:15];
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reg [31:0] input_data32 [0:15];
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reg [15:0] input_data16 [0:15];
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reg [15:0] input_data16 [0:15];
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reg [7:0] input_data8 [0:15];
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reg [7:0] input_data8 [0:15];
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reg [32:0] err_data; // holds the contents of the error register from the various modules
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reg [32:0] err_data; // holds the contents of the error register from the various modules
|
|
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reg failed;
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reg failed;
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integer i;
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integer i;
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|
|
initial
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initial
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begin
|
begin
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jtag_tck_o = 1'b0;
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jtag_tck_o = 1'b0;
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jtag_tms_o = 1'b0;
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jtag_tms_o = 1'b0;
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jtag_tdo_o = 1'b0;
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jtag_tdo_o = 1'b0;
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end
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end
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// Provide the wishbone clock
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// Provide the wishbone clock
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`ifdef DBG_WISHBONE_SUPPORTED
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`ifdef DBG_WISHBONE_SUPPORTED
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initial
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initial
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begin
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begin
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wb_clk_i = 1'b0;
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wb_clk_i = 1'b0;
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forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
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forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
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end
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end
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`endif
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`endif
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// Provide the CPU0 clock
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// Provide the CPU0 clock
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//`ifdef DBG_CPU0_SUPPORTED
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//`ifdef DBG_CPU0_SUPPORTED
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//initial
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//initial
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//begin
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//begin
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//cpu0_clk = 1'b0;
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//cpu0_clk = 1'b0;
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//forever #6 cpu0_clk = ~cpu0_clk; // Odd frequency ratio to test the synchronization
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//forever #6 cpu0_clk = ~cpu0_clk; // Odd frequency ratio to test the synchronization
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//end
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//end
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//`endif
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//`endif
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// Start the test (and reset the wishbone)
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// Start the test (and reset the wishbone)
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initial
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initial
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begin
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begin
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test_enabled = 1'b0;
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test_enabled = 1'b0;
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wb_rst_i = 1'b0;
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wb_rst_i = 1'b0;
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#100;
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#100;
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wb_rst_i = 1'b1;
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wb_rst_i = 1'b1;
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#100;
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#100;
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wb_rst_i = 1'b0;
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wb_rst_i = 1'b0;
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// Init the memory
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// Init the memory
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initialize_memory(32'h0,32'h16);
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initialize_memory(32'h0,32'h16);
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// Init the WB model
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// Init the WB model
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i_wb.cycle_response(`ACK_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
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i_wb.cycle_response(`ACK_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
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#1 test_enabled<=#1 1'b1;
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#1 test_enabled<=#1 1'b1;
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end
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end
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// This is the main test procedure
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// This is the main test procedure
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always @ (posedge test_enabled)
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always @ (posedge test_enabled)
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begin
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begin
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$display("Starting advanced debug test");
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$display("Starting advanced debug test");
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reset_jtag;
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reset_jtag;
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#1000;
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#1000;
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check_idcode;
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check_idcode;
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#1000;
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#1000;
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// Select the debug module in the IR
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// Select the debug module in the IR
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set_ir(`DEBUG);
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set_ir(`DEBUG);
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#1000;
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#1000;
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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// Test CPU0 unit
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// Test CPU0 unit
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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`ifdef DBG_CPU0_SUPPORTED
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`ifdef DBG_CPU0_SUPPORTED
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// Select the CPU0 unit in the debug module
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// Select the CPU0 unit in the debug module
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#1000;
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#1000;
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$display("Selecting CPU0 module at time %t", $time);
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$display("Selecting CPU0 module at time %t", $time);
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select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
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select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
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// Test reset, stall bits
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// Test reset, stall bits
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#1000;
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#1000;
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$display("Testing CPU0 intreg select at time %t", $time);
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$display("Testing CPU0 intreg select at time %t", $time);
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select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
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select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
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#1000;
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#1000;
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select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
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select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
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#1000;
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#1000;
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// Read the stall and reset bits
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// Read the stall and reset bits
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$display("Testing reset and stall bits at time %t", $time);
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$display("Testing reset and stall bits at time %t", $time);
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read_module_internal_register(8'd2, err_data); // We assume the register is already selected
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read_module_internal_register(8'd2, err_data); // We assume the register is already selected
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$display("Reset and stall bits are %x", err_data);
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$display("Reset and stall bits are %x", err_data);
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#1000;
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#1000;
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// Set rst/stall bits
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// Set rst/stall bits
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$display("Setting reset and stall bits at time %t", $time);
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$display("Setting reset and stall bits at time %t", $time);
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write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2); // idx, idxlen, data, datalen
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write_module_internal_register(32'h0, 8'h1, 32'h3, 8'h2); // idx, idxlen, data, datalen
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#1000;
|
#1000;
|
|
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// Read the bits again
|
// Read the bits again
|
$display("Testing reset and stall bits again at time %t", $time);
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$display("Testing reset and stall bits again at time %t", $time);
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read_module_internal_register(8'd2, err_data); // We assume the register is already selected
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read_module_internal_register(8'd2, err_data); // We assume the register is already selected
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$display("Reset and stall bits are %x", err_data);
|
$display("Reset and stall bits are %x", err_data);
|
#1000;
|
#1000;
|
|
|
// Clear the bits
|
// Clear the bits
|
$display("Clearing reset and stall bits at time %t", $time);
|
$display("Clearing reset and stall bits at time %t", $time);
|
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
|
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
|
#1000;
|
#1000;
|
|
|
// Read the bits again
|
// Read the bits again
|
$display("Testing reset and stall bits again at time %t", $time);
|
$display("Testing reset and stall bits again at time %t", $time);
|
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
|
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
|
$display("Reset and stall bits are %x", err_data);
|
$display("Reset and stall bits are %x", err_data);
|
#1000;
|
#1000;
|
|
|
// Behavioral CPU model must be stalled in order to do SPR access
|
// Behavioral CPU model must be stalled in order to do SPR access
|
//$display("Setting reset and stall bits at time %t", $time);
|
//$display("Setting reset and stall bits at time %t", $time);
|
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
|
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
|
#1000;
|
#1000;
|
|
|
// Test SPR bus access
|
// Test SPR bus access
|
$display("Testing CPU0 32-bit burst write at time %t", $time);
|
$display("Testing CPU0 32-bit burst write at time %t", $time);
|
do_module_burst_write(3'h4, 16'd16, 32'h10); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h4, 16'd16, 32'h10); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
$display("Testing CPU0 32-bit burst read at time %t", $time);
|
$display("Testing CPU0 32-bit burst read at time %t", $time);
|
do_module_burst_read(3'h4, 16'd16, 32'h0);
|
do_module_burst_read(3'h4, 16'd16, 32'h0);
|
#1000;
|
#1000;
|
|
|
`endif
|
`endif
|
|
|
|
|
///////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////
|
// Test the Wishbone unit
|
// Test the Wishbone unit
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// Select the WB unit in the debug module
|
// Select the WB unit in the debug module
|
#1000;
|
#1000;
|
$display("Selecting Wishbone module at time %t", $time);
|
$display("Selecting Wishbone module at time %t", $time);
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
|
|
/*
|
/*
|
// Test error conditions
|
// Test error conditions
|
#1000;
|
#1000;
|
$display("Testing error (size 0 WB burst write) at time %t", $time);
|
$display("Testing error (size 0 WB burst write) at time %t", $time);
|
do_module_burst_write(3'h1, 16'h0, 32'h0); // 0-word write = error, ignored
|
do_module_burst_write(3'h1, 16'h0, 32'h0); // 0-word write = error, ignored
|
#1000;
|
#1000;
|
$display("Testing error (size 0 WB burst read) at time %t", $time);
|
$display("Testing error (size 0 WB burst read) at time %t", $time);
|
do_module_burst_read(3'h1, 16'h0, 32'h0); // 0-word read = error, ignored
|
do_module_burst_read(3'h1, 16'h0, 32'h0); // 0-word read = error, ignored
|
|
|
// Test NOP (a zero in the MSB, then a NOP opcode)
|
// Test NOP (a zero in the MSB, then a NOP opcode)
|
#1000;
|
#1000;
|
$display("Testing NOP at time %t", $time);
|
$display("Testing NOP at time %t", $time);
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream(5'h0, 8'h5, 1); // write data, exit_1
|
jtag_write_stream(5'h0, 8'h5, 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
#1000;
|
#1000;
|
*/
|
*/
|
|
|
#1000;
|
#1000;
|
$display("Testing WB intreg select at time %t", $time);
|
$display("Testing WB intreg select at time %t", $time);
|
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
|
select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
|
#1000;
|
#1000;
|
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
|
select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
|
#1000;
|
#1000;
|
|
|
// Reset the error bit
|
// Reset the error bit
|
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
|
write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
|
#1000;
|
#1000;
|
|
|
// Read the error bit
|
// Read the error bit
|
read_module_internal_register(8'd33, err_data); // We assume the register is already selected
|
read_module_internal_register(8'd33, err_data); // We assume the register is already selected
|
#1000;
|
#1000;
|
|
|
|
|
/////////////////////////////////
|
/////////////////////////////////
|
// Test 8-bit WB access
|
// Test 8-bit WB access
|
failed = 0;
|
failed = 0;
|
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
|
$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
|
do_module_burst_write(3'h1, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h1, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
$display("Testing WB 8-bit burst read at time %t", $time);
|
$display("Testing WB 8-bit burst read at time %t", $time);
|
do_module_burst_read(3'h1, 16'd16, 32'h0);
|
do_module_burst_read(3'h1, 16'd16, 32'h0);
|
#1000;
|
#1000;
|
for(i = 0; i < 16; i = i+1) begin
|
for(i = 0; i < 16; i = i+1) begin
|
if(static_data8[i] != input_data8[i]) begin
|
if(static_data8[i] != input_data8[i]) begin
|
failed = 1;
|
failed = 1;
|
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
|
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
|
end
|
end
|
end
|
end
|
if(!failed) $display("8-bit read/write OK!");
|
if(!failed) $display("8-bit read/write OK!");
|
|
|
/* try it unaligned
|
/* try it unaligned
|
do_module_burst_write(3'h1, 16'd5, 32'h3); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h1, 16'd5, 32'h3); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
do_module_burst_read(3'h1, 16'd4, 32'h4);
|
do_module_burst_read(3'h1, 16'd4, 32'h4);
|
#1000;
|
#1000;
|
*/
|
*/
|
|
|
/////////////////////////////////
|
/////////////////////////////////
|
// Test 16-bit WB access
|
// Test 16-bit WB access
|
failed = 0;
|
failed = 0;
|
$display("Testing WB 16-bit burst write at time %t", $time);
|
$display("Testing WB 16-bit burst write at time %t", $time);
|
do_module_burst_write(3'h2, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h2, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
$display("Testing WB 16-bit burst read at time %t", $time);
|
$display("Testing WB 16-bit burst read at time %t", $time);
|
do_module_burst_read(3'h2, 16'd16, 32'h0);
|
do_module_burst_read(3'h2, 16'd16, 32'h0);
|
#1000;
|
#1000;
|
for(i = 0; i < 16; i = i+1) begin
|
for(i = 0; i < 16; i = i+1) begin
|
if(static_data16[i] != input_data16[i]) begin
|
if(static_data16[i] != input_data16[i]) begin
|
failed = 1;
|
failed = 1;
|
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
|
$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
|
end
|
end
|
end
|
end
|
if(!failed) $display("16-bit read/write OK!");
|
if(!failed) $display("16-bit read/write OK!");
|
|
|
/* try it unaligned
|
/* try it unaligned
|
do_module_burst_write(3'h2, 16'd5, 32'h2); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h2, 16'd5, 32'h2); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
do_module_burst_read(3'h2, 16'd4, 32'h4);
|
do_module_burst_read(3'h2, 16'd4, 32'h4);
|
#1000;
|
#1000;
|
*/
|
*/
|
|
|
////////////////////////////////////
|
////////////////////////////////////
|
// Test 32-bit WB access
|
// Test 32-bit WB access
|
failed = 0;
|
failed = 0;
|
$display("Testing WB 32-bit burst write at time %t", $time);
|
$display("Testing WB 32-bit burst write at time %t", $time);
|
do_module_burst_write(3'h4, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h4, 16'd16, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
$display("Testing WB 32-bit burst read at time %t", $time);
|
$display("Testing WB 32-bit burst read at time %t", $time);
|
do_module_burst_read(3'h4, 16'd16, 32'h0);
|
do_module_burst_read(3'h4, 16'd16, 32'h0);
|
#1000;
|
#1000;
|
for(i = 0; i < 16; i = i+1) begin
|
for(i = 0; i < 16; i = i+1) begin
|
if(static_data32[i] != input_data32[i]) begin
|
if(static_data32[i] != input_data32[i]) begin
|
failed = 1;
|
failed = 1;
|
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
|
$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
|
end
|
end
|
end
|
end
|
if(!failed) $display("32-bit read/write OK!");
|
if(!failed) $display("32-bit read/write OK!");
|
|
|
/* Try another address
|
/* Try another address
|
do_module_burst_write(3'h4, 16'd16, 32'h200); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h4, 16'd16, 32'h200); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
#1000;
|
#1000;
|
do_module_burst_read(3'h4, 16'd15, 32'h204);
|
do_module_burst_read(3'h4, 16'd15, 32'h204);
|
#1000;
|
#1000;
|
*/
|
*/
|
|
|
////////////////////////////////
|
////////////////////////////////
|
// Test error register
|
// Test error register
|
err_data = 33'h0;
|
err_data = 33'h0;
|
// Select and reset the error register
|
// Select and reset the error register
|
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
|
write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
|
i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
|
i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
|
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
|
read_module_internal_register(8'd33, err_data); // get the error register
|
read_module_internal_register(8'd33, err_data); // get the error register
|
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
|
$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
|
|
|
`endif // WB module supported
|
`endif // WB module supported
|
|
|
end
|
end
|
|
|
task initialize_memory;
|
task initialize_memory;
|
input [31:0] start_addr;
|
input [31:0] start_addr;
|
input [31:0] length;
|
input [31:0] length;
|
integer i;
|
integer i;
|
reg [31:0] addr;
|
reg [31:0] addr;
|
begin
|
begin
|
|
|
for (i=0; i<length; i=i+1)
|
for (i=0; i<length; i=i+1)
|
begin
|
begin
|
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
|
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
|
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
|
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
|
static_data8[i] <= i[7:0];
|
static_data8[i] <= i[7:0];
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Declaration and interconnection of components
|
// Declaration and interconnection of components
|
|
|
// Top module
|
// Top module
|
tap_top i_tap (
|
tap_top i_tap (
|
// JTAG pads
|
// JTAG pads
|
.tms_pad_i(jtag_tms_o),
|
.tms_pad_i(jtag_tms_o),
|
.tck_pad_i(jtag_tck_o),
|
.tck_pad_i(jtag_tck_o),
|
.trstn_pad_i(1'b1),
|
.trstn_pad_i(1'b1),
|
.tdi_pad_i(jtag_tdo_o),
|
.tdi_pad_i(jtag_tdo_o),
|
.tdo_pad_o(jtag_tdi_i),
|
.tdo_pad_o(jtag_tdi_i),
|
.tdo_padoe_o(),
|
.tdo_padoe_o(),
|
|
|
// TAP states
|
// TAP states
|
.test_logic_reset_o(dbg_rst),
|
.test_logic_reset_o(dbg_rst),
|
.run_test_idle_o(),
|
.run_test_idle_o(),
|
.shift_dr_o(shift_dr),
|
.shift_dr_o(shift_dr),
|
.pause_dr_o(pause_dr),
|
.pause_dr_o(pause_dr),
|
.update_dr_o(update_dr),
|
.update_dr_o(update_dr),
|
.capture_dr_o(capture_dr),
|
.capture_dr_o(capture_dr),
|
|
|
// Select signals for boundary scan or mbist
|
// Select signals for boundary scan or mbist
|
.extest_select_o(),
|
.extest_select_o(),
|
.sample_preload_select_o(),
|
.sample_preload_select_o(),
|
.mbist_select_o(),
|
.mbist_select_o(),
|
.debug_select_o(dbg_sel),
|
.debug_select_o(dbg_sel),
|
|
|
// TDO signal that is connected to TDI of sub-modules.
|
// TDO signal that is connected to TDI of sub-modules.
|
.tdo_o(dbg_tdo),
|
.tdo_o(dbg_tdo),
|
|
|
// TDI signals from sub-modules
|
// TDI signals from sub-modules
|
.debug_tdi_i(dbg_tdi), // from debug module
|
.debug_tdi_i(dbg_tdi), // from debug module
|
.bs_chain_tdi_i(1'b0), // from Boundary Scan Chain
|
.bs_chain_tdi_i(1'b0), // from Boundary Scan Chain
|
.mbist_tdi_i(1'b0) // from Mbist Chain
|
.mbist_tdi_i(1'b0) // from Mbist Chain
|
);
|
);
|
|
|
|
|
// Top module
|
// Top module
|
dbg_top i_dbg_module(
|
dbg_top i_dbg_module(
|
// JTAG signals
|
// JTAG signals
|
.tck_i(jtag_tck_o),
|
.tck_i(jtag_tck_o),
|
.tdi_i(dbg_tdo),
|
.tdi_i(dbg_tdo),
|
.tdo_o(dbg_tdi),
|
.tdo_o(dbg_tdi),
|
.rst_i(dbg_rst),
|
.rst_i(dbg_rst),
|
|
|
// TAP states
|
// TAP states
|
.shift_dr_i(shift_dr),
|
.shift_dr_i(shift_dr),
|
.pause_dr_i(pause_dr),
|
.pause_dr_i(pause_dr),
|
.update_dr_i(update_dr),
|
.update_dr_i(update_dr),
|
.capture_dr_i(capture_dr),
|
.capture_dr_i(capture_dr),
|
|
|
// Instructions
|
// Instructions
|
.debug_select_i(dbg_sel)
|
.debug_select_i(dbg_sel)
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// WISHBONE common signals
|
// WISHBONE common signals
|
,
|
,
|
.wb_clk_i(wb_clk_i),
|
.wb_clk_i(wb_clk_i),
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
.wb_adr_o(wb_adr),
|
.wb_adr_o(wb_adr),
|
.wb_dat_o(wb_dat_m),
|
.wb_dat_o(wb_dat_m),
|
.wb_dat_i(wb_dat_s),
|
.wb_dat_i(wb_dat_s),
|
.wb_cyc_o(wb_cyc),
|
.wb_cyc_o(wb_cyc),
|
.wb_stb_o(wb_stb),
|
.wb_stb_o(wb_stb),
|
.wb_sel_o(wb_sel),
|
.wb_sel_o(wb_sel),
|
.wb_we_o(wb_we),
|
.wb_we_o(wb_we),
|
.wb_ack_i(wb_ack),
|
.wb_ack_i(wb_ack),
|
.wb_cab_o(),
|
.wb_cab_o(),
|
.wb_err_i(wb_err),
|
.wb_err_i(wb_err),
|
.wb_cti_o(),
|
.wb_cti_o(),
|
.wb_bte_o()
|
.wb_bte_o()
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
// CPU signals
|
// CPU signals
|
,
|
,
|
.cpu0_clk_i(cpu0_clk),
|
.cpu0_clk_i(cpu0_clk),
|
.cpu0_addr_o(cpu0_addr),
|
.cpu0_addr_o(cpu0_addr),
|
.cpu0_data_i(cpu0_data_c),
|
.cpu0_data_i(cpu0_data_c),
|
.cpu0_data_o(cpu0_data_d),
|
.cpu0_data_o(cpu0_data_d),
|
.cpu0_bp_i(cpu0_bp),
|
.cpu0_bp_i(cpu0_bp),
|
.cpu0_stall_o(cpu0_stall),
|
.cpu0_stall_o(cpu0_stall),
|
.cpu0_stb_o(cpu0_stb),
|
.cpu0_stb_o(cpu0_stb),
|
.cpu0_we_o(cpu0_we),
|
.cpu0_we_o(cpu0_we),
|
.cpu0_ack_i(cpu0_ack),
|
.cpu0_ack_i(cpu0_ack),
|
.cpu0_rst_o(cpu0_rst)
|
.cpu0_rst_o(cpu0_rst)
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
`ifdef DBG_CPU1_SUPPORTED
|
// CPU signals
|
// CPU signals
|
,
|
,
|
.cpu1_clk_i(cpu1_clk),
|
.cpu1_clk_i(cpu1_clk),
|
.cpu1_addr_o(cpu1_addr),
|
.cpu1_addr_o(cpu1_addr),
|
.cpu1_data_i(cpu1_data_c),
|
.cpu1_data_i(cpu1_data_c),
|
.cpu1_data_o(cpu1_data_d),
|
.cpu1_data_o(cpu1_data_d),
|
.cpu1_bp_i(cpu1_bp),
|
.cpu1_bp_i(cpu1_bp),
|
.cpu1_stall_o(cpu1_stall),
|
.cpu1_stall_o(cpu1_stall),
|
.cpu1_stb_o(cpu1_stb),
|
.cpu1_stb_o(cpu1_stb),
|
.cpu1_we_o(cpu1_we),
|
.cpu1_we_o(cpu1_we),
|
.cpu1_ack_i(cpu1_ack),
|
.cpu1_ack_i(cpu1_ack),
|
.cpu1_rst_o(cpu1_rst)
|
.cpu1_rst_o(cpu1_rst)
|
`endif
|
`endif
|
|
|
);
|
);
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// The 'wishbone' may be just a p2p connection to a simple RAM
|
// The 'wishbone' may be just a p2p connection to a simple RAM
|
/*
|
/*
|
onchip_ram_top i_ocram (
|
onchip_ram_top i_ocram (
|
.wb_clk_i(wb_clk_i),
|
.wb_clk_i(wb_clk_i),
|
.wb_rst_i(wb_rst_i),
|
.wb_rst_i(wb_rst_i),
|
.wb_dat_i(wb_dat_m),
|
.wb_dat_i(wb_dat_m),
|
.wb_dat_o(wb_dat_s),
|
.wb_dat_o(wb_dat_s),
|
.wb_adr_i(wb_adr[11:0]),
|
.wb_adr_i(wb_adr[11:0]),
|
.wb_sel_i(wb_sel),
|
.wb_sel_i(wb_sel),
|
.wb_we_i(wb_we),
|
.wb_we_i(wb_we),
|
.wb_cyc_i(wb_cyc),
|
.wb_cyc_i(wb_cyc),
|
.wb_stb_i(wb_stb),
|
.wb_stb_i(wb_stb),
|
.wb_ack_o(wb_ack),
|
.wb_ack_o(wb_ack),
|
.wb_err_o(wb_err)
|
.wb_err_o(wb_err)
|
);
|
);
|
*/
|
*/
|
|
|
wb_slave_behavioral i_wb
|
wb_slave_behavioral i_wb
|
(
|
(
|
.CLK_I(wb_clk_i),
|
.CLK_I(wb_clk_i),
|
.RST_I(wb_rst_i),
|
.RST_I(wb_rst_i),
|
.ACK_O(wb_ack),
|
.ACK_O(wb_ack),
|
.ADR_I(wb_adr),
|
.ADR_I(wb_adr),
|
.CYC_I(wb_cyc),
|
.CYC_I(wb_cyc),
|
.DAT_O(wb_dat_s),
|
.DAT_O(wb_dat_s),
|
.DAT_I(wb_dat_m),
|
.DAT_I(wb_dat_m),
|
.ERR_O(wb_err),
|
.ERR_O(wb_err),
|
.RTY_O(),
|
.RTY_O(),
|
.SEL_I(wb_sel),
|
.SEL_I(wb_sel),
|
.STB_I(wb_stb),
|
.STB_I(wb_stb),
|
.WE_I(wb_we),
|
.WE_I(wb_we),
|
.CAB_I(1'b0)
|
.CAB_I(1'b0)
|
);
|
);
|
`endif
|
`endif
|
|
|
|
|
`ifdef DBG_CPU0_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
// Instantiate a behavioral model of the CPU SPR bus
|
// Instantiate a behavioral model of the CPU SPR bus
|
cpu_behavioral cpu0_i (
|
cpu_behavioral cpu0_i (
|
.cpu_rst_i(cpu0_rst),
|
.cpu_rst_i(cpu0_rst),
|
.cpu_clk_o(cpu0_clk),
|
.cpu_clk_o(cpu0_clk),
|
.cpu_addr_i(cpu0_addr),
|
.cpu_addr_i(cpu0_addr),
|
.cpu_data_o(cpu0_data_c),
|
.cpu_data_o(cpu0_data_c),
|
.cpu_data_i(cpu0_data_d),
|
.cpu_data_i(cpu0_data_d),
|
.cpu_bp_o(cpu0_bp),
|
.cpu_bp_o(cpu0_bp),
|
.cpu_stall_i(cpu0_stall),
|
.cpu_stall_i(cpu0_stall),
|
.cpu_stb_i(cpu0_stb),
|
.cpu_stb_i(cpu0_stb),
|
.cpu_we_i(cpu0_we),
|
.cpu_we_i(cpu0_we),
|
.cpu_ack_o(cpu0_ack),
|
.cpu_ack_o(cpu0_ack),
|
.cpu_rst_o(cpu0_rst)
|
.cpu_rst_o(cpu0_rst)
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
`ifdef DBG_CPU1_SUPPORTED
|
// Instantiate a behavioral model of the CPU SPR bus
|
// Instantiate a behavioral model of the CPU SPR bus
|
cpu_behavioral cpu1_i (
|
cpu_behavioral cpu1_i (
|
.cpu_rst_i(cpu1_rst),
|
.cpu_rst_i(cpu1_rst),
|
.cpu_clk_o(cpu1_clk),
|
.cpu_clk_o(cpu1_clk),
|
.cpu_addr_i(cpu1_addr),
|
.cpu_addr_i(cpu1_addr),
|
.cpu_data_o(cpu1_data_c),
|
.cpu_data_o(cpu1_data_c),
|
.cpu_data_i(cpu1_data_d),
|
.cpu_data_i(cpu1_data_d),
|
.cpu_bp_o(cpu1_bp),
|
.cpu_bp_o(cpu1_bp),
|
.cpu_stall_i(cpu1_stall),
|
.cpu_stall_i(cpu1_stall),
|
.cpu_stb_i(cpu1_stb),
|
.cpu_stb_i(cpu1_stb),
|
.cpu_we_i(cpu1_we),
|
.cpu_we_i(cpu1_we),
|
.cpu_ack_o(cpu1_ack),
|
.cpu_ack_o(cpu1_ack),
|
.cpu_rst_o(cpu1_rst)
|
.cpu_rst_o(cpu1_rst)
|
);
|
);
|
`endif
|
`endif
|
|
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
// Higher-level chain manipulation functions
|
// Higher-level chain manipulation functions
|
|
|
// calculate the CRC, up to 32 bits at a time
|
// calculate the CRC, up to 32 bits at a time
|
task compute_crc;
|
task compute_crc;
|
input [31:0] crc_in;
|
input [31:0] crc_in;
|
input [31:0] data_in;
|
input [31:0] data_in;
|
input [5:0] length_bits;
|
input [5:0] length_bits;
|
output [31:0] crc_out;
|
output [31:0] crc_out;
|
integer i;
|
integer i;
|
reg [31:0] d;
|
reg [31:0] d;
|
reg [31:0] c;
|
reg [31:0] c;
|
begin
|
begin
|
crc_out = crc_in;
|
crc_out = crc_in;
|
for(i = 0; i < length_bits; i = i+1) begin
|
for(i = 0; i < length_bits; i = i+1) begin
|
d = (data_in[i]) ? 32'hffffffff : 32'h0;
|
d = (data_in[i]) ? 32'hffffffff : 32'h0;
|
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
|
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
|
//crc_out = {crc_out[30:0], 1'b0}; // original
|
//crc_out = {crc_out[30:0], 1'b0}; // original
|
crc_out = crc_out >> 1;
|
crc_out = crc_out >> 1;
|
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
|
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
|
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
|
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task check_idcode;
|
task check_idcode;
|
reg [63:0] readdata;
|
reg [63:0] readdata;
|
reg[31:0] idcode;
|
reg[31:0] idcode;
|
begin
|
begin
|
set_ir(`IDCODE);
|
set_ir(`IDCODE);
|
|
|
// Read the IDCODE in the DR
|
// Read the IDCODE in the DR
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
|
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
idcode = readdata[31:0];
|
idcode = readdata[31:0];
|
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
|
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
|
end
|
end
|
endtask;
|
endtask;
|
|
|
task select_debug_module;
|
task select_debug_module;
|
input [1:0] moduleid;
|
input [1:0] moduleid;
|
reg validid;
|
reg validid;
|
begin
|
begin
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
|
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
|
|
$display("Selecting module (%0x)", moduleid);
|
$display("Selecting module (%0x)", moduleid);
|
|
|
// Read back the status to make sure a valid chain is selected
|
// Read back the status to make sure a valid chain is selected
|
/* Pointless, the newly selected module would respond instead...
|
/* Pointless, the newly selected module would respond instead...
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
|
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
|
|
if(validid) $display("Selected valid module (%0x)", moduleid);
|
if(validid) $display("Selected valid module (%0x)", moduleid);
|
else $display("Failed to select module (%0x)", moduleid);
|
else $display("Failed to select module (%0x)", moduleid);
|
*/
|
*/
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task send_module_burst_command;
|
task send_module_burst_command;
|
input [3:0] opcode;
|
input [3:0] opcode;
|
input [31:0] address;
|
input [31:0] address;
|
input [15:0] burstlength;
|
input [15:0] burstlength;
|
reg [63:0] streamdata;
|
reg [63:0] streamdata;
|
begin
|
begin
|
streamdata = {11'h0,1'b0,opcode,address,burstlength};
|
streamdata = {11'h0,1'b0,opcode,address,burstlength};
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
|
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
task select_module_internal_register; // Really just a read, with discarded data
|
task select_module_internal_register; // Really just a read, with discarded data
|
input [31:0] regidx;
|
input [31:0] regidx;
|
input [7:0] len; // the length of the register index data, we assume not more than 32
|
input [7:0] len; // the length of the register index data, we assume not more than 32
|
reg[63:0] streamdata;
|
reg[63:0] streamdata;
|
begin
|
begin
|
streamdata = 64'h0;
|
streamdata = 64'h0;
|
streamdata = streamdata | regidx;
|
streamdata = streamdata | regidx;
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
|
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task read_module_internal_register; // We assume the register is already selected
|
task read_module_internal_register; // We assume the register is already selected
|
//input [31:0] regidx;
|
//input [31:0] regidx;
|
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
|
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
|
output [63:0] instream;
|
output [63:0] instream;
|
reg [63:0] bitmask;
|
reg [63:0] bitmask;
|
begin
|
begin
|
instream = 64'h0;
|
instream = 64'h0;
|
// We shift out all 0's, which is a NOP to the debug unit
|
// We shift out all 0's, which is a NOP to the debug unit
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
// Shift at least 5 bits, as this is the min, for a valid NOP
|
// Shift at least 5 bits, as this is the min, for a valid NOP
|
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
|
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
bitmask = 64'hffffffffffffffff;
|
bitmask = 64'hffffffffffffffff;
|
bitmask = bitmask << len;
|
bitmask = bitmask << len;
|
bitmask = ~bitmask;
|
bitmask = ~bitmask;
|
instream = instream & bitmask; // Cut off any unwanted excess bits
|
instream = instream & bitmask; // Cut off any unwanted excess bits
|
end
|
end
|
endtask
|
endtask
|
|
|
task write_module_internal_register;
|
task write_module_internal_register;
|
input [31:0] regidx; // the length of the register index data
|
input [31:0] regidx; // the length of the register index data
|
input [7:0] idxlen;
|
input [7:0] idxlen;
|
input [63:0] writedata;
|
input [63:0] writedata;
|
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
|
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
|
reg[63:0] streamdata;
|
reg[63:0] streamdata;
|
begin
|
begin
|
streamdata = 64'h0; // This will 0 the toplevel/module select bit
|
streamdata = 64'h0; // This will 0 the toplevel/module select bit
|
streamdata = streamdata | writedata;
|
streamdata = streamdata | writedata;
|
streamdata = streamdata | (regidx << datalen);
|
streamdata = streamdata | (regidx << datalen);
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
|
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
|
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(`JTAG_TMS_bit); // update_dr
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
// This includes the sending of the burst command
|
// This includes the sending of the burst command
|
task do_module_burst_read;
|
task do_module_burst_read;
|
input [5:0] word_size_bytes;
|
input [5:0] word_size_bytes;
|
input [15:0] word_count;
|
input [15:0] word_count;
|
input [31:0] start_address;
|
input [31:0] start_address;
|
reg [3:0] opcode;
|
reg [3:0] opcode;
|
reg status;
|
reg status;
|
reg [63:0] instream;
|
reg [63:0] instream;
|
integer i;
|
integer i;
|
integer j;
|
integer j;
|
reg [31:0] crc_calc_i;
|
reg [31:0] crc_calc_i;
|
reg [31:0] crc_calc_o; // temp signal...
|
reg [31:0] crc_calc_o; // temp signal...
|
reg [31:0] crc_read;
|
reg [31:0] crc_read;
|
reg [5:0] word_size_bits;
|
reg [5:0] word_size_bits;
|
begin
|
begin
|
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
instream = 64'h0;
|
instream = 64'h0;
|
word_size_bits = word_size_bytes << 3;
|
word_size_bits = word_size_bytes << 3;
|
crc_calc_i = 32'hffffffff;
|
crc_calc_i = 32'hffffffff;
|
|
|
// Send the command
|
// Send the command
|
case (word_size_bytes)
|
case (word_size_bytes)
|
3'h1: opcode = `DBG_WB_CMD_BREAD8;
|
3'h1: opcode = `DBG_WB_CMD_BREAD8;
|
3'h2: opcode = `DBG_WB_CMD_BREAD16;
|
3'h2: opcode = `DBG_WB_CMD_BREAD16;
|
3'h4: opcode = `DBG_WB_CMD_BREAD32;
|
3'h4: opcode = `DBG_WB_CMD_BREAD32;
|
default:
|
default:
|
begin
|
begin
|
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
opcode = `DBG_WB_CMD_BREAD32;
|
opcode = `DBG_WB_CMD_BREAD32;
|
end
|
end
|
endcase
|
endcase
|
|
|
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
|
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
|
|
|
// Get us back to shift_dr mode to read a burst
|
// Get us back to shift_dr mode to read a burst
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
|
|
// Now, repeat...
|
// Now, repeat...
|
for(i = 0; i < word_count; i=i+1) begin
|
for(i = 0; i < word_count; i=i+1) begin
|
// Get 1 status bit, then word_size_bytes*8 bits
|
// Get 1 status bit, then word_size_bytes*8 bits
|
status = 1'b0;
|
status = 1'b0;
|
j = 0;
|
j = 0;
|
while(!status) begin
|
while(!status) begin
|
read_write_bit(3'h0, status);
|
read_write_bit(3'h0, status);
|
j = j + 1;
|
j = j + 1;
|
end
|
end
|
|
|
if(j > 1) begin
|
if(j > 1) begin
|
$display("Took %0d tries before good status bit during burst read", j);
|
$display("Took %0d tries before good status bit during burst read", j);
|
end
|
end
|
|
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
//$display("Read 0x%0x", instream[31:0]);
|
//$display("Read 0x%0x", instream[31:0]);
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
crc_calc_i = crc_calc_o;
|
crc_calc_i = crc_calc_o;
|
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
|
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
|
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
|
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
|
else input_data32[i] = instream[31:0];
|
else input_data32[i] = instream[31:0];
|
end
|
end
|
|
|
// Read the data CRC from the debug module.
|
// Read the data CRC from the debug module.
|
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
|
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
|
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
|
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
|
else $display("CRC OK!");
|
else $display("CRC OK!");
|
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
// Finally, shift out 5 0's, to make the next command a NOP
|
// Not necessary, debug unit won't latch a new opcode at the end of a burst
|
// Not necessary, debug unit won't latch a new opcode at the end of a burst
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task do_module_burst_write;
|
task do_module_burst_write;
|
input [5:0] word_size_bytes;
|
input [5:0] word_size_bytes;
|
input [15:0] word_count;
|
input [15:0] word_count;
|
input [31:0] start_address;
|
input [31:0] start_address;
|
reg [3:0] opcode;
|
reg [3:0] opcode;
|
reg status;
|
reg status;
|
reg [63:0] dataword;
|
reg [63:0] dataword;
|
integer i;
|
integer i;
|
integer j;
|
integer j;
|
reg [31:0] crc_calc_i;
|
reg [31:0] crc_calc_i;
|
reg [31:0] crc_calc_o;
|
reg [31:0] crc_calc_o;
|
reg crc_match;
|
reg crc_match;
|
reg [5:0] word_size_bits;
|
reg [5:0] word_size_bits;
|
begin
|
begin
|
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
word_size_bits = word_size_bytes << 3;
|
word_size_bits = word_size_bytes << 3;
|
crc_calc_i = 32'hffffffff;
|
crc_calc_i = 32'hffffffff;
|
|
|
// Send the command
|
// Send the command
|
case (word_size_bytes)
|
case (word_size_bytes)
|
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
|
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
|
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
|
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
|
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
|
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
|
default:
|
default:
|
begin
|
begin
|
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
opcode = `DBG_WB_CMD_BWRITE32;
|
opcode = `DBG_WB_CMD_BWRITE32;
|
end
|
end
|
endcase
|
endcase
|
|
|
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
|
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
|
|
|
// Get us back to shift_dr mode to write a burst
|
// Get us back to shift_dr mode to write a burst
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
|
|
|
|
// Write a start bit (a 1) so it knows when to start counting
|
// Write a start bit (a 1) so it knows when to start counting
|
write_bit(`JTAG_TDO_bit);
|
write_bit(`JTAG_TDO_bit);
|
|
|
// Now, repeat...
|
// Now, repeat...
|
for(i = 0; i < word_count; i=i+1) begin
|
for(i = 0; i < word_count; i=i+1) begin
|
// Write word_size_bytes*8 bits, then get 1 status bit
|
// Write word_size_bytes*8 bits, then get 1 status bit
|
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
|
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
|
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
|
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
|
else dataword = {56'h0, static_data8[i]};
|
else dataword = {56'h0, static_data8[i]};
|
|
|
|
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
crc_calc_i = crc_calc_o;
|
crc_calc_i = crc_calc_o;
|
|
|
// Check if WB bus is ready
|
// Check if WB bus is ready
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
status = 1'b0;
|
status = 1'b0;
|
read_write_bit(3'h0, status);
|
read_write_bit(3'h0, status);
|
|
|
if(!status) begin
|
if(!status) begin
|
$display("Bad status bit during burst write, index %d", i);
|
$display("Bad status bit during burst write, index %d", i);
|
end
|
end
|
|
|
|
|
//$display("Wrote 0x%0x", dataword);
|
//$display("Wrote 0x%0x", dataword);
|
end
|
end
|
|
|
// Send the CRC we computed
|
// Send the CRC we computed
|
jtag_write_stream(crc_calc_o, 6'd32,0);
|
jtag_write_stream(crc_calc_o, 6'd32,0);
|
|
|
// Read the 'CRC match' bit, and go to exit1_dr
|
// Read the 'CRC match' bit, and go to exit1_dr
|
read_write_bit(`JTAG_TMS_bit, crc_match);
|
read_write_bit(`JTAG_TMS_bit, crc_match);
|
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
|
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
|
else $display("CRC OK!");
|
else $display("CRC OK!");
|
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
// Finally, shift out 5 0's, to make the next command a NOP
|
// Not necessary, module will not latch new opcode during burst
|
// Not necessary, module will not latch new opcode during burst
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
|
|
// Puts a value in the TAP IR, assuming we start in IDLE state.
|
// Puts a value in the TAP IR, assuming we start in IDLE state.
|
// Returns to IDLE state when finished
|
// Returns to IDLE state when finished
|
task set_ir;
|
task set_ir;
|
input [3:0] irval;
|
input [3:0] irval;
|
begin
|
begin
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_ir_scan
|
write_bit(`JTAG_TMS_bit); // select_ir_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
|
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(`JTAG_TMS_bit); // update_ir
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
// Resets the TAP and puts it into idle mode
|
// Resets the TAP and puts it into idle mode
|
task reset_jtag;
|
task reset_jtag;
|
integer i;
|
integer i;
|
begin
|
begin
|
for(i = 0; i < 8; i=i+1) begin
|
for(i = 0; i < 8; i=i+1) begin
|
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
|
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
|
end
|
end
|
write_bit(3'h0); // idle
|
write_bit(3'h0); // idle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
// Tasks to write or read-write a string of data
|
// Tasks to write or read-write a string of data
|
|
|
task jtag_write_stream;
|
task jtag_write_stream;
|
input [63:0] stream;
|
input [63:0] stream;
|
input [7:0] len;
|
input [7:0] len;
|
input set_last_bit;
|
input set_last_bit;
|
integer i;
|
integer i;
|
integer databit;
|
integer databit;
|
reg [2:0] bits;
|
reg [2:0] bits;
|
begin
|
begin
|
for(i = 0; i < (len-1); i=i+1) begin
|
for(i = 0; i < (len-1); i=i+1) begin
|
databit = (stream >> i) & 1'h1;
|
databit = (stream >> i) & 1'h1;
|
bits = databit << `JTAG_TDO;
|
bits = databit << `JTAG_TDO;
|
write_bit(bits);
|
write_bit(bits);
|
end
|
end
|
|
|
databit = (stream >> i) & 1'h1;
|
databit = (stream >> i) & 1'h1;
|
bits = databit << `JTAG_TDO;
|
bits = databit << `JTAG_TDO;
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
write_bit(bits);
|
write_bit(bits);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task jtag_read_write_stream;
|
task jtag_read_write_stream;
|
input [63:0] stream;
|
input [63:0] stream;
|
input [7:0] len;
|
input [7:0] len;
|
input set_last_bit;
|
input set_last_bit;
|
output [63:0] instream;
|
output [63:0] instream;
|
integer i;
|
integer i;
|
integer databit;
|
integer databit;
|
reg [2:0] bits;
|
reg [2:0] bits;
|
reg inbit;
|
reg inbit;
|
begin
|
begin
|
instream = 64'h0;
|
instream = 64'h0;
|
for(i = 0; i < (len-1); i=i+1) begin
|
for(i = 0; i < (len-1); i=i+1) begin
|
databit = (stream >> i) & 1'h1;
|
databit = (stream >> i) & 1'h1;
|
bits = databit << `JTAG_TDO;
|
bits = databit << `JTAG_TDO;
|
read_write_bit(bits, inbit);
|
read_write_bit(bits, inbit);
|
instream = (instream | (inbit << i));
|
instream = (instream | (inbit << i));
|
end
|
end
|
|
|
databit = (stream >> i) & 1'h1;
|
databit = (stream >> i) & 1'h1;
|
bits = databit << `JTAG_TDO;
|
bits = databit << `JTAG_TDO;
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
read_write_bit(bits, inbit);
|
read_write_bit(bits, inbit);
|
instream = (instream | (inbit << (len-1)));
|
instream = (instream | (inbit << (len-1)));
|
end
|
end
|
endtask
|
endtask
|
|
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
// Tasks which write or readwrite a single bit (including clocking)
|
// Tasks which write or readwrite a single bit (including clocking)
|
|
|
task write_bit;
|
task write_bit;
|
input [2:0] bitvals;
|
input [2:0] bitvals;
|
begin
|
begin
|
|
|
// Set data
|
// Set data
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
`wait_jtag_period;
|
`wait_jtag_period;
|
|
|
// Raise clock
|
// Raise clock
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
`wait_jtag_period;
|
`wait_jtag_period;
|
|
|
// drop clock (making output available in the SHIFT_xR states)
|
// drop clock (making output available in the SHIFT_xR states)
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
`wait_jtag_period;
|
`wait_jtag_period;
|
end
|
end
|
endtask
|
endtask
|
|
|
task read_write_bit;
|
task read_write_bit;
|
input [2:0] bitvals;
|
input [2:0] bitvals;
|
output l_tdi_val;
|
output l_tdi_val;
|
begin
|
begin
|
|
|
// read bit state
|
// read bit state
|
l_tdi_val <= jtag_tdi_i;
|
l_tdi_val <= jtag_tdi_i;
|
|
|
// Set data
|
// Set data
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
`wait_jtag_period;
|
`wait_jtag_period;
|
|
|
// Raise clock
|
// Raise clock
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
`wait_jtag_period;
|
`wait_jtag_period;
|
|
|
// drop clock (making output available in the SHIFT_xR states)
|
// drop clock (making output available in the SHIFT_xR states)
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
`wait_jtag_period;
|
`wait_jtag_period;
|
end
|
end
|
endtask
|
endtask
|
|
|
/////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////
|
// Basic functions to set the state of the JTAG TAP I/F bits
|
// Basic functions to set the state of the JTAG TAP I/F bits
|
|
|
task jtag_out;
|
task jtag_out;
|
input [2:0] bitvals;
|
input [2:0] bitvals;
|
begin
|
begin
|
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task jtag_inout;
|
task jtag_inout;
|
input [2:0] bitvals;
|
input [2:0] bitvals;
|
output l_tdi_val;
|
output l_tdi_val;
|
begin
|
begin
|
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
|
|
l_tdi_val <= jtag_tdi_i;
|
l_tdi_val <= jtag_tdi_i;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|