//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// syncreg.v ////
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//// syncreg.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Synchronizes a register between two clock domains ////
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//// Synchronizes a register between two clock domains ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors ////
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//// Copyright (C) 2010 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// This is a synchronization element between two clock domains. Domain A
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// This is a synchronization element between two clock domains. Domain A
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// is considered the 'source' domain (produces the data), and Domain B
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// is considered the 'source' domain (produces the data), and Domain B
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// is considered the 'destination' domain (consumes the data). It is assumed
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// is considered the 'destination' domain (consumes the data). It is assumed
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// that clock A is faster than clock B, but this element will work
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// that clock A is faster than clock B, but this element will work
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// regardless. The idea here is NOT to insure that domain B sees every
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// regardless. The idea here is NOT to insure that domain B sees every
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// change to the value generated by domain A. Rather, this device
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// change to the value generated by domain A. Rather, this device
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// attempts to keep the value seen by domain B as current as possible,
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// attempts to keep the value seen by domain B as current as possible,
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// always updating to the latest value of the input in domain A.
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// always updating to the latest value of the input in domain A.
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// Thus, there may be dozens or hundreds of changes to register A
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// Thus, there may be dozens or hundreds of changes to register A
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// which are not seen by domain B. There is no external acknowledge
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// which are not seen by domain B. There is no external acknowledge
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// of receipt from domain B. Domain B simply wants the most current
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// of receipt from domain B. Domain B simply wants the most current
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// value of register A possible at any given time.
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// value of register A possible at any given time.
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// Note the reset is asynchronous; this is necessary to coordinate between
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// Note the reset is asynchronous; this is necessary to coordinate between
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// two clock domains which may have separate reset signals. I could find
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// two clock domains which may have separate reset signals. I could find
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// no other way to insure correct initialization with two separate
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// no other way to insure correct initialization with two separate
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// reset signals.
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// reset signals.
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//
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//
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// Ports:
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// Ports:
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// CLKA: Clock for the source domain
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// CLKA: Clock for the source domain
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// CLKB: Clock for the destination domain
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// CLKB: Clock for the destination domain
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// RST: Asynchronously resets all sync elements, prepares
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// RST: Asynchronously resets all sync elements, prepares
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// unit for operation.
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// unit for operation.
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// DATA_IN: Data input from clock domain A
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// DATA_IN: Data input from clock domain A
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// DATA_OUT: Data output to clock domain B
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// DATA_OUT: Data output to clock domain B
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//
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//
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// Top module
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// Top module
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module syncreg (
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module syncreg (
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CLKA,
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CLKA,
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CLKB,
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CLKB,
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RST,
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RST,
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DATA_IN,
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DATA_IN,
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DATA_OUT
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DATA_OUT
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);
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);
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input CLKA;
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input CLKA;
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input CLKB;
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input CLKB;
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input RST;
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input RST;
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input [3:0] DATA_IN;
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input [3:0] DATA_IN;
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output [3:0] DATA_OUT;
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output [3:0] DATA_OUT;
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reg [3:0] regA;
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reg [3:0] regA;
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reg [3:0] regB;
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reg [3:0] regB;
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reg strobe_toggle;
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reg strobe_toggle;
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reg ack_toggle;
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reg ack_toggle;
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wire A_not_equal;
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wire A_not_equal;
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wire A_enable;
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wire A_enable;
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wire strobe_sff_out;
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wire strobe_sff_out;
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wire ack_sff_out;
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wire ack_sff_out;
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wire [3:0] DATA_OUT;
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wire [3:0] DATA_OUT;
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// Combinatorial assignments
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// Combinatorial assignments
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assign A_enable = A_not_equal & ack_sff_out;
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assign A_enable = A_not_equal & ack_sff_out;
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assign A_not_equal = !(DATA_IN == regA);
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assign A_not_equal = !(DATA_IN == regA);
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assign DATA_OUT = regB;
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assign DATA_OUT = regB;
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// register A (latches input any time it changes)
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// register A (latches input any time it changes)
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always @ (posedge CLKA or posedge RST)
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always @ (posedge CLKA or posedge RST)
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begin
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begin
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if(RST)
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if(RST)
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regA <= 4'b0;
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regA <= 4'b0;
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else if(A_enable)
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else if(A_enable)
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regA <= DATA_IN;
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regA <= DATA_IN;
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end
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end
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// register B (latches data from regA when enabled by the strobe SFF)
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// register B (latches data from regA when enabled by the strobe SFF)
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always @ (posedge CLKB or posedge RST)
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always @ (posedge CLKB or posedge RST)
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begin
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begin
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if(RST)
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if(RST)
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regB <= 4'b0;
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regB <= 4'b0;
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else if(strobe_sff_out)
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else if(strobe_sff_out)
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regB <= regA;
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regB <= regA;
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end
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end
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// 'strobe' toggle FF
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// 'strobe' toggle FF
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always @ (posedge CLKA or posedge RST)
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always @ (posedge CLKA or posedge RST)
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begin
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begin
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if(RST)
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if(RST)
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strobe_toggle <= 1'b0;
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strobe_toggle <= 1'b0;
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else if(A_enable)
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else if(A_enable)
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strobe_toggle <= ~strobe_toggle;
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strobe_toggle <= ~strobe_toggle;
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end
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end
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// 'ack' toggle FF
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// 'ack' toggle FF
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// This is set to '1' at reset, to initialize the unit.
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// This is set to '1' at reset, to initialize the unit.
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always @ (posedge CLKB or posedge RST)
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always @ (posedge CLKB or posedge RST)
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begin
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begin
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if(RST)
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if(RST)
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ack_toggle <= 1'b1;
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ack_toggle <= 1'b1;
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else if (strobe_sff_out)
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else if (strobe_sff_out)
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ack_toggle <= ~ack_toggle;
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ack_toggle <= ~ack_toggle;
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end
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end
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// 'strobe' sync element
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// 'strobe' sync element
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syncflop strobe_sff (
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syncflop strobe_sff (
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.DEST_CLK (CLKB),
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.DEST_CLK (CLKB),
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.D_SET (1'b0),
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.D_SET (1'b0),
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.D_RST (strobe_sff_out),
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.D_RST (strobe_sff_out),
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.RESET (RST),
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.RESET (RST),
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.TOGGLE_IN (strobe_toggle),
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.TOGGLE_IN (strobe_toggle),
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.D_OUT (strobe_sff_out)
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.D_OUT (strobe_sff_out)
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);
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);
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// 'ack' sync element
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// 'ack' sync element
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syncflop ack_sff (
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syncflop ack_sff (
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.DEST_CLK (CLKA),
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.DEST_CLK (CLKA),
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.D_SET (1'b0),
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.D_SET (1'b0),
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.D_RST (A_enable),
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.D_RST (A_enable),
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.RESET (RST),
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.RESET (RST),
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.TOGGLE_IN (ack_toggle),
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.TOGGLE_IN (ack_toggle),
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.D_OUT (ack_sff_out)
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.D_OUT (ack_sff_out)
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);
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);
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endmodule
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endmodule
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