/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* This verilog file is a part of the Boundary Scan Implementation and comes in *
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* This verilog file is a part of the Boundary Scan Implementation and comes in *
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* a pack with several other files. It is fully IEEE 1149.1 compliant. *
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* a pack with several other files. It is fully IEEE 1149.1 compliant. *
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* For details check www.opencores.org (pdf files, bsdl file, etc.) *
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* For details check www.opencores.org (pdf files, bsdl file, etc.) *
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* *
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* *
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* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
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* Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG *
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* *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* (at your option) any later version. *
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* *
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* *
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* See the file COPYING for the full details of the license. *
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* See the file COPYING for the full details of the license. *
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* *
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* *
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* OPENCORES.ORG is looking for new open source IP cores and developers that *
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* OPENCORES.ORG is looking for new open source IP cores and developers that *
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* would like to help in our mission. *
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* would like to help in our mission. *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Output Cell: *
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* Output Cell: *
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* *
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* *
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* FromCore: Value that comes from on-chip logic and goes to pin *
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* FromCore: Value that comes from on-chip logic and goes to pin *
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* FromPreviousBSCell: Value from previous boundary scan cell *
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* FromPreviousBSCell: Value from previous boundary scan cell *
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* ToNextBSCell: Value for next boundary scan cell *
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* ToNextBSCell: Value for next boundary scan cell *
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* CaptureDR, ShiftDR, UpdateDR: TAP states *
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* CaptureDR, ShiftDR, UpdateDR: TAP states *
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* extest: Instruction Register Command *
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* extest: Instruction Register Command *
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* TCK: Test Clock *
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* TCK: Test Clock *
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* TristatedPin: Signal from core is connected to this output pin via BS *
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* TristatedPin: Signal from core is connected to this output pin via BS *
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* FromOutputEnable: This pin comes from core or ControlCell *
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* FromOutputEnable: This pin comes from core or ControlCell *
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* *
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* *
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* Signal that is connected to TristatedPin comes from core or BS chain. *
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* Signal that is connected to TristatedPin comes from core or BS chain. *
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* Tristate control is generated in core or BS chain (ControlCell). *
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* Tristate control is generated in core or BS chain (ControlCell). *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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// This is not a top module
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// This is not a top module
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module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
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module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin);
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input FromCore;
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input FromCore;
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input FromPreviousBSCell;
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input FromPreviousBSCell;
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input CaptureDR;
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input CaptureDR;
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input ShiftDR;
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input ShiftDR;
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input UpdateDR;
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input UpdateDR;
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input extest;
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input extest;
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input TCK;
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input TCK;
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input FromOutputEnable;
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input FromOutputEnable;
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reg Latch;
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reg Latch;
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output ToNextBSCell;
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output ToNextBSCell;
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reg ToNextBSCell;
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reg ToNextBSCell;
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output TristatedPin;
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output TristatedPin;
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reg ShiftedControl;
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reg ShiftedControl;
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wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
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wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell;
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always @ (posedge TCK)
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always @ (posedge TCK)
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begin
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begin
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if(CaptureDR | ShiftDR)
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if(CaptureDR | ShiftDR)
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Latch<=SelectedInput;
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Latch<=SelectedInput;
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end
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end
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always @ (negedge TCK)
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always @ (negedge TCK)
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begin
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begin
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ToNextBSCell<=Latch;
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ToNextBSCell<=Latch;
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end
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end
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always @ (negedge TCK)
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always @ (negedge TCK)
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begin
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begin
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if(UpdateDR)
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if(UpdateDR)
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ShiftedControl<=ToNextBSCell;
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ShiftedControl<=ToNextBSCell;
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end
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end
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wire MuxedSignal = extest? ShiftedControl : FromCore;
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wire MuxedSignal = extest? ShiftedControl : FromCore;
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assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
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assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz;
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